Use standard MII register definitions from mii.h. No binary change.
This commit is contained in:
jakllsch
parent
d5fd80ad0d
commit
393ce9b83e
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@ -1,4 +1,4 @@
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/* $NetBSD: rgephy.c,v 1.28 2009/08/23 13:41:06 tsutsui Exp $ */
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/* $NetBSD: rgephy.c,v 1.29 2010/07/18 03:00:39 jakllsch Exp $ */
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/*
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* Copyright (c) 2003
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@ -33,7 +33,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.28 2009/08/23 13:41:06 tsutsui Exp $");
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__KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.29 2010/07/18 03:00:39 jakllsch Exp $");
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/*
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@ -203,9 +203,8 @@ rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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rgephy_reset(sc); /* XXX hardware bug work-around */
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anar = PHY_READ(sc, RGEPHY_MII_ANAR);
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anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
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RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10);
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anar = PHY_READ(sc, MII_ANAR);
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anar &= ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10);
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_AUTO:
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@ -213,38 +212,37 @@ rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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/*
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* If we're already in auto mode, just return.
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*/
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if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
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if (PHY_READ(sc, MII_BMCR) & BMCR_AUTOEN)
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return 0;
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#endif
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(void)rgephy_mii_phy_auto(sc);
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break;
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case IFM_1000_T:
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speed = RGEPHY_S1000;
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speed = BMCR_S1000;
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goto setit;
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case IFM_100_TX:
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speed = RGEPHY_S100;
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anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX;
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speed = BMCR_S100;
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anar |= ANAR_TX_FD | ANAR_TX;
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goto setit;
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case IFM_10_T:
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speed = RGEPHY_S10;
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anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10;
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speed = BMCR_S10;
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anar |= ANAR_10_FD | ANAR_10;
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setit:
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rgephy_loop(sc);
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if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
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speed |= RGEPHY_BMCR_FDX;
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gig = RGEPHY_1000CTL_AFD;
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anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10);
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speed |= BMCR_FDX;
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gig = GTCR_ADV_1000TFDX;
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anar &= ~(ANAR_TX | ANAR_10);
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} else {
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gig = RGEPHY_1000CTL_AHD;
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anar &=
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~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD);
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gig = GTCR_ADV_1000THDX;
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anar &= ~(ANAR_TX_FD | ANAR_10_FD);
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}
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) {
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PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
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PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
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PHY_WRITE(sc, RGEPHY_MII_BMCR, speed |
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RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
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PHY_WRITE(sc, MII_100T2CR, 0);
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PHY_WRITE(sc, MII_ANAR, anar);
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PHY_WRITE(sc, MII_BMCR, speed |
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BMCR_AUTOEN | BMCR_STARTNEG);
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break;
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}
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@ -257,14 +255,13 @@ rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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* be a master, otherwise it's a slave.
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*/
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if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
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PHY_WRITE(sc, RGEPHY_MII_1000CTL,
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gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
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PHY_WRITE(sc, MII_100T2CR,
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gig|GTCR_MAN_MS|GTCR_ADV_MS);
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} else {
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PHY_WRITE(sc, RGEPHY_MII_1000CTL,
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gig|RGEPHY_1000CTL_MSE);
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PHY_WRITE(sc, MII_100T2CR, gig|GTCR_MAN_MS);
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}
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PHY_WRITE(sc, RGEPHY_MII_BMCR, speed |
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RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
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PHY_WRITE(sc, MII_BMCR, speed |
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BMCR_AUTOEN | BMCR_STARTNEG);
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break;
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case IFM_NONE:
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PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
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@ -366,20 +363,20 @@ rgephy_status(struct mii_softc *sc)
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mii->mii_media_status |= IFM_ACTIVE;
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}
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bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
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bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
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bmsr = PHY_READ(sc, MII_BMSR);
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bmcr = PHY_READ(sc, MII_BMCR);
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if ((bmcr & RGEPHY_BMCR_ISO) != 0) {
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if ((bmcr & BMCR_ISO) != 0) {
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mii->mii_media_active |= IFM_NONE;
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mii->mii_media_status = 0;
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return;
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}
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if ((bmcr & RGEPHY_BMCR_LOOP) != 0)
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if ((bmcr & BMCR_LOOP) != 0)
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mii->mii_media_active |= IFM_LOOP;
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if ((bmcr & RGEPHY_BMCR_AUTOEN) != 0) {
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if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
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if ((bmcr & BMCR_AUTOEN) != 0) {
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if ((bmsr & BMSR_ACOMP) == 0) {
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/* Erg, still trying, I guess... */
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mii->mii_media_active |= IFM_NONE;
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return;
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@ -436,15 +433,13 @@ rgephy_mii_phy_auto(struct mii_softc *mii)
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anar = BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA;
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if (mii->mii_flags & MIIF_DOPAUSE)
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anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
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anar |= ANAR_FC | ANAR_X_PAUSE_ASYM;
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PHY_WRITE(mii, RGEPHY_MII_ANAR, anar);
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PHY_WRITE(mii, MII_ANAR, anar);
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DELAY(1000);
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PHY_WRITE(mii, RGEPHY_MII_1000CTL,
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RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD);
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PHY_WRITE(mii, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX);
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DELAY(1000);
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PHY_WRITE(mii, RGEPHY_MII_BMCR,
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RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
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PHY_WRITE(mii, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
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DELAY(100);
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return EJUSTRETURN;
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@ -459,13 +454,13 @@ rgephy_loop(struct mii_softc *sc)
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rsc = (struct rgephy_softc *)sc;
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if (rsc->mii_revision < 2) {
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PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
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PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN);
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DELAY(1000);
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}
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for (i = 0; i < 15000; i++) {
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bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
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if ((bmsr & RGEPHY_BMSR_LINK) == 0) {
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bmsr = PHY_READ(sc, MII_BMSR);
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if ((bmsr & BMSR_LINK) == 0) {
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#if 0
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device_printf(sc->mii_dev, "looped %d\n", i);
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#endif
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@ -613,15 +608,12 @@ rgephy_reset(struct mii_softc *sc)
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/* Reset capabilities */
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/* Step1: write our capability */
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/* 10/100 capability */
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PHY_WRITE(sc, RGEPHY_MII_ANAR,
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RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
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RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10 | ANAR_CSMA);
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PHY_WRITE(sc, MII_ANAR,
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ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
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/* 1000 capability */
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PHY_WRITE(sc, RGEPHY_MII_1000CTL,
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RGEPHY_1000CTL_AFD | RGEPHY_1000CTL_AHD);
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PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX);
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/* Step2: Restart NWay */
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/* NWay enable and Restart NWay */
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PHY_WRITE(sc, RGEPHY_MII_BMCR,
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RGEPHY_BMCR_RESET | RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
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PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: rgephyreg.h,v 1.5 2009/01/09 21:56:35 cegger Exp $ */
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/* $NetBSD: rgephyreg.h,v 1.6 2010/07/18 03:00:39 jakllsch Exp $ */
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/*
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* Copyright (c) 2003
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@ -41,104 +41,6 @@
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* RealTek 8169S/8110S gigE PHY registers
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*/
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#define RGEPHY_MII_BMCR 0x00
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#define RGEPHY_BMCR_RESET 0x8000
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#define RGEPHY_BMCR_LOOP 0x4000
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#define RGEPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
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#define RGEPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
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#define RGEPHY_BMCR_PDOWN 0x0800 /* Power down */
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#define RGEPHY_BMCR_ISO 0x0400 /* Isolate */
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#define RGEPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
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#define RGEPHY_BMCR_FDX 0x0100 /* Duplex mode */
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#define RGEPHY_BMCR_CTEST 0x0080 /* Collision test enable */
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#define RGEPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
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#define RGEPHY_S1000 RGEPHY_BMCR_SPD1 /* 1000mbps */
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#define RGEPHY_S100 RGEPHY_BMCR_SPD0 /* 100mpbs */
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#define RGEPHY_S10 0 /* 10mbps */
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#define RGEPHY_MII_BMSR 0x01
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#define RGEPHY_BMSR_100T4 0x8000 /* 100 base T4 capable */
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#define RGEPHY_BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */
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#define RGEPHY_BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */
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#define RGEPHY_BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */
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#define RGEPHY_BMSR_10THDX 0x0800 /* 10 base T half duplex capable */
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#define RGEPHY_BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */
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#define RGEPHY_BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */
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#define RGEPHY_BMSR_EXTSTS 0x0100 /* Extended status present */
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#define RGEPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */
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#define RGEPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */
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#define RGEPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */
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#define RGEPHY_BMSR_ANEG 0x0008 /* Autoneg capable */
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#define RGEPHY_BMSR_LINK 0x0004 /* Link status */
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#define RGEPHY_BMSR_JABBER 0x0002 /* Jabber detected */
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#define RGEPHY_BMSR_EXT 0x0001 /* Extended capability */
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#define RGEPHY_MII_ANAR 0x04
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#define RGEPHY_ANAR_NP 0x8000 /* Next page */
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#define RGEPHY_ANAR_RF 0x2000 /* Remote fault */
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#define RGEPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */
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#define RGEPHY_ANAR_PC 0x0400 /* Pause capable */
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#define RGEPHY_ANAR_T4 0x0200 /* local device supports 100bT4 */
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#define RGEPHY_ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */
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#define RGEPHY_ANAR_TX 0x0080 /* local device supports 100bTx */
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#define RGEPHY_ANAR_10_FD 0x0040 /* local device supports 10bT FD */
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#define RGEPHY_ANAR_10 0x0020 /* local device supports 10bT */
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#define RGEPHY_ANAR_SEL 0x001F /* selector field, 00001=Ethernet */
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#define RGEPHY_MII_ANLPAR 0x05
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#define RGEPHY_ANLPAR_NP 0x8000 /* Next page */
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#define RGEPHY_ANLPAR_RF 0x2000 /* Remote fault */
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#define RGEPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */
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#define RGEPHY_ANLPAR_PC 0x0400 /* Pause capable */
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#define RGEPHY_ANLPAR_T4 0x0200 /* link partner supports 100bT4 */
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#define RGEPHY_ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */
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#define RGEPHY_ANLPAR_TX 0x0080 /* link partner supports 100bTx */
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#define RGEPHY_ANLPAR_10_FD 0x0040 /* link partner supports 10bT FD */
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#define RGEPHY_ANLPAR_10 0x0020 /* link partner supports 10bT */
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#define RGEPHY_ANLPAR_SEL 0x001F /* selector field, 00001=Ethernet */
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#define RGEPHY_SEL_TYPE 0x0001 /* ethernet */
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#define RGEPHY_MII_ANER 0x06
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#define RGEPHY_ANER_PDF 0x0010 /* Parallel detection fault */
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#define RGEPHY_ANER_LPNP 0x0008 /* Link partner can next page */
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#define RGEPHY_ANER_NP 0x0004 /* Local PHY can next page */
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#define RGEPHY_ANER_RX 0x0002 /* Next page received */
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#define RGEPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */
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#define RGEPHY_MII_NEXTP 0x07 /* Next page */
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#define RGEPHY_MII_NEXTP_LP 0x08 /* Next page of link partner */
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#define RGEPHY_MII_1000CTL 0x09 /* 1000baseT control */
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#define RGEPHY_1000CTL_TST 0xE000 /* test modes */
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#define RGEPHY_1000CTL_MSE 0x1000 /* Master/Slave manual enable */
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#define RGEPHY_1000CTL_MSC 0x0800 /* Master/Slave select */
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#define RGEPHY_1000CTL_RD 0x0400 /* Repeater/DTE */
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#define RGEPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */
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#define RGEPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */
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#define RGEPHY_TEST_TX_JITTER 0x2000
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#define RGEPHY_TEST_TX_JITTER_MASTER_MODE 0x4000
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#define RGEPHY_TEST_TX_JITTER_SLAVE_MODE 0x6000
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#define RGEPHY_TEST_TX_DISTORTION 0x8000
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#define RGEPHY_MII_1000STS 0x0A /* 1000baseT status */
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#define RGEPHY_1000STS_MSF 0x8000 /* Master/slave fault */
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#define RGEPHY_1000STS_MSR 0x4000 /* Master/slave result */
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#define RGEPHY_1000STS_LRS 0x2000 /* Local receiver status */
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#define RGEPHY_1000STS_RRS 0x1000 /* Remote receiver status */
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#define RGEPHY_1000STS_LPFD 0x0800 /* Link partner can FD */
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#define RGEPHY_1000STS_LPHD 0x0400 /* Link partner can HD */
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#define RGEPHY_1000STS_IEC 0x00FF /* Idle error count */
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#define RGEPHY_MII_EXTSTS 0x0F /* Extended status */
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#define RGEPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
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#define RGEPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
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#define RGEPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
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#define RGEPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
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/* RTL8211B(L)/RTL8211C(L) */
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#define RGEPHY_MII_SSR 0x11 /* PHY Specific status register */
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#define RGEPHY_SSR_S1000 0x8000 /* 1000Mbps */
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