cast to appropriate types.

This commit is contained in:
christos 2012-03-21 02:32:26 +00:00
parent 59f433dfc5
commit 39052f3b3d
3 changed files with 36 additions and 36 deletions

View File

@ -1,4 +1,4 @@
/* $NetBSD: softfloat-macros,v 1.2 2009/02/16 10:23:35 tron Exp $ */
/* $NetBSD: softfloat-macros,v 1.3 2012/03/21 02:32:26 christos Exp $ */
/*
===============================================================================
@ -464,10 +464,10 @@ INLINE void mul64To128( bits64 a, bits64 b, bits64 *z0Ptr, bits64 *z1Ptr )
bits32 aHigh, aLow, bHigh, bLow;
bits64 z0, zMiddleA, zMiddleB, z1;
aLow = a;
aHigh = a>>32;
bLow = b;
bHigh = b>>32;
aLow = (bits32)a;
aHigh = (bits32)(a>>32);
bLow = (bits32)b;
bHigh = (bits32)(b>>32);
z1 = ( (bits64) aLow ) * bLow;
zMiddleA = ( (bits64) aLow ) * bHigh;
zMiddleB = ( (bits64) aHigh ) * bLow;
@ -616,7 +616,7 @@ static bits32 estimateSqrt32( int16 aExp, bits32 a )
z = 0x8000 + ( a>>17 ) - sqrtEvenAdjustments[ idx ];
z = a / z + z;
z = ( 0x20000 <= z ) ? 0xFFFF8000 : ( z<<15 );
if ( z <= a ) return (bits32) ( ( (sbits32) a )>>1 );
if ( z <= a ) return (bits32) ( ( (bits32) a )>>1 );
}
return ( (bits32) ( ( ( (bits64) a )<<31 ) / z ) ) + ( z>>1 );
@ -682,7 +682,7 @@ static int8 countLeadingZeros64( bits64 a )
else {
a >>= 32;
}
shiftCount += countLeadingZeros32( a );
shiftCount += (int8)countLeadingZeros32( (bits32)a );
return shiftCount;
}

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@ -1,4 +1,4 @@
/* $NetBSD: softfloat.c,v 1.9 2012/03/20 21:34:51 martin Exp $ */
/* $NetBSD: softfloat.c,v 1.10 2012/03/21 02:32:26 christos Exp $ */
/*
* This version hacked for use with gcc -msoft-float by bjh21.
@ -46,7 +46,7 @@ this code that are retained.
#include <sys/cdefs.h>
#if defined(LIBC_SCCS) && !defined(lint)
__RCSID("$NetBSD: softfloat.c,v 1.9 2012/03/20 21:34:51 martin Exp $");
__RCSID("$NetBSD: softfloat.c,v 1.10 2012/03/21 02:32:26 christos Exp $");
#endif /* LIBC_SCCS and not lint */
#ifdef SOFTFLOAT_FOR_GCC
@ -137,10 +137,10 @@ static int32 roundAndPackInt32( flag zSign, bits64 absZ )
}
}
}
roundBits = absZ & 0x7F;
roundBits = (int8)(absZ & 0x7F);
absZ = ( absZ + roundIncrement )>>7;
absZ &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven );
z = absZ;
z = (int32)absZ;
if ( zSign ) z = - z;
if ( ( absZ>>32 ) || ( z && ( ( z < 0 ) ^ zSign ) ) ) {
float_raise( float_flag_invalid );
@ -340,7 +340,7 @@ static float32 roundAndPackFloat32( flag zSign, int16 zExp, bits32 zSig )
isTiny =
( float_detect_tininess == float_tininess_before_rounding )
|| ( zExp < -1 )
|| ( zSig + roundIncrement < 0x80000000 );
|| ( zSig + roundIncrement < 0x80000000U );
shift32RightJamming( zSig, - zExp, &zSig );
zExp = 0;
roundBits = zSig & 0x7F;
@ -395,7 +395,7 @@ Returns the exponent bits of the double-precision floating-point value `a'.
INLINE int16 extractFloat64Exp( float64 a )
{
return ( FLOAT64_DEMANGLE(a)>>52 ) & 0x7FF;
return (int16)((FLOAT64_DEMANGLE(a) >> 52) & 0x7FF);
}
@ -407,7 +407,7 @@ Returns the sign bit of the double-precision floating-point value `a'.
INLINE flag extractFloat64Sign( float64 a )
{
return FLOAT64_DEMANGLE(a)>>63;
return (flag)(FLOAT64_DEMANGLE(a) >> 63);
}
@ -497,7 +497,7 @@ static float64 roundAndPackFloat64( flag zSign, int16 zExp, bits64 zSig )
}
}
}
roundBits = zSig & 0x3FF;
roundBits = (int16)(zSig & 0x3FF);
if ( 0x7FD <= (bits16) zExp ) {
if ( ( 0x7FD < zExp )
|| ( ( zExp == 0x7FD )
@ -512,10 +512,10 @@ static float64 roundAndPackFloat64( flag zSign, int16 zExp, bits64 zSig )
isTiny =
( float_detect_tininess == float_tininess_before_rounding )
|| ( zExp < -1 )
|| ( zSig + roundIncrement < LIT64( 0x8000000000000000 ) );
|| ( zSig + roundIncrement < (bits64)LIT64( 0x8000000000000000 ) );
shift64RightJamming( zSig, - zExp, &zSig );
zExp = 0;
roundBits = zSig & 0x3FF;
roundBits = (int16)(zSig & 0x3FF);
if ( isTiny && roundBits ) float_raise( float_flag_underflow );
}
}
@ -876,7 +876,7 @@ Returns the exponent bits of the quadruple-precision floating-point value
INLINE int32 extractFloat128Exp( float128 a )
{
return ( a.high>>48 ) & 0x7FFF;
return (int32)((a.high >> 48) & 0x7FFF);
}
@ -888,7 +888,7 @@ Returns the sign bit of the quadruple-precision floating-point value `a'.
INLINE flag extractFloat128Sign( float128 a )
{
return a.high>>63;
return (flag)(a.high >> 63);
}
@ -1124,7 +1124,7 @@ float32 int32_to_float32( int32 a )
if ( a == 0 ) return 0;
if ( a == (sbits32) 0x80000000 ) return packFloat32( 1, 0x9E, 0 );
zSign = ( a < 0 );
return normalizeRoundAndPackFloat32( zSign, 0x9C, zSign ? - a : a );
return normalizeRoundAndPackFloat32(zSign, 0x9C, (uint32)(zSign ? - a : a));
}
@ -1936,7 +1936,7 @@ float32 float32_mul( float32 a, float32 b )
aSig = ( aSig | 0x00800000 )<<7;
bSig = ( bSig | 0x00800000 )<<8;
shift64RightJamming( ( (bits64) aSig ) * bSig, 32, &zSig64 );
zSig = zSig64;
zSig = (bits32)zSig64;
if ( 0 <= (sbits32) ( zSig<<1 ) ) {
zSig <<= 1;
--zExp;
@ -2000,7 +2000,7 @@ float32 float32_div( float32 a, float32 b )
aSig >>= 1;
++zExp;
}
zSig = ( ( (bits64) aSig )<<32 ) / bSig;
zSig = (bits32)(((bits64) aSig) << 32) / bSig;
if ( ( zSig & 0x3F ) == 0 ) {
zSig |= ( (bits64) bSig * zSig != ( (bits64) aSig )<<32 );
}
@ -2379,7 +2379,7 @@ int32 float64_to_int32_round_to_zero( float64 a )
shiftCount = 0x433 - aExp;
savedASig = aSig;
aSig >>= shiftCount;
z = aSig;
z = (int32)aSig;
if ( aSign ) z = - z;
if ( ( z < 0 ) ^ aSign ) {
invalid:
@ -2514,7 +2514,7 @@ float32 float64_to_float32( float64 a )
return packFloat32( aSign, 0xFF, 0 );
}
shift64RightJamming( aSig, 22, &aSig );
zSig = aSig;
zSig = (bits32)aSig;
if ( aExp || zSig ) {
zSig |= 0x40000000;
aExp -= 0x381;
@ -4362,7 +4362,7 @@ int32 float128_to_int32_round_to_zero( float128 a )
shiftCount = 0x402F - aExp;
savedASig = aSig0;
aSig0 >>= shiftCount;
z = aSig0;
z = (int32)aSig0;
if ( aSign ) z = - z;
if ( ( z < 0 ) ^ aSign ) {
invalid:
@ -4562,7 +4562,7 @@ float32 float128_to_float32( float128 a )
}
aSig0 |= ( aSig1 != 0 );
shift64RightJamming( aSig0, 18, &aSig0 );
zSig = aSig0;
zSig = (bits32)aSig0;
if ( aExp || zSig ) {
zSig |= 0x40000000;
aExp -= 0x3F81;
@ -5255,9 +5255,9 @@ float128 float128_sqrt( float128 a )
if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( 0, 0, 0, 0 );
normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );
}
zExp = ( ( aExp - 0x3FFF )>>1 ) + 0x3FFE;
zExp = ( (unsigned int)(aExp - 0x3FFF) >> 1) + 0x3FFE;
aSig0 |= LIT64( 0x0001000000000000 );
zSig0 = estimateSqrt32( aExp, aSig0>>17 );
zSig0 = estimateSqrt32((int16)aExp, (bits32)(aSig0>>17));
shortShift128Left( aSig0, aSig1, 13 - ( aExp & 1 ), &aSig0, &aSig1 );
zSig0 = estimateDiv128To64( aSig0, aSig1, zSig0<<32 ) + ( zSig0<<30 );
doubleZSig0 = zSig0<<1;
@ -5542,7 +5542,7 @@ uint32 float64_to_uint32_round_to_zero( float64 a )
shiftCount = 0x433 - aExp;
savedASig = aSig;
aSig >>= shiftCount;
z = aSig;
z = (uint32)aSig;
if ( ( aSig<<shiftCount ) != savedASig ) {
float_exception_flags |= float_flag_inexact;
}

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@ -1,4 +1,4 @@
/* $NetBSD: softfloat-specialize,v 1.6 2011/03/06 10:27:37 martin Exp $ */
/* $NetBSD: softfloat-specialize,v 1.7 2012/03/21 02:32:26 christos Exp $ */
/* This is a derivative work. */
@ -114,7 +114,7 @@ static
flag float32_is_nan( float32 a )
{
return ( 0xFF000000 < (bits32) ( a<<1 ) );
return ( (bits32)0xFF000000 < (bits32) ( a<<1 ) );
}
@ -163,7 +163,7 @@ precision floating-point format.
static float32 commonNaNToFloat32( commonNaNT a )
{
return ( ( (bits32) a.sign )<<31 ) | 0x7FC00000 | ( a.high>>41 );
return ( ( (bits32) a.sign )<<31 ) | 0x7FC00000 | (bits32)( a.high>>41 );
}
@ -213,7 +213,7 @@ static
flag float64_is_nan( float64 a )
{
return ( LIT64( 0xFFE0000000000000 ) <
return ( (bits64)LIT64( 0xFFE0000000000000 ) <
(bits64) ( FLOAT64_DEMANGLE(a)<<1 ) );
}
@ -249,7 +249,7 @@ static commonNaNT float64ToCommonNaN( float64 a )
commonNaNT z;
if ( float64_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
z.sign = FLOAT64_DEMANGLE(a)>>63;
z.sign = (flag)(FLOAT64_DEMANGLE(a)>>63);
z.low = 0;
z.high = FLOAT64_DEMANGLE(a)<<12;
return z;
@ -427,7 +427,7 @@ flag float128_is_nan( float128 a )
{
return
( LIT64( 0xFFFE000000000000 ) <= (bits64) ( a.high<<1 ) )
( (bits64)LIT64( 0xFFFE000000000000 ) <= (bits64) ( a.high<<1 ) )
&& ( a.low || ( a.high & LIT64( 0x0000FFFFFFFFFFFF ) ) );
}
@ -459,7 +459,7 @@ static commonNaNT float128ToCommonNaN( float128 a )
commonNaNT z;
if ( float128_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
z.sign = a.high>>63;
z.sign = (flag)(a.high>>63);
shortShift128Left( a.high, a.low, 16, &z.high, &z.low );
return z;