- Port clock calibration code (auich_calibrate) from ich.c of FreeBSD to solve
kern/16373. - SiS 7012 support from kern/17716 submitted by Quentin Garnier. - ICH4 support - Experimental support for nForce MCP, AMD768 and AMD8111. - Rename the short name for ICH3: "i830M" -> "ICH3"
This commit is contained in:
kent
parent
38b5f64780
commit
3898bab95a
@ -1,4 +1,4 @@
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/* $NetBSD: auich.c,v 1.17 2002/04/11 10:54:23 augustss Exp $ */
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/* $NetBSD: auich.c,v 1.18 2002/08/07 10:31:09 kent Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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@ -66,21 +66,55 @@
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* from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp
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*/
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/*
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* Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp>
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* Copyright (c) 2001 Cameron Grant <cg@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
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* SUCH DAMAGE.
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*
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* auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp
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*/
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/* #define ICH_DEBUG */
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/*
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* AC'97 audio found on Intel 810/820/440MX chipsets.
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* http://developer.intel.com/design/chipsets/datashts/290655.htm
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* http://developer.intel.com/design/chipsets/manuals/298028.htm
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* ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm
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* ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm
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*
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* TODO:
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*
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* - Probe codecs for supported sample rates.
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*
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* - Add support for the microphone input.
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* - 4ch/6ch support.
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* - auich_calibrate() is called in auich_open(). It causes about 0.1sec
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* delay in the first open(). auich_calibrate() should be called in
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* auich_attach(). However microtime() doesn't work in the attach
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* stage.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.17 2002/04/11 10:54:23 augustss Exp $");
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__KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.18 2002/08/07 10:31:09 kent Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -168,7 +202,13 @@ struct auich_softc {
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struct auich_dma *sc_dmas;
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int sc_fixed_rate;
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int sc_fixed_rate;
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int sc_ac97rate;
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int sc_ignore_codecready;
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/* SiS 7012 hack */
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int sc_sample_size;
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int sc_sts_reg;
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void (*sc_pintr)(void *);
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void *sc_parg;
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@ -233,6 +273,7 @@ int auich_freemem(struct auich_softc *, struct auich_dma *);
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void auich_powerhook(int, void *);
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int auich_set_rate(struct auich_softc *sc, int mode, uint srate);
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unsigned int auich_calibrate(struct auich_softc *sc);
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struct audio_hw_if auich_hw_if = {
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@ -271,23 +312,33 @@ int auich_write_codec(void *, u_int8_t, u_int16_t);
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void auich_reset_codec(void *);
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static const struct auich_devtype {
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int vendor;
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int product;
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const char *name;
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const char *shortname;
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} auich_devices[] = {
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{ PCI_PRODUCT_INTEL_82801AA_ACA,
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA,
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"i82801AA (ICH) AC-97 Audio", "ICH" },
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{ PCI_PRODUCT_INTEL_82801AB_ACA,
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"i82801AB (ICH0) AC-97 Audio", "ICH0" },
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{ PCI_PRODUCT_INTEL_82801BA_ACA,
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA,
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"i82801AB (ICH0) AC-97 Audio", "ICH0" }, /* i810-L */
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA,
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"i82801BA (ICH2) AC-97 Audio", "ICH2" },
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{ PCI_PRODUCT_INTEL_82440MX_ACA,
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA,
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"i82440MX AC-97 Audio", "440MX" },
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{ PCI_PRODUCT_INTEL_82801CA_AC,
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"i82801CA AC-97 Audio", "i830M" },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC,
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"i82801CA (ICH3) AC-97 Audio", "ICH3" }, /* i830Mx i845MP/MZ*/
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC,
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"i82801DB (ICH4) AC-97 Audio", "ICH4" }, /* i845E i845Gx */
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{ PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC,
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"SiS 7012 AC-97 Audio", "SiS7012" },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC,
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"nForce MCP AC-97 Audio", "nForce-MCP" },
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{ PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC,
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"AMD768 AC-97 Audio", "AMD768" },
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{ PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC,
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"AMD8111 AC-97 Audio", "AMD8111" },
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{ 0,
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NULL, NULL },
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NULL, NULL },
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};
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static const struct auich_devtype *
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@ -295,11 +346,9 @@ auich_lookup(struct pci_attach_args *pa)
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{
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const struct auich_devtype *d;
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if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL)
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return (NULL);
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for (d = auich_devices; d->name != NULL; d++) {
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if (PCI_PRODUCT(pa->pa_id) == d->product)
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if (PCI_VENDOR(pa->pa_id) == d->vendor
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&& PCI_PRODUCT(pa->pa_id) == d->product)
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return (d);
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}
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@ -328,6 +377,7 @@ auich_attach(struct device *parent, struct device *self, void *aux)
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const char *intrstr;
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const struct auich_devtype *d;
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u_int16_t ext_id, ext_status;
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u_int32_t status;
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d = auich_lookup(pa);
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if (d == NULL)
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@ -375,6 +425,16 @@ auich_attach(struct device *parent, struct device *self, void *aux)
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sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class));
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strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname);
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/* SiS 7012 needs special handling */
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if (d->vendor == PCI_VENDOR_SIS
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&& d->product == PCI_PRODUCT_SIS_7012_AC) {
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sc->sc_sts_reg = ICH_PICB;
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sc->sc_sample_size = 1;
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} else {
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sc->sc_sts_reg = ICH_STS;
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sc->sc_sample_size = 2;
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}
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/* Set up DMA lists. */
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sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0;
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auich_alloc_cdata(sc);
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@ -384,6 +444,23 @@ auich_attach(struct device *parent, struct device *self, void *aux)
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/* Reset codec and AC'97 */
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auich_reset_codec(sc);
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status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS);
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if (!(status & ICH_PCR)) { /* reset failure */
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if (d->vendor == PCI_VENDOR_INTEL
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&& d->product == PCI_PRODUCT_INTEL_82801DB_AC) {
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/* MSI 845G Max never return ICH_PCR */
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sc->sc_ignore_codecready = TRUE;
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} else {
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return;
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}
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}
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/* Print capabilities though there are no supports for now */
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if ((status & ICH_SAMPLE_CAP) == ICH_POM20)
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printf("%s: 20 bit precision support\n", sc->sc_dev.dv_xname);
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if ((status & ICH_CHAN_CAP) == ICH_PCM4)
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printf("%s: 4ch PCM output support\n", sc->sc_dev.dv_xname);
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if ((status & ICH_CHAN_CAP) == ICH_PCM6)
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printf("%s: 6ch PCM output support\n", sc->sc_dev.dv_xname);
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sc->host_if.arg = sc;
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sc->host_if.attach = auich_attach_codec;
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@ -404,10 +481,12 @@ auich_attach(struct device *parent, struct device *self, void *aux)
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auich_write_codec(sc, AC97_REG_EXTENDED_STATUS, ext_status);
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/* so it claims to do variable rate, let's make sure */
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sc->sc_ac97rate = FIXED_RATE;
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if (auich_set_rate(sc, AUMODE_PLAY, 44100) == 44100)
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sc->sc_fixed_rate = 0;
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else
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sc->sc_fixed_rate = FIXED_RATE;
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sc->sc_ac97rate = 0;
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} else {
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sc->sc_fixed_rate = FIXED_RATE;
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}
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@ -429,8 +508,9 @@ auich_read_codec(void *v, u_int8_t reg, u_int16_t *val)
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int i;
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uint32_t status;
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if (!(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) {
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printf("auich_read_codec: codec is not ready.");
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status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS);
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if (!sc->sc_ignore_codecready && !(status & ICH_PCR)) {
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printf("auich_read_codec: codec is not ready (0x%x)\n", status);
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*val = 0xffff;
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return -1;
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}
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@ -464,7 +544,8 @@ auich_write_codec(void *v, u_int8_t reg, u_int16_t val)
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int i;
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DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val));
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if (!(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) {
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if (!sc->sc_ignore_codecready
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&& !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) {
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printf("auich_write_codec: codec is not ready.");
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return -1;
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}
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@ -497,20 +578,27 @@ auich_reset_codec(void *v)
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{
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struct auich_softc *sc = v;
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int i;
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uint32_t control;
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bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, 0);
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DELAY(10);
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bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, ICH_CRESET);
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control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL);
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control &= ~(ICH_ACLSO | ICH_PCM246_MASK);
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control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET;
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bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control);
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for (i = 500000; i-- &&
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!(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR);
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DELAY(1)); /* or ICH_SCR? */
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if (i <= 0)
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printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname);
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}
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int
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auich_open(void *v, int flags)
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{
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struct auich_softc *sc = v;
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if (!sc->sc_fixed_rate && sc->sc_ac97rate == 0)
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sc->sc_ac97rate = auich_calibrate(sc);
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return 0;
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}
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@ -588,23 +676,26 @@ int
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auich_set_rate(struct auich_softc *sc, int mode, uint srate)
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{
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u_int16_t val, rate, inout;
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u_int32_t rvalue;
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inout = mode == AUMODE_PLAY ? ICH_PM_PCMO : ICH_PM_PCMI;
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auich_read_codec(sc, AC97_REG_POWER, &val);
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auich_write_codec(sc, AC97_REG_POWER, val | inout);
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rvalue = srate * FIXED_RATE / sc->sc_ac97rate;
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if (mode == AUMODE_PLAY) {
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auich_write_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, srate);
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auich_write_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, rvalue);
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auich_read_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, &rate);
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} else {
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auich_write_codec(sc, AC97_REG_PCM_LR_ADC_RATE, srate);
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auich_write_codec(sc, AC97_REG_PCM_LR_ADC_RATE, rvalue);
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auich_read_codec(sc, AC97_REG_PCM_LR_ADC_RATE, &rate);
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}
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auich_write_codec(sc, AC97_REG_POWER, val);
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return rate;
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rvalue = rate * sc->sc_ac97rate / FIXED_RATE;
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return rvalue;
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}
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int
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@ -641,8 +732,12 @@ auich_set_params(void *v, int setmode, int usemode, struct audio_params *play,
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/* setup hardware formats */
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p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE;
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p->hw_precision = 16;
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/* If manaural is requested, aurateconv expands a monaural
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* stream to stereo. */
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if (p->channels < 2)
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p->hw_channels = 2;
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switch (p->encoding) {
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case AUDIO_ENCODING_SLINEAR_BE:
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if (p->precision == 16) {
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@ -715,11 +810,14 @@ auich_set_params(void *v, int setmode, int usemode, struct audio_params *play,
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return (EINVAL);
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}
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if (sc->sc_fixed_rate)
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if (sc->sc_fixed_rate) {
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p->hw_sample_rate = sc->sc_fixed_rate;
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else
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} else {
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p->hw_sample_rate = auich_set_rate(sc, mode,
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p->sample_rate);
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}
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/* If hw_sample_rate is different from sample_rate, aurateconv
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* works. */
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}
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return (0);
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@ -880,7 +978,7 @@ auich_intr(void *v)
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DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts));
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if (gsts & ICH_POINT) {
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sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+ICH_STS);
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sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg);
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DPRINTF(ICH_DEBUG_DMA,
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("auich_intr: osts=0x%x\n", sts));
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@ -899,7 +997,7 @@ auich_intr(void *v)
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q = &sc->dmalist_pcmo[qptr];
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q->base = sc->pcmo_p;
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q->len = (sc->pcmo_blksize / 2) | ICH_DMAF_IOC;
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q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC;
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DPRINTF(ICH_DEBUG_DMA,
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("auich_intr: %p, %p = %x @ 0x%x\n",
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&sc->dmalist_pcmo[i], q,
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@ -923,14 +1021,14 @@ auich_intr(void *v)
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sc->sc_pintr(sc->sc_parg);
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/* int ack */
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bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_STS,
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bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg,
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sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE));
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bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT);
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ret++;
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}
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if (gsts & ICH_PIINT) {
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sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+ICH_STS);
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sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg);
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DPRINTF(ICH_DEBUG_DMA,
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("auich_intr: ists=0x%x\n", sts));
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@ -949,7 +1047,7 @@ auich_intr(void *v)
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q = &sc->dmalist_pcmi[qptr];
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q->base = sc->pcmi_p;
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q->len = (sc->pcmi_blksize / 2) | ICH_DMAF_IOC;
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q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC;
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DPRINTF(ICH_DEBUG_DMA,
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("auich_intr: %p, %p = %x @ 0x%x\n",
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&sc->dmalist_pcmi[i], q,
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@ -973,14 +1071,14 @@ auich_intr(void *v)
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sc->sc_rintr(sc->sc_rarg);
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/* int ack */
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bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_STS,
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bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg,
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sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE));
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bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT);
|
||||
ret++;
|
||||
}
|
||||
|
||||
if (gsts & ICH_MIINT) {
|
||||
sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+ICH_STS);
|
||||
sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg);
|
||||
DPRINTF(ICH_DEBUG_DMA,
|
||||
("auich_intr: ists=0x%x\n", sts));
|
||||
if (sts & ICH_FIFOE)
|
||||
@ -1032,7 +1130,7 @@ auich_trigger_output(void *v, void *start, void *end, int blksize,
|
||||
sc->ptr_pcmo = 0;
|
||||
q = &sc->dmalist_pcmo[sc->ptr_pcmo];
|
||||
q->base = sc->pcmo_start;
|
||||
q->len = (blksize / 2) | ICH_DMAF_IOC;
|
||||
q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC;
|
||||
if (++sc->ptr_pcmo == ICH_DMALIST_MAX)
|
||||
sc->ptr_pcmo = 0;
|
||||
|
||||
@ -1089,7 +1187,7 @@ auich_trigger_input(v, start, end, blksize, intr, arg, param)
|
||||
sc->ptr_pcmi = 0;
|
||||
q = &sc->dmalist_pcmi[sc->ptr_pcmi];
|
||||
q->base = sc->pcmi_start;
|
||||
q->len = (blksize / 2) | ICH_DMAF_IOC;
|
||||
q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC;
|
||||
if (++sc->ptr_pcmi == ICH_DMALIST_MAX)
|
||||
sc->ptr_pcmi = 0;
|
||||
|
||||
@ -1244,3 +1342,105 @@ auich_powerhook(int why, void *addr)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
/* Calibrate card (some boards are overclocked and need scaling) */
|
||||
|
||||
unsigned int
|
||||
auich_calibrate(struct auich_softc *sc)
|
||||
{
|
||||
struct timeval t1, t2;
|
||||
u_int8_t ociv, nciv;
|
||||
u_int32_t wait_us, actual_48k_rate, bytes, ac97rate;
|
||||
void *temp_buffer;
|
||||
struct auich_dma *p;
|
||||
|
||||
ac97rate = 48000;
|
||||
/*
|
||||
* Grab audio from input for fixed interval and compare how
|
||||
* much we actually get with what we expect. Interval needs
|
||||
* to be sufficiently short that no interrupts are
|
||||
* generated.
|
||||
*/
|
||||
|
||||
/* Setup a buffer */
|
||||
bytes = 16000;
|
||||
temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK);
|
||||
for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next)
|
||||
;
|
||||
if (p == NULL) {
|
||||
printf("auich_calibrate: bad address %p\n", temp_buffer);
|
||||
return ac97rate;
|
||||
}
|
||||
sc->dmalist_pcmi[0].base = DMAADDR(p);
|
||||
sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size) | ICH_DMAF_IOC;
|
||||
|
||||
/*
|
||||
* our data format is stereo, 16 bit so each sample is 4 bytes.
|
||||
* assuming we get 48000 samples per second, we get 192000 bytes/sec.
|
||||
* we're going to start recording with interrupts disabled and measure
|
||||
* the time taken for one block to complete. we know the block size,
|
||||
* we know the time in microseconds, we calculate the sample rate:
|
||||
*
|
||||
* actual_rate [bps] = bytes / (time [s] * 4)
|
||||
* actual_rate [bps] = (bytes * 1000000) / (time [us] * 4)
|
||||
* actual_rate [Hz] = (bytes * 250000) / time [us]
|
||||
*/
|
||||
|
||||
/* prepare */
|
||||
ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV);
|
||||
nciv = ociv;
|
||||
bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR,
|
||||
sc->sc_cddma + ICH_PCMI_OFF(0));
|
||||
bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI,
|
||||
(0 - 1) & ICH_LVI_MASK);
|
||||
|
||||
/* start */
|
||||
microtime(&t1);
|
||||
bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM);
|
||||
|
||||
/* wait */
|
||||
while (nciv == ociv) {
|
||||
microtime(&t2);
|
||||
if (t2.tv_sec - t1.tv_sec > 1)
|
||||
break;
|
||||
nciv = bus_space_read_1(sc->iot, sc->aud_ioh,
|
||||
ICH_PCMI + ICH_CIV);
|
||||
}
|
||||
microtime(&t2);
|
||||
|
||||
/* stop */
|
||||
bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0);
|
||||
|
||||
/* reset */
|
||||
DELAY(100);
|
||||
bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR);
|
||||
|
||||
/* turn time delta into us */
|
||||
wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec;
|
||||
|
||||
auich_freem(sc, temp_buffer, M_DEVBUF);
|
||||
|
||||
if (nciv == ociv) {
|
||||
printf("%s: ac97 link rate calibration timed out after %d us\n",
|
||||
sc->sc_dev.dv_xname, wait_us);
|
||||
return ac97rate;
|
||||
}
|
||||
|
||||
actual_48k_rate = (bytes * 250000) / wait_us;
|
||||
|
||||
if (actual_48k_rate < 47500 || actual_48k_rate > 48500) {
|
||||
ac97rate = actual_48k_rate;
|
||||
}
|
||||
|
||||
if (ac97rate != 48000) {
|
||||
printf("%s: measured ac97 link rate at %d Hz",
|
||||
sc->sc_dev.dv_xname, actual_48k_rate);
|
||||
if (ac97rate != actual_48k_rate)
|
||||
printf(", will use %d Hz", ac97rate);
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
return ac97rate;
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: auichreg.h,v 1.2 2000/11/28 16:57:16 thorpej Exp $ */
|
||||
/* $NetBSD: auichreg.h,v 1.3 2002/08/07 10:31:09 kent Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2000 Michael Shalayeff
|
||||
@ -70,6 +70,16 @@
|
||||
#define ICH_MICI 0x20
|
||||
|
||||
#define ICH_GCTRL 0x2c
|
||||
#define ICH_SSM_78 0x40000000 /* S/PDIF slots 7 and 8 */
|
||||
#define ICH_SSM_69 0x80000000 /* S/PDIF slots 6 and 9 */
|
||||
#define ICH_SSM_1011 0xc0000000 /* S/PDIF slots 10 and 11 */
|
||||
#define ICH_POM16 0x000000 /* PCM out precision 16bit */
|
||||
#define ICH_POM20 0x400000 /* PCM out precision 20bit */
|
||||
#define ICH_PCM246_MASK 0x300000
|
||||
#define ICH_PCM2 0x000000 /* 2ch output */
|
||||
#define ICH_PCM4 0x100000 /* 4ch output */
|
||||
#define ICH_PCM6 0x200000 /* 6ch output */
|
||||
#define ICH_S2RIE 0x40 /* int when tertiary codec resume */
|
||||
#define ICH_SRIE 0x20 /* int when 2ndary codec resume */
|
||||
#define ICH_PRIE 0x10 /* int when primary codec resume */
|
||||
#define ICH_ACLSO 0x08 /* aclink shut off */
|
||||
@ -77,6 +87,14 @@
|
||||
#define ICH_CRESET 0x02 /* cold reset */
|
||||
#define ICH_GIE 0x01 /* gpi int enable */
|
||||
#define ICH_GSTS 0x30
|
||||
#define ICH_S2RI 0x20000000 /* tertiary resume int */
|
||||
#define ICH_S2CR 0x10000000 /* tertiary codec ready */
|
||||
#define ICH_BCS 0x08000000 /* bit clock stopped */
|
||||
#define ICH_SPINT 0x04000000 /* S/PDIF int */
|
||||
#define ICH_P2INT 0x02000000 /* PCM-In 2 int */
|
||||
#define ICH_M2INT 0x01000000 /* mic 2 int */
|
||||
#define ICH_SAMPLE_CAP 0x00c00000 /* sampling precision capability */
|
||||
#define ICH_CHAN_CAP 0x00300000 /* multi-channel capability */
|
||||
#define ICH_MD3 0x20000 /* pwr-dn semaphore for modem */
|
||||
#define ICH_AD3 0x10000 /* pwr-dn semaphore for audio */
|
||||
#define ICH_RCS 0x08000 /* read completion status */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user