Pull up the following, requested by msaitoh in ticket #1933:
sys/dev/pci/ixgbe/ix_txrx.c 1.105-1.116 via patch
sys/dev/pci/ixgbe/ixgbe.c 1.345-1.346,1.349 via patch
sys/dev/pci/ixgbe/ixgbe.h 1.94-1.98
sys/dev/pci/ixgbe/ixgbe_type.h 1.62
sys/dev/pci/ixgbe/ixv.c 1.193,1.195-1.196
- Clear the WTHRESH bit field before writing it.
- Optimize ixgbe_txeof().
- Use kmem_zalloc() instead of malloc(,M_ZERO).
- Add QPRDC(Queue Packet Receive Drop Count) into iqdrops.
- No functional change
- Move assignment of TXD.
- ixv(4): Remove unused IFF_OACTIVE.
- Don't include the Flow Director related members to reduce the
size of struct tx_ring. On amd64 and aarch64, the real size is
not changed because of the alignment.
- The descriptor ring size and the alignment are tested in the
attach function, so it's not required to use
roundup2(size, DBA_ALIGN).
- Use #ifdef LRO more to reduce the size of struct rx_ring.
- Change "me" from 32bit to 8bit because the max is 128.
This commit doesn't change the real size of ix_queue, tx_ring
and rx_ring because of the alignment.
- Th RSC (hardware receive side coalescing) feature has been
disabled all along, so enclose the code with #ifdef RSC.
- Remove unused.
- Modify for the readability.
- Modify comment.
- Fix comment. Whitespace.
This commit is contained in:
martin
parent
e221697f36
commit
381ed247f5
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@ -1,4 +1,4 @@
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/* $NetBSD: ix_txrx.c,v 1.24.2.30 2023/10/18 14:23:15 martin Exp $ */
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/* $NetBSD: ix_txrx.c,v 1.24.2.31 2024/02/03 12:17:03 martin Exp $ */
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/******************************************************************************
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@ -64,13 +64,14 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ix_txrx.c,v 1.24.2.30 2023/10/18 14:23:15 martin Exp $");
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__KERNEL_RCSID(0, "$NetBSD: ix_txrx.c,v 1.24.2.31 2024/02/03 12:17:03 martin Exp $");
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#include "opt_inet.h"
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#include "opt_inet6.h"
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#include "ixgbe.h"
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#ifdef RSC
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/*
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* HW RSC control:
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* this feature only works with
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@ -84,7 +85,9 @@ __KERNEL_RCSID(0, "$NetBSD: ix_txrx.c,v 1.24.2.30 2023/10/18 14:23:15 martin Exp
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* to enable.
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*/
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static bool ixgbe_rsc_enable = FALSE;
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#endif
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#ifdef IXGBE_FDIR
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/*
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* For Flow Director: this is the
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* number of TX packets we sample
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@ -95,6 +98,7 @@ static bool ixgbe_rsc_enable = FALSE;
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* setting this to 0.
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*/
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static int atr_sample_rate = 20;
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#endif
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#define IXGBE_M_ADJ(sc, rxr, mp) \
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if (sc->max_frame_size <= (rxr->mbuf_sz - ETHER_ALIGN)) \
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@ -122,8 +126,9 @@ static __inline void ixgbe_rx_input(struct rx_ring *, struct ifnet *,
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static int ixgbe_dma_malloc(struct ixgbe_softc *, bus_size_t,
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struct ixgbe_dma_alloc *, int);
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static void ixgbe_dma_free(struct ixgbe_softc *, struct ixgbe_dma_alloc *);
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static void ixgbe_setup_hw_rsc(struct rx_ring *);
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#ifdef RSC
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static void ixgbe_setup_hw_rsc(struct rx_ring *);
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#endif
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/************************************************************************
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* ixgbe_legacy_start_locked - Transmit entry point
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@ -406,7 +411,7 @@ ixgbe_drain_all(struct ixgbe_softc *sc)
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static int
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ixgbe_xmit(struct tx_ring *txr, struct mbuf *m_head)
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{
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struct ixgbe_softc *sc = txr->sc;
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struct ixgbe_softc *sc = txr->sc;
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struct ixgbe_tx_buf *txbuf;
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union ixgbe_adv_tx_desc *txd = NULL;
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struct ifnet *ifp = sc->ifp;
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@ -487,8 +492,8 @@ retry:
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}
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/*
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* Set up the appropriate offload context
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* this will consume the first descriptor
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* Set up the appropriate offload context if requested,
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* this may consume one TX descriptor.
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*/
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error = ixgbe_tx_ctx_setup(txr, m_head, &cmd_type_len, &olinfo_status);
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if (__predict_false(error)) {
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@ -625,14 +630,8 @@ ixgbe_allocate_transmit_buffers(struct tx_ring *txr)
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goto fail;
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}
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txr->tx_buffers =
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(struct ixgbe_tx_buf *) malloc(sizeof(struct ixgbe_tx_buf) *
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sc->num_tx_desc, M_DEVBUF, M_NOWAIT | M_ZERO);
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if (txr->tx_buffers == NULL) {
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aprint_error_dev(dev, "Unable to allocate tx_buffer memory\n");
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error = ENOMEM;
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goto fail;
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}
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txr->tx_buffers = kmem_zalloc(sizeof(struct ixgbe_tx_buf) *
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sc->num_tx_desc, KM_SLEEP);
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/* Create the descriptor buffer dma maps */
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txbuf = txr->tx_buffers;
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@ -722,9 +721,11 @@ ixgbe_setup_transmit_ring(struct tx_ring *txr)
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txbuf->eop = NULL;
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}
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#ifdef IXGBE_FDIR
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/* Set the rate at which we sample packets */
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if (sc->feat_en & IXGBE_FEATURE_FDIR)
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txr->atr_sample = atr_sample_rate;
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#endif
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/* Set number of descriptors available */
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txr->tx_avail = sc->num_tx_desc;
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@ -761,7 +762,7 @@ ixgbe_free_transmit_structures(struct ixgbe_softc *sc)
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ixgbe_dma_free(sc, &txr->txdma);
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IXGBE_TX_LOCK_DESTROY(txr);
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}
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free(sc->tx_rings, M_DEVBUF);
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kmem_free(sc->tx_rings, sizeof(struct tx_ring) * sc->num_queues);
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} /* ixgbe_free_transmit_structures */
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/************************************************************************
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@ -772,7 +773,7 @@ ixgbe_free_transmit_structures(struct ixgbe_softc *sc)
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static void
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ixgbe_free_transmit_buffers(struct tx_ring *txr)
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{
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struct ixgbe_softc *sc = txr->sc;
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struct ixgbe_softc *sc = txr->sc;
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struct ixgbe_tx_buf *tx_buffer;
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int i;
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@ -809,7 +810,8 @@ ixgbe_free_transmit_buffers(struct tx_ring *txr)
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pcq_destroy(txr->txr_interq);
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}
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if (txr->tx_buffers != NULL) {
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free(txr->tx_buffers, M_DEVBUF);
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kmem_free(txr->tx_buffers,
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sizeof(struct ixgbe_tx_buf) * sc->num_tx_desc);
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txr->tx_buffers = NULL;
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}
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if (txr->txtag != NULL) {
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@ -861,9 +863,6 @@ ixgbe_tx_ctx_setup(struct tx_ring *txr, struct mbuf *mp,
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/* Indicate the whole packet as payload when not doing TSO */
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*olinfo_status |= mp->m_pkthdr.len << IXGBE_ADVTXD_PAYLEN_SHIFT;
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/* Now ready a context descriptor */
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TXD = (struct ixgbe_adv_tx_context_desc *)&txr->tx_base[ctxd];
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/*
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* In advanced descriptors the vlan tag must
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* be placed into the context descriptor. Hence
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no_offloads:
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type_tucmd_mlhl |= IXGBE_ADVTXD_DCMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
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/* Now ready a context descriptor */
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TXD = (struct ixgbe_adv_tx_context_desc *)&txr->tx_base[ctxd];
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/* Now copy bits into descriptor */
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TXD->vlan_macip_lens = htole32(vlan_macip_lens);
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TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
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@ -1115,6 +1117,7 @@ ixgbe_txeof(struct tx_ring *txr)
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union ixgbe_adv_tx_desc *txd;
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u32 work, processed = 0;
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u32 limit = sc->tx_process_limit;
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u16 avail;
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KASSERT(mutex_owned(&txr->tx_mtx));
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buf = &txr->tx_buffers[work];
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txd = &txr->tx_base[work];
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work -= txr->num_desc; /* The distance to ring end */
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avail = txr->tx_avail;
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ixgbe_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map,
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BUS_DMASYNC_POSTREAD);
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@ -1179,8 +1183,7 @@ ixgbe_txeof(struct tx_ring *txr)
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buf->m_head = NULL;
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}
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buf->eop = NULL;
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txr->txr_no_space = false;
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++txr->tx_avail;
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++avail;
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/* We clean the range if multi segment */
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while (txd != eop) {
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@ -1205,13 +1208,11 @@ ixgbe_txeof(struct tx_ring *txr)
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m_freem(buf->m_head);
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buf->m_head = NULL;
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}
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++txr->tx_avail;
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++avail;
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buf->eop = NULL;
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}
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++txr->packets;
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++processed;
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++ifp->if_opackets;
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/* Try the next packet */
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++txd;
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@ -1231,6 +1232,12 @@ ixgbe_txeof(struct tx_ring *txr)
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work += txr->num_desc;
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txr->next_to_clean = work;
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if (processed) {
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txr->tx_avail = avail;
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txr->txr_no_space = false;
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txr->packets += processed;
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ifp->if_opackets += processed;
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}
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/*
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* Queue Hang detection, we know there's
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@ -1255,6 +1262,7 @@ ixgbe_txeof(struct tx_ring *txr)
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return ((limit > 0) ? false : true);
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} /* ixgbe_txeof */
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#ifdef RSC
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/************************************************************************
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* ixgbe_rsc_count
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*
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@ -1331,6 +1339,7 @@ ixgbe_setup_hw_rsc(struct rx_ring *rxr)
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rxr->hw_rsc = TRUE;
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} /* ixgbe_setup_hw_rsc */
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#endif
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/************************************************************************
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* ixgbe_refresh_mbufs
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@ -1425,13 +1434,7 @@ ixgbe_allocate_receive_buffers(struct rx_ring *rxr)
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int bsize, error;
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bsize = sizeof(struct ixgbe_rx_buf) * rxr->num_desc;
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rxr->rx_buffers = (struct ixgbe_rx_buf *)malloc(bsize, M_DEVBUF,
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M_NOWAIT | M_ZERO);
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if (rxr->rx_buffers == NULL) {
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aprint_error_dev(dev, "Unable to allocate rx_buffer memory\n");
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error = ENOMEM;
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goto fail;
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}
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rxr->rx_buffers = kmem_zalloc(bsize, KM_SLEEP);
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error = ixgbe_dma_tag_create(
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/* parent */ sc->osdep.dmat,
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@ -1509,8 +1512,8 @@ ixgbe_setup_receive_ring(struct rx_ring *rxr)
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slot = netmap_reset(na, NR_RX, rxr->me, 0);
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#endif /* DEV_NETMAP */
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rsize = roundup2(sc->num_rx_desc *
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sizeof(union ixgbe_adv_rx_desc), DBA_ALIGN);
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rsize = sc->num_rx_desc * sizeof(union ixgbe_adv_rx_desc);
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KASSERT((rsize % DBA_ALIGN) == 0);
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bzero((void *)rxr->rx_base, rsize);
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/* Cache the size */
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rxr->mbuf_sz = sc->rx_mbuf_sz;
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@ -1519,10 +1522,10 @@ ixgbe_setup_receive_ring(struct rx_ring *rxr)
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ixgbe_free_receive_ring(rxr);
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/* Now replenish the mbufs */
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for (int j = 0; j != rxr->num_desc; ++j) {
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for (int i = 0; i < rxr->num_desc; i++) {
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struct mbuf *mp;
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rxbuf = &rxr->rx_buffers[j];
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rxbuf = &rxr->rx_buffers[i];
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#ifdef DEV_NETMAP
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/*
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@ -1533,14 +1536,14 @@ ixgbe_setup_receive_ring(struct rx_ring *rxr)
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* an mbuf, so end the block with a continue;
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*/
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if ((sc->feat_en & IXGBE_FEATURE_NETMAP) && slot) {
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int sj = netmap_idx_n2k(na->rx_rings[rxr->me], j);
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int sj = netmap_idx_n2k(na->rx_rings[rxr->me], i);
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uint64_t paddr;
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void *addr;
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addr = PNMB(na, slot + sj, &paddr);
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netmap_load_map(na, rxr->ptag, rxbuf->pmap, addr);
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/* Update descriptor and the cached value */
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rxr->rx_base[j].read.pkt_addr = htole64(paddr);
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rxr->rx_base[i].read.pkt_addr = htole64(paddr);
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rxbuf->addr = htole64(paddr);
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continue;
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}
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@ -1572,7 +1575,7 @@ ixgbe_setup_receive_ring(struct rx_ring *rxr)
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bus_dmamap_sync(rxr->ptag->dt_dmat, rxbuf->pmap,
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0, mp->m_pkthdr.len, BUS_DMASYNC_PREREAD);
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/* Update the descriptor and the cached value */
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rxr->rx_base[j].read.pkt_addr =
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rxr->rx_base[i].read.pkt_addr =
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htole64(rxbuf->pmap->dm_segs[0].ds_addr);
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rxbuf->addr = htole64(rxbuf->pmap->dm_segs[0].ds_addr);
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}
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@ -1580,7 +1583,9 @@ ixgbe_setup_receive_ring(struct rx_ring *rxr)
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/* Setup our descriptor indices */
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rxr->next_to_check = 0;
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rxr->next_to_refresh = sc->num_rx_desc - 1; /* Fully allocated */
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#ifdef LRO
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rxr->lro_enabled = FALSE;
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#endif
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rxr->discard_multidesc = false;
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IXGBE_EVC_STORE(&rxr->rx_copies, 0);
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#if 0 /* NetBSD */
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@ -1597,10 +1602,15 @@ ixgbe_setup_receive_ring(struct rx_ring *rxr)
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/*
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* Now set up the LRO interface
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*/
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#ifdef RSC
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if (ixgbe_rsc_enable)
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ixgbe_setup_hw_rsc(rxr);
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#endif
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#ifdef LRO
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else if (ifp->if_capenable & IFCAP_LRO) {
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#ifdef RSC
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else
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#endif
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if (ifp->if_capenable & IFCAP_LRO) {
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device_t dev = sc->dev;
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int err = tcp_lro_init(lro);
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if (err) {
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@ -1677,7 +1687,7 @@ ixgbe_free_receive_structures(struct ixgbe_softc *sc)
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IXGBE_RX_LOCK_DESTROY(rxr);
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}
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free(sc->rx_rings, M_DEVBUF);
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kmem_free(sc->rx_rings, sizeof(struct rx_ring) * sc->num_queues);
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} /* ixgbe_free_receive_structures */
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@ -1704,7 +1714,8 @@ ixgbe_free_receive_buffers(struct rx_ring *rxr)
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}
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if (rxr->rx_buffers != NULL) {
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free(rxr->rx_buffers, M_DEVBUF);
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kmem_free(rxr->rx_buffers,
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sizeof(struct ixgbe_rx_buf) * rxr->num_desc);
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rxr->rx_buffers = NULL;
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}
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}
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@ -1867,7 +1878,10 @@ ixgbe_rxeof(struct ix_queue *que)
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struct mbuf *sendmp, *mp;
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struct mbuf *newmp;
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u32 rsc, ptype;
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#ifdef RSC
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u32 rsc;
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#endif
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u32 ptype;
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u16 len;
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u16 vtag = 0;
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bool eop;
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@ -1902,7 +1916,9 @@ ixgbe_rxeof(struct ix_queue *que)
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loopcount++;
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sendmp = newmp = NULL;
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nbuf = NULL;
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#ifdef RSC
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rsc = 0;
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#endif
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cur->wb.upper.status_error = 0;
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rbuf = &rxr->rx_buffers[i];
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mp = rbuf->buf;
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@ -1988,6 +2004,7 @@ ixgbe_rxeof(struct ix_queue *que)
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* Figure out the next descriptor
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* of this frame.
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*/
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#ifdef RSC
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if (rxr->hw_rsc == TRUE) {
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rsc = ixgbe_rsc_count(cur);
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rxr->rsc_num += (rsc - 1);
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@ -1995,7 +2012,9 @@ ixgbe_rxeof(struct ix_queue *que)
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if (rsc) { /* Get hardware index */
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nextp = ((staterr & IXGBE_RXDADV_NEXTP_MASK) >>
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IXGBE_RXDADV_NEXTP_SHIFT);
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} else { /* Just sequential */
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} else
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#endif
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{ /* Just sequential */
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nextp = i + 1;
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if (nextp == sc->num_rx_desc)
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nextp = 0;
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@ -2345,35 +2364,20 @@ ixgbe_allocate_queues(struct ixgbe_softc *sc)
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int txconf = 0, rxconf = 0;
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/* First, allocate the top level queue structs */
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sc->queues = (struct ix_queue *)malloc(sizeof(struct ix_queue) *
|
||||
sc->num_queues, M_DEVBUF, M_NOWAIT | M_ZERO);
|
||||
if (sc->queues == NULL) {
|
||||
aprint_error_dev(dev, "Unable to allocate queue memory\n");
|
||||
error = ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
sc->queues = kmem_zalloc(sizeof(struct ix_queue) * sc->num_queues,
|
||||
KM_SLEEP);
|
||||
|
||||
/* Second, allocate the TX ring struct memory */
|
||||
sc->tx_rings = (struct tx_ring *)malloc(sizeof(struct tx_ring) *
|
||||
sc->num_queues, M_DEVBUF, M_NOWAIT | M_ZERO);
|
||||
if (sc->tx_rings == NULL) {
|
||||
aprint_error_dev(dev, "Unable to allocate TX ring memory\n");
|
||||
error = ENOMEM;
|
||||
goto tx_fail;
|
||||
}
|
||||
sc->tx_rings = kmem_zalloc(sizeof(struct tx_ring) * sc->num_queues,
|
||||
KM_SLEEP);
|
||||
|
||||
/* Third, allocate the RX ring */
|
||||
sc->rx_rings = (struct rx_ring *)malloc(sizeof(struct rx_ring) *
|
||||
sc->num_queues, M_DEVBUF, M_NOWAIT | M_ZERO);
|
||||
if (sc->rx_rings == NULL) {
|
||||
aprint_error_dev(dev, "Unable to allocate RX ring memory\n");
|
||||
error = ENOMEM;
|
||||
goto rx_fail;
|
||||
}
|
||||
sc->rx_rings = kmem_zalloc(sizeof(struct rx_ring) * sc->num_queues,
|
||||
KM_SLEEP);
|
||||
|
||||
/* For the ring itself */
|
||||
tsize = roundup2(sc->num_tx_desc * sizeof(union ixgbe_adv_tx_desc),
|
||||
DBA_ALIGN);
|
||||
tsize = sc->num_tx_desc * sizeof(union ixgbe_adv_tx_desc);
|
||||
KASSERT((tsize % DBA_ALIGN) == 0);
|
||||
|
||||
/*
|
||||
* Now set up the TX queues, txconf is needed to handle the
|
||||
|
|
@ -2429,8 +2433,8 @@ ixgbe_allocate_queues(struct ixgbe_softc *sc)
|
|||
/*
|
||||
* Next the RX queues...
|
||||
*/
|
||||
rsize = roundup2(sc->num_rx_desc * sizeof(union ixgbe_adv_rx_desc),
|
||||
DBA_ALIGN);
|
||||
rsize = sc->num_rx_desc * sizeof(union ixgbe_adv_rx_desc);
|
||||
KASSERT((rsize % DBA_ALIGN) == 0);
|
||||
for (int i = 0; i < sc->num_queues; i++, rxconf++) {
|
||||
rxr = &sc->rx_rings[i];
|
||||
/* Set up some basics */
|
||||
|
|
@ -2488,12 +2492,9 @@ err_rx_desc:
|
|||
err_tx_desc:
|
||||
for (txr = sc->tx_rings; txconf > 0; txr++, txconf--)
|
||||
ixgbe_dma_free(sc, &txr->txdma);
|
||||
free(sc->rx_rings, M_DEVBUF);
|
||||
rx_fail:
|
||||
free(sc->tx_rings, M_DEVBUF);
|
||||
tx_fail:
|
||||
free(sc->queues, M_DEVBUF);
|
||||
fail:
|
||||
kmem_free(sc->rx_rings, sizeof(struct rx_ring) * sc->num_queues);
|
||||
kmem_free(sc->tx_rings, sizeof(struct tx_ring) * sc->num_queues);
|
||||
kmem_free(sc->queues, sizeof(struct ix_queue) * sc->num_queues);
|
||||
return (error);
|
||||
} /* ixgbe_allocate_queues */
|
||||
|
||||
|
|
@ -2515,5 +2516,5 @@ ixgbe_free_queues(struct ixgbe_softc *sc)
|
|||
que = &sc->queues[i];
|
||||
mutex_destroy(&que->dc_mtx);
|
||||
}
|
||||
free(sc->queues, M_DEVBUF);
|
||||
kmem_free(sc->queues, sizeof(struct ix_queue) * sc->num_queues);
|
||||
} /* ixgbe_free_queues */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: ixgbe.c,v 1.88.2.58 2023/10/18 14:23:15 martin Exp $ */
|
||||
/* $NetBSD: ixgbe.c,v 1.88.2.59 2024/02/03 12:17:03 martin Exp $ */
|
||||
|
||||
/******************************************************************************
|
||||
|
||||
|
|
@ -64,7 +64,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: ixgbe.c,v 1.88.2.58 2023/10/18 14:23:15 martin Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: ixgbe.c,v 1.88.2.59 2024/02/03 12:17:03 martin Exp $");
|
||||
|
||||
#ifdef _KERNEL_OPT
|
||||
#include "opt_inet.h"
|
||||
|
|
@ -718,7 +718,7 @@ ixgbe_initialize_transmit_units(struct ixgbe_softc *sc)
|
|||
|
||||
txr->txr_no_space = false;
|
||||
|
||||
/* Disable Head Writeback */
|
||||
/* Disable relax ordering */
|
||||
/*
|
||||
* Note: for X550 series devices, these registers are actually
|
||||
* prefixed with TPH_ instead of DCA_, but the addresses and
|
||||
|
|
@ -1599,7 +1599,7 @@ ixgbe_update_stats_counters(struct ixgbe_softc *sc)
|
|||
struct ixgbe_hw *hw = &sc->hw;
|
||||
struct ixgbe_hw_stats *stats = &sc->stats.pf;
|
||||
u32 missed_rx = 0, bprc, lxontxc, lxofftxc;
|
||||
u64 total, total_missed_rx = 0;
|
||||
u64 total, total_missed_rx = 0, total_qprdc = 0;
|
||||
uint64_t crcerrs, illerrc, rlec, ruc, rfc, roc, rjc;
|
||||
unsigned int queue_counters;
|
||||
int i;
|
||||
|
|
@ -1618,13 +1618,18 @@ ixgbe_update_stats_counters(struct ixgbe_softc *sc)
|
|||
IXGBE_EVC_REGADD(hw, stats, IXGBE_QPRC(i), qprc[i]);
|
||||
IXGBE_EVC_REGADD(hw, stats, IXGBE_QPTC(i), qptc[i]);
|
||||
if (hw->mac.type >= ixgbe_mac_82599EB) {
|
||||
uint32_t qprdc;
|
||||
|
||||
IXGBE_EVC_ADD(&stats->qbrc[i],
|
||||
IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)) +
|
||||
((u64)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32));
|
||||
IXGBE_EVC_ADD(&stats->qbtc[i],
|
||||
IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)) +
|
||||
((u64)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32));
|
||||
IXGBE_EVC_REGADD(hw, stats, IXGBE_QPRDC(i), qprdc[i]);
|
||||
/* QPRDC will be added to iqdrops. */
|
||||
qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
|
||||
IXGBE_EVC_ADD(&stats->qprdc[i], qprdc);
|
||||
total_qprdc += qprdc;
|
||||
} else {
|
||||
/* 82598 */
|
||||
IXGBE_EVC_REGADD(hw, stats, IXGBE_QBRC(i), qbrc[i]);
|
||||
|
|
@ -1758,7 +1763,7 @@ ixgbe_update_stats_counters(struct ixgbe_softc *sc)
|
|||
ifp->if_collisions = 0;
|
||||
|
||||
/* Rx Errors */
|
||||
ifp->if_iqdrops += total_missed_rx;
|
||||
ifp->if_iqdrops += total_missed_rx + total_qprdc;
|
||||
|
||||
/*
|
||||
* Aggregate following types of errors as RX errors:
|
||||
|
|
@ -3529,7 +3534,7 @@ static int
|
|||
ixgbe_allocate_pci_resources(struct ixgbe_softc *sc,
|
||||
const struct pci_attach_args *pa)
|
||||
{
|
||||
pcireg_t memtype, csr;
|
||||
pcireg_t memtype, csr;
|
||||
device_t dev = sc->dev;
|
||||
bus_addr_t addr;
|
||||
int flags;
|
||||
|
|
@ -4081,6 +4086,7 @@ ixgbe_init_locked(struct ixgbe_softc *sc)
|
|||
txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txr->me));
|
||||
txdctl |= IXGBE_TXDCTL_ENABLE;
|
||||
/* Set WTHRESH to 8, burst writeback */
|
||||
txdctl &= ~IXGBE_TXDCTL_WTHRESH_MASK;
|
||||
txdctl |= IXGBE_TX_WTHRESH << IXGBE_TXDCTL_WTHRESH_SHIFT;
|
||||
/*
|
||||
* When the internal queue falls below PTHRESH (32),
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: ixgbe.h,v 1.24.6.29 2023/10/18 14:23:15 martin Exp $ */
|
||||
/* $NetBSD: ixgbe.h,v 1.24.6.30 2024/02/03 12:17:03 martin Exp $ */
|
||||
|
||||
/******************************************************************************
|
||||
SPDX-License-Identifier: BSD-3-Clause
|
||||
|
|
@ -325,7 +325,7 @@ struct ix_queue {
|
|||
struct ixgbe_softc *sc;
|
||||
u32 msix; /* This queue's MSI-X vector */
|
||||
u32 eitr_setting;
|
||||
u32 me;
|
||||
u8 me;
|
||||
struct resource *res;
|
||||
int busy;
|
||||
struct tx_ring *txr;
|
||||
|
|
@ -357,7 +357,7 @@ struct ix_queue {
|
|||
struct tx_ring {
|
||||
struct ixgbe_softc *sc;
|
||||
kmutex_t tx_mtx;
|
||||
u32 me;
|
||||
u8 me;
|
||||
u32 tail;
|
||||
int busy;
|
||||
union ixgbe_adv_tx_desc *tx_base;
|
||||
|
|
@ -376,9 +376,11 @@ struct tx_ring {
|
|||
void *txr_si;
|
||||
bool txr_no_space; /* Like IFF_OACTIVE */
|
||||
|
||||
#ifdef IXGBE_FDIR
|
||||
/* Flow Director */
|
||||
u16 atr_sample;
|
||||
u16 atr_count;
|
||||
#endif
|
||||
|
||||
u64 bytes; /* Used for AIM */
|
||||
u64 packets;
|
||||
|
|
@ -405,15 +407,17 @@ struct tx_ring {
|
|||
struct rx_ring {
|
||||
struct ixgbe_softc *sc;
|
||||
kmutex_t rx_mtx;
|
||||
u32 me;
|
||||
u8 me;
|
||||
u32 tail;
|
||||
union ixgbe_adv_rx_desc *rx_base;
|
||||
struct ixgbe_dma_alloc rxdma;
|
||||
#ifdef LRO
|
||||
struct lro_ctrl lro;
|
||||
#endif /* LRO */
|
||||
bool lro_enabled;
|
||||
#endif /* LRO */
|
||||
#ifdef RSC
|
||||
bool hw_rsc;
|
||||
#endif
|
||||
bool vtag_strip;
|
||||
bool discard_multidesc;
|
||||
u16 next_to_refresh;
|
||||
|
|
@ -435,10 +439,9 @@ struct rx_ring {
|
|||
struct evcnt rx_bytes;
|
||||
struct evcnt rx_discarded;
|
||||
struct evcnt no_mbuf;
|
||||
#ifdef RSC
|
||||
u64 rsc_num;
|
||||
|
||||
/* Flow Director */
|
||||
u64 flm;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct ixgbe_vf {
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: ixgbe_type.h,v 1.22.2.21 2023/10/18 14:23:15 martin Exp $ */
|
||||
/* $NetBSD: ixgbe_type.h,v 1.22.2.22 2024/02/03 12:17:03 martin Exp $ */
|
||||
|
||||
/******************************************************************************
|
||||
SPDX-License-Identifier: BSD-3-Clause
|
||||
|
|
@ -2625,6 +2625,7 @@ enum {
|
|||
/* Transmit Config masks */
|
||||
#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Ena specific Tx Queue */
|
||||
#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */
|
||||
#define IXGBE_TXDCTL_WTHRESH_MASK 0x007f0000
|
||||
#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
|
||||
/* Enable short packet padding to 64 bytes */
|
||||
#define IXGBE_TX_PAD_ENABLE 0x00000400
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: ixv.c,v 1.56.2.43 2023/10/18 14:23:15 martin Exp $ */
|
||||
/* $NetBSD: ixv.c,v 1.56.2.44 2024/02/03 12:17:03 martin Exp $ */
|
||||
|
||||
/******************************************************************************
|
||||
|
||||
|
|
@ -35,7 +35,7 @@
|
|||
/*$FreeBSD: head/sys/dev/ixgbe/if_ixv.c 331224 2018-03-19 20:55:05Z erj $*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: ixv.c,v 1.56.2.43 2023/10/18 14:23:15 martin Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: ixv.c,v 1.56.2.44 2024/02/03 12:17:03 martin Exp $");
|
||||
|
||||
#ifdef _KERNEL_OPT
|
||||
#include "opt_inet.h"
|
||||
|
|
@ -848,7 +848,6 @@ ixv_init_locked(struct ixgbe_softc *sc)
|
|||
|
||||
/* Inform the stack we're ready */
|
||||
ifp->if_flags |= IFF_RUNNING;
|
||||
ifp->if_flags &= ~IFF_OACTIVE;
|
||||
|
||||
/* And now turn on interrupts */
|
||||
ixv_enable_intr(sc);
|
||||
|
|
@ -1491,7 +1490,7 @@ ixv_stop_locked(void *arg)
|
|||
ixv_disable_intr(sc);
|
||||
|
||||
/* Tell the stack that the interface is no longer active */
|
||||
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
|
||||
ifp->if_flags &= ~IFF_RUNNING;
|
||||
|
||||
hw->mac.ops.reset_hw(hw);
|
||||
sc->hw.adapter_stopped = FALSE;
|
||||
|
|
@ -1512,8 +1511,8 @@ static int
|
|||
ixv_allocate_pci_resources(struct ixgbe_softc *sc,
|
||||
const struct pci_attach_args *pa)
|
||||
{
|
||||
pcireg_t memtype, csr;
|
||||
device_t dev = sc->dev;
|
||||
pcireg_t memtype, csr;
|
||||
device_t dev = sc->dev;
|
||||
bus_addr_t addr;
|
||||
int flags;
|
||||
|
||||
|
|
@ -1711,6 +1710,7 @@ ixv_initialize_transmit_units(struct ixgbe_softc *sc)
|
|||
|
||||
/* Set WTHRESH to 8, burst writeback */
|
||||
txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j));
|
||||
txdctl &= ~IXGBE_TXDCTL_WTHRESH_MASK;
|
||||
txdctl |= IXGBE_TX_WTHRESH << IXGBE_TXDCTL_WTHRESH_SHIFT;
|
||||
IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j), txdctl);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue