PCI Interrupt router support for VIA VT823[1357] Southbridges.
From OpenBSD.
This commit is contained in:
xtraeme
parent
264b791562
commit
37a21a6320
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@ -1,4 +1,4 @@
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# $NetBSD: files.i386,v 1.275 2005/12/31 17:55:55 xtraeme Exp $
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# $NetBSD: files.i386,v 1.276 2006/01/01 12:12:43 xtraeme Exp $
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#
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# new style config file for i386 architecture
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#
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@ -166,6 +166,7 @@ file arch/i386/pci/opti82c558.c pcibios & pci_intr_fixup
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file arch/i386/pci/opti82c700.c pcibios & pci_intr_fixup
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file arch/i386/pci/sis85c503.c pcibios & pci_intr_fixup
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file arch/i386/pci/via82c586.c pcibios & pci_intr_fixup
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file arch/i386/pci/via8231.c pcibios & pci_intr_fixup
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file arch/i386/pci/amd756.c pcibios & pci_intr_fixup
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file arch/i386/pci/ali1543.c pcibios & pci_intr_fixup
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file arch/i386/pci/pci_bus_fixup.c pci_bus_fixup
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@ -1,4 +1,4 @@
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/* $NetBSD: pci_intr_fixup.c,v 1.35 2005/12/26 19:24:00 perry Exp $ */
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/* $NetBSD: pci_intr_fixup.c,v 1.36 2006/01/01 12:12:44 xtraeme Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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@ -67,7 +67,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_intr_fixup.c,v 1.35 2005/12/26 19:24:00 perry Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pci_intr_fixup.c,v 1.36 2006/01/01 12:12:44 xtraeme Exp $");
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#include "opt_pcibios.h"
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#include "opt_pcifixup.h"
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@ -171,6 +171,15 @@ const struct pciintr_icu_table {
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{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C686A_ISA,
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via82c586_init },
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{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8231,
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via8231_init },
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{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8233A,
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via8231_init },
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{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8235,
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via8231_init },
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{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237,
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via8231_init },
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{ PCI_VENDOR_SIS, PCI_PRODUCT_SIS_85C503,
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sis85c503_init },
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@ -1,4 +1,4 @@
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/* $NetBSD: pci_intr_fixup.h,v 1.7 2005/12/26 19:24:00 perry Exp $ */
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/* $NetBSD: pci_intr_fixup.h,v 1.8 2006/01/01 12:12:44 xtraeme Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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@ -63,6 +63,8 @@ int opti82c700_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
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pciintr_icu_tag_t *, pciintr_icu_handle_t *);
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int via82c586_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
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pciintr_icu_tag_t *, pciintr_icu_handle_t *);
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int via8231_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
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pciintr_icu_tag_t *, pciintr_icu_handle_t *);
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int sis85c503_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
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pciintr_icu_tag_t *, pciintr_icu_handle_t *);
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int amd756_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
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@ -0,0 +1,319 @@
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/* $NetBSD: via8231.c,v 1.1 2006/01/01 12:12:44 xtraeme Exp $ */
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/* OpenBSD: via8231.c,v 1.6 2005/10/27 16:41:06 mickey Exp */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 2005, by Michael Shalayeff
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* Copyright (c) 2003, by Matthew Gream
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Support for the VIA Technologies Inc. VIA VT823[1357] PCI to ISA Bridge
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* Based upon documentation:
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* 1. VIA VT8231 South Bridge, Revision 1.85 (March 11, 2002), pg 73
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* 2. VIA VT8237R South Bridge, Revision 2.06 (December 15, 2004), pg 100
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* Derived from amd756.c
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: via8231.c,v 1.1 2006/01/01 12:12:44 xtraeme Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <machine/intr.h>
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#include <machine/bus.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <i386/pci/pci_intr_fixup.h>
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#include <i386/pci/via8231reg.h>
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struct via8231_handle {
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bus_space_tag_t ph_iot;
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bus_space_handle_t ph_regs_ioh;
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pci_chipset_tag_t ph_pc;
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pcitag_t ph_tag;
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int flags;
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#define VT8237 0x0001
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};
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int via8231_getclink(pciintr_icu_handle_t, int, int *);
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int via8231_get_intr(pciintr_icu_handle_t, int, int *);
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int via8231_set_intr(pciintr_icu_handle_t, int, int);
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int via8231_get_trigger(pciintr_icu_handle_t, int, int *);
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int via8231_set_trigger(pciintr_icu_handle_t, int, int);
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#ifdef VIA8231_DEBUG
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static void via8231_pir_dump(const char*, struct via8231_handle *);
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#endif
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const struct pciintr_icu via8231_pci_icu = {
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via8231_getclink,
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via8231_get_intr,
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via8231_set_intr,
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via8231_get_trigger,
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via8231_set_trigger,
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};
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struct mask_shft_pair {
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int mask;
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int shft;
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};
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static const struct mask_shft_pair via8231_routing_cnfg[VIA8231_LINK_MAX+1] = {
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{ 0x0f, 0+4 }, /*PINTA#*/
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{ 0x0f, 8+0 }, /*PINTB#*/
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{ 0x0f, 8+4 }, /*PINTC#*/
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{ 0x0f, 16+4 } /*PINTD#*/
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};
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#define VIA8231_GET_TRIGGER_CNFG(reg, pirq) \
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((reg) & (1 << (3 - (clink & 3))))
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#define VIA8231_SET_TRIGGER_CNFG(reg, clink, cfg) \
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(((reg) & ~(1 << (3 - (clink & 3)))) | ((cfg) << (3 - (clink & 3))))
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#define VIA8231_GET_ROUTING_CNFG(reg, pirq) \
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(((reg) >> via8231_routing_cnfg[(pirq)].shft) & \
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via8231_routing_cnfg[(pirq)].mask)
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#define VIA8231_SET_ROUTING_CNFG(reg, pirq, cfg) \
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(((reg) & ~(via8231_routing_cnfg[(pirq)].mask << \
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via8231_routing_cnfg[(pirq)].shft)) | \
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(((cfg) & via8231_routing_cnfg[(pirq)].mask) << \
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via8231_routing_cnfg[(pirq)].shft))
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int
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via8231_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag,
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pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp)
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{
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struct via8231_handle *ph;
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pcireg_t id;
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ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT);
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if (ph == NULL)
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return (1);
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ph->ph_iot = iot;
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ph->ph_pc = pc;
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ph->ph_tag = tag;
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id = pci_conf_read(pc, tag, PCI_ID_REG);
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ph->flags = PCI_VENDOR(id) == PCI_VENDOR_VIATECH &&
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PCI_PRODUCT(id) == PCI_PRODUCT_VIATECH_VT8231? 0 : VT8237;
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*ptagp = &via8231_pci_icu;
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*phandp = ph;
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#ifdef VIA8231_DEBUG
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via8231_pir_dump("via8231_init", ph);
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#endif
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return 0;
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}
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int
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via8231_getclink(pciintr_icu_handle_t v, int link, int *clinkp)
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{
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struct via8231_handle *ph = v;
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if ((ph->flags & VT8237) && !VIA8237_LINK_LEGAL(link - 1))
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return (1);
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if (!(ph->flags & VT8237) && !VIA8231_LINK_LEGAL(link - 1))
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return (1);
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*clinkp = link - 1;
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return (0);
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}
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int
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via8231_get_intr(pciintr_icu_handle_t v, int clink, int *irqp)
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{
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struct via8231_handle *ph = v;
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int reg, val;
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if (VIA8237_LINK_LEGAL(clink) == 0)
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return (1);
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if (VIA8231_LINK_LEGAL(clink)) {
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reg = VIA8231_GET_ROUTING(ph);
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val = VIA8231_GET_ROUTING_CNFG(reg, clink);
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} else {
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reg = VIA8237_GET_ROUTING(ph);
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val = (reg >> ((clink & 3) * 4)) & 0xf;
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}
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*irqp = (val == VIA8231_ROUTING_CNFG_DISABLED) ?
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X86_PCI_INTERRUPT_LINE_NO_CONNECTION : val;
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return (0);
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}
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int
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via8231_set_intr(pciintr_icu_handle_t v, int clink, int irq)
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{
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struct via8231_handle *ph = v;
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int reg;
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if (VIA8237_LINK_LEGAL(clink) == 0 || VIA8231_PIRQ_LEGAL(irq) == 0)
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return (1);
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#ifdef VIA8231_DEBUG
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printf("via8231_set_intr: link(%02x) --> irq(%02x)\n", clink, irq);
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via8231_pir_dump("via8231_set_intr: ", ph);
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#endif
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if (VIA8231_LINK_LEGAL(clink)) {
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reg = VIA8231_GET_ROUTING(ph);
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VIA8231_SET_ROUTING(ph,
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VIA8231_SET_ROUTING_CNFG(reg, clink, irq));
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} else {
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reg = VIA8237_GET_ROUTING(ph);
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VIA8237_SET_ROUTING(ph, (reg & ~(0xf << (clink & 3))) |
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((irq & 0xf) << (clink & 3)));
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}
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return (0);
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}
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int
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via8231_get_trigger(pciintr_icu_handle_t v, int irq, int *triggerp)
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{
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struct via8231_handle *ph = v;
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int reg, clink, m, pciirq;
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if (VIA8231_PIRQ_LEGAL(irq) == 0)
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return (1);
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m = ph->flags & VT8237? VIA8237_LINK_MAX : VIA8231_LINK_MAX;
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for (clink = 0; clink <= m; clink++) {
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via8231_get_intr(v, clink, &pciirq);
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if (pciirq == irq) {
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reg = VIA8231_LINK_LEGAL(clink)?
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VIA8231_GET_TRIGGER(ph):
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VIA8237_GET_TRIGGER(ph);
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*triggerp = VIA8231_GET_TRIGGER_CNFG(reg, clink)?
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IST_EDGE : IST_LEVEL;
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return (0);
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}
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}
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return (1);
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}
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int
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via8231_set_trigger(pciintr_icu_handle_t v, int irq, int trigger)
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{
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struct via8231_handle *ph = v;
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int reg, clink, m, pciirq;
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if (VIA8231_PIRQ_LEGAL(irq) == 0 || VIA8231_TRIG_LEGAL(trigger) == 0)
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return (1);
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#ifdef VIA8231_DEBUG
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printf("via8231_set_trig: irq(%02x) --> trig(%02x)\n", irq, trigger);
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via8231_pir_dump("via8231_set_trig: ", ph);
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#endif
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m = ph->flags & VT8237? VIA8237_LINK_MAX : VIA8231_LINK_MAX;
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for (clink = 0; clink <= VIA8231_LINK_MAX; clink++) {
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via8231_get_intr(v, clink, &pciirq);
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if (pciirq == irq) {
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reg = VIA8231_LINK_LEGAL(clink)?
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VIA8231_GET_TRIGGER(ph):
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VIA8237_GET_TRIGGER(ph);
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switch (trigger) {
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case IST_LEVEL:
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reg = VIA8231_SET_TRIGGER_CNFG(reg, clink,
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VIA8231_TRIGGER_CNFG_LEVEL);
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break;
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case IST_EDGE:
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reg = VIA8231_SET_TRIGGER_CNFG(reg, clink,
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VIA8231_TRIGGER_CNFG_EDGE);
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break;
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default:
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return (1);
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}
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if (VIA8231_LINK_LEGAL(clink))
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VIA8231_SET_TRIGGER(ph, reg);
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else
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VIA8237_SET_TRIGGER(ph, reg);
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return (0);
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}
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}
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return (1);
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}
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#ifdef VIA8231_DEBUG
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static void
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via8231_pir_dump(const char *m, struct via8231_handle *ph)
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{
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int a, b;
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a = VIA8231_GET_TRIGGER(ph);
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b = VIA8231_GET_ROUTING(ph);
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printf("%s STATE: trigger(%02x), routing(%08x)\n", m, a, b);
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}
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#endif
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@ -0,0 +1,137 @@
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/* $NetBSD: via8231reg.h,v 1.1 2006/01/01 12:12:44 xtraeme Exp $ */
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/* OpenBSD: via8231reg.h,v 1.4 2005/10/26 21:38:28 mickey Exp */
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/*
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* Copyright (c) 2005, by Michael Shalayeff
|
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* Copyright (c) 2003, by Matthew Gream
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* Copyright (c) 1999, by UCHIYAMA Yasushi
|
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* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. The name of the developer may NOT be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Register definitions for the VIA8231 PCI to ISA Bridge
|
||||
*/
|
||||
|
||||
/*
|
||||
* Edge Triggered Interrupt Select register. (0x54)
|
||||
* bits 7-4: reserved
|
||||
* bit 3: Edge Triggered Interrupt Select for PCI Interrupt A
|
||||
* bit 2: Edge Triggered Interrupt Select for PCI Interrupt B
|
||||
* bit 1: Edge Triggered Interrupt Select for PCI Interrupt C
|
||||
* bit 0: Edge Triggered Interrupt Select for PCI Interrupt D
|
||||
* 0 = Non-invert (level)
|
||||
* 1 = Invert (edge)
|
||||
*
|
||||
* PIRQ Select register. (0x55 - 0x57)
|
||||
* (0x55)
|
||||
* bits 7-4: PINTA# Routing
|
||||
* bits 3-0: reserved
|
||||
* (0x56)
|
||||
* bits 7-4: PINTC# Routing
|
||||
* bits 3-0: PINTB# Routing
|
||||
* (0x57)
|
||||
* bits 7-4: PINTD# Routing
|
||||
* bits 3-0: reserved
|
||||
* PIRQ Select register. (0x44 - 0x47)
|
||||
* (0x44)
|
||||
* bits 7-4: PINTF# Routing
|
||||
* bits 3-0: PINTE# Routing
|
||||
* (0x45)
|
||||
* bits 7-4: PINTH# Routing
|
||||
* bits 3-0: PINTG# Routing
|
||||
* (0x46)
|
||||
* bit 4: EFGH/ABCD share (1 -- use above mappings)
|
||||
* bit 3: Edge Triggered Interrupt Select for PCI Interrupt H
|
||||
* bit 2: Edge Triggered Interrupt Select for PCI Interrupt G
|
||||
* bit 1: Edge Triggered Interrupt Select for PCI Interrupt F
|
||||
* bit 0: Edge Triggered Interrupt Select for PCI Interrupt E
|
||||
*
|
||||
* 0000: Disabled 0100: IRQ4 1000: Reserved 1100: IRQ12
|
||||
* 0001: IRQ1 0101: IRQ5 1001: IRQ9 1101: Reserved
|
||||
* 0010: Reserved 0110: IRQ6 1010: IRQ10 1110: IRQ14
|
||||
* 0011: IRQ3 0111: IRQ7 1011: IRQ11 1111: IRQ15
|
||||
*/
|
||||
#define VIA8231_CFG_PIR 0x54
|
||||
#define VIA8237_CFG_PIR 0x44
|
||||
|
||||
#define VIA8231_TRIGGER_CNFG_MASK 0x000000ff
|
||||
#define VIA8231_TRIGGER_CNFG_SHFT 0
|
||||
#define VIA8237_TRIGGER_CNFG_MASK 0x000f0000
|
||||
#define VIA8237_TRIGGER_CNFG_SHFT 16
|
||||
#define VIA8231_TRIGGER_CNFG_LEVEL 0
|
||||
#define VIA8231_TRIGGER_CNFG_EDGE 1
|
||||
#define VIA8237_TRIGGER_CNFG_ENA 0x00100000
|
||||
|
||||
#define VIA8231_GET_TRIGGER(ph) \
|
||||
((pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR) \
|
||||
& VIA8231_TRIGGER_CNFG_MASK) >> VIA8231_TRIGGER_CNFG_SHFT)
|
||||
#define VIA8237_GET_TRIGGER(ph) \
|
||||
((pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR) \
|
||||
& VIA8237_TRIGGER_CNFG_MASK) >> VIA8237_TRIGGER_CNFG_SHFT)
|
||||
|
||||
#define VIA8231_SET_TRIGGER(ph, n) \
|
||||
pci_conf_write((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR, \
|
||||
(pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR) \
|
||||
& ~VIA8231_TRIGGER_CNFG_MASK) | ((n) << VIA8231_TRIGGER_CNFG_SHFT))
|
||||
#define VIA8237_SET_TRIGGER(ph, n) \
|
||||
pci_conf_write((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR, \
|
||||
(pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR) \
|
||||
& ~VIA8237_TRIGGER_CNFG_MASK) | ((n) << VIA8237_TRIGGER_CNFG_SHFT))
|
||||
|
||||
|
||||
#define VIA8231_ROUTING_CNFG_MASK 0xffffff00
|
||||
#define VIA8231_ROUTING_CNFG_SHFT 8 /* skip 0x54 triggers */
|
||||
#define VIA8231_ROUTING_CNFG_DISABLED 0
|
||||
#define VIA8237_ROUTING_CNFG_MASK 0xffff
|
||||
#define VIA8237_ROUTING_CNFG_SHFT 0
|
||||
|
||||
#define VIA8231_GET_ROUTING(ph) \
|
||||
((pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR) \
|
||||
& VIA8231_ROUTING_CNFG_MASK) >> VIA8231_ROUTING_CNFG_SHFT)
|
||||
#define VIA8237_GET_ROUTING(ph) \
|
||||
((pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR) \
|
||||
& VIA8237_ROUTING_CNFG_MASK) >> VIA8237_ROUTING_CNFG_SHFT)
|
||||
|
||||
#define VIA8231_SET_ROUTING(ph, n) \
|
||||
pci_conf_write((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR, \
|
||||
(pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR) \
|
||||
& ~VIA8231_ROUTING_CNFG_MASK) | ((n) << VIA8231_ROUTING_CNFG_SHFT))
|
||||
#define VIA8237_SET_ROUTING(ph, n) \
|
||||
pci_conf_write((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR, \
|
||||
(pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR) \
|
||||
& ~VIA8237_ROUTING_CNFG_MASK) | \
|
||||
((n) << VIA8237_ROUTING_CNFG_SHFT) | VIA8237_TRIGGER_CNFG_ENA)
|
||||
|
||||
|
||||
#define VIA8231_PIRQ_MASK 0xdefa
|
||||
#define VIA8231_PIRQ_LEGAL(irq) \
|
||||
((irq) >= 0 && (irq) <= 15 && ((1 << (irq)) & VIA8231_PIRQ_MASK))
|
||||
#define VIA8231_LINK_MAX 3
|
||||
#define VIA8237_LINK_MAX 7
|
||||
#define VIA8231_LINK_LEGAL(link) \
|
||||
((link) >= 0 && (link) <= VIA8231_LINK_MAX)
|
||||
#define VIA8237_LINK_LEGAL(link) \
|
||||
((link) >= 0 && (link) <= VIA8237_LINK_MAX)
|
||||
#define VIA8231_TRIG_LEGAL(trig) \
|
||||
((trig) == IST_LEVEL || (trig) == IST_EDGE)
|
||||
|
||||
Loading…
Reference in New Issue