More patches for ARC from Noriyuki Soda:
* commit isapnpvar.h changes required for ARC to support plain isa.
* fixup mistake over mips/include/cpuregs.h.
* mips/mips_machdep.c:
set L2 cache-size for arc, cleanup use of L2cache present
vs L2 cache-size variables. check for no L2 cache on kernels
configured to require one. misc cleanups.
* mips/mpis/trap.c: more locore stack-traceback label cleanup.
XXX Locore callbacks for mips3, mips4, r4600 cacheflush need more work.
This commit is contained in:
jonathan
parent
948d228b24
commit
379c9be4a8
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@ -1,4 +1,4 @@
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/* $NetBSD: cpuregs.h,v 1.15 1998/09/11 16:46:31 jonathan Exp $ */
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/* $NetBSD: cpuregs.h,v 1.16 1998/10/01 00:42:37 jonathan Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -502,7 +502,8 @@
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#define MIPS3_TLB_PHYS_PAGE_SHIFT 6
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#define MIPS3_TLB_PF_NUM 0x3fffffc0
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#define MIPS3_TLB_ATTR_MASK 0x00000038
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#define MIPS3_TLB_ATTR_SHIFT 3
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#define MIPS3_TLB_MOD_BIT 0x00000004
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#define MIPS3_TLB_VALID_BIT 0x00000002
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#define MIPS3_TLB_GLOBAL_BIT 0x00000001
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@ -516,7 +517,7 @@
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* 4: cacheable, coherent, write-back, exclusive (exclusive)
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* 5: cacheable, coherent, write-back, exclusive on write (sharable)
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* 6: cacheable, coherent, write-back, update on write (update)
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* 7: cacheable, ?, ?, ?, ?
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* 7: uncached, accelerated (gather STORE operations)
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*/
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#define MIPS3_TLB_ATTR_WT 0 /* IDT */
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#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */
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@ -524,7 +525,7 @@
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#define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */
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#define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */
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#define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */
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#define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */
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#define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */
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/*
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@ -1,4 +1,4 @@
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/* $NetBSD: trap.h,v 1.8 1998/05/19 04:11:50 simonb Exp $ */
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/* $NetBSD: trap.h,v 1.9 1998/10/01 00:42:37 jonathan Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -85,3 +85,13 @@ extern int kdbpeek __P((vm_offset_t addr));
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#define T_VCED 31 /* Virtual coherency data */
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#define T_USER 0x20 /* user-mode flag or'ed with type */
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#ifdef _KERNEL
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extern int (*mips_hardware_intr) __P((u_int mask, u_int pc, u_int statusReg,
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u_int causeReg));
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#endif /* _KERNEL */
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#ifdef _KERNEL
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extern int (*mips_hardware_intr) __P((u_int mask, u_int pc, u_int statusReg,
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u_int causeReg));
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#endif /* _KERNEL */
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@ -1,4 +1,4 @@
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/* $NetBSD: mips_machdep.c,v 1.33 1998/09/14 07:04:06 jonathan Exp $ */
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/* $NetBSD: mips_machdep.c,v 1.34 1998/10/01 00:42:38 jonathan Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -52,7 +52,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.33 1998/09/14 07:04:06 jonathan Exp $");
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__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.34 1998/10/01 00:42:38 jonathan Exp $");
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#include "opt_compat_netbsd.h"
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#include "opt_uvm.h"
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@ -277,7 +277,7 @@ mips3_ConfigCache()
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/*
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* Clear out the I and D caches.
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*/
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mips_L2CachePresent = 0; /* kluge to skip L2 cache flush */
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mips_L2CacheSize = 0; /* kluge to skip L2 cache flush */
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mips3_FlushCache();
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i = *(volatile int *)&snoop_check; /* Read and cache */
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@ -332,6 +332,9 @@ mips3_vector_init()
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mips_L2CachePresent = 1;
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mips_L2CacheSize = 1024 * 1024;
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#endif
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#ifdef arc
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mips_L2CacheSize = mips_L2CachePresent ? 1024 * 1024 : 0;
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#endif
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mips3_FlushCache();
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}
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@ -386,7 +389,9 @@ mips_vector_init()
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mips_num_tlb_entries = MIPS3_TLB_NUM_TLB_ENTRIES;
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mips3_L1TwoWayCache = 0;
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mips3_cacheflush_bug = 0;
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mips3_cacheflush_bug = 1; /* XXX FIXME: probably not needed */
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#if 1 /* XXX FIXME: avoid hangs in mips3_vector_init() */
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mips3_cacheflush_bug = 1;
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#endif
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break;
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case MIPS_R4300:
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cpu_arch = 3;
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@ -436,7 +441,6 @@ mips_vector_init()
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#endif
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#ifdef MIPS3
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case 3:
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case 4:
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mips3_SetWIRED(0);
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mips3_TLBFlush(mips_num_tlb_entries);
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mips3_SetWIRED(MIPS3_TLB_WIRED_ENTRIES);
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@ -532,7 +536,6 @@ cpu_identify()
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printf("QED R4700 Orion CPU");
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#endif
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break;
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break;
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case MIPS_R3TOSH:
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printf("Toshiba R3000 based CPU");
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break;
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@ -663,6 +666,14 @@ cpu_identify()
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* good place to do this is mips_vector_init(),
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* but printf() doesn't work in it.
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*/
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#if !defined(MIPS3_FLUSH)
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if (!mips_L2CachePresent) {
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printf("This kernel doesn't work without L2 cache.\n"
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"Please add \"options MIPS3_FLUSH\""
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"to the kernel config file.\n");
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cpu_reboot(RB_HALT, NULL);
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}
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#endif
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if (mips3_L1TwoWayCache &&
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(mips_L1ICacheLSize < 32 || mips_L1DCacheLSize < 32)) {
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/*
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@ -1,4 +1,4 @@
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/* $NetBSD: trap.c,v 1.92 1998/09/11 16:46:34 jonathan Exp $ */
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/* $NetBSD: trap.c,v 1.93 1998/10/01 00:42:38 jonathan Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -43,7 +43,7 @@
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.92 1998/09/11 16:46:34 jonathan Exp $");
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__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.93 1998/10/01 00:42:38 jonathan Exp $");
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#include "opt_cputype.h" /* which mips CPU levels do we support? */
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#include "opt_inet.h"
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@ -1649,7 +1649,7 @@ specialframe:
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subr = (unsigned) splx;
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else if (pcBetween(cpu_switch, cpu_switch_end))
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subr = (unsigned) cpu_switch;
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else if (pcBetween(idle, cpu_switch)) {
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else if (pcBetween(idle, idle_end)) {
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subr = (unsigned) idle;
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ra = 0;
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goto done;
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@ -1,4 +1,4 @@
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/* $NetBSD: isapnpvar.h,v 1.16 1998/09/05 14:15:26 christos Exp $ */
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/* $NetBSD: isapnpvar.h,v 1.17 1998/10/01 00:42:37 jonathan Exp $ */
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/*-
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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@ -49,12 +49,15 @@
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*/
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struct isapnp_softc;
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#if (alpha + arm32 + atari + bebox + i386 != 1)
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#if (alpha + arc + arm32 + atari + bebox + i386 != 1)
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ERROR: COMPILING FOR UNSUPPORTED MACHINE, OR MORE THAN ONE.
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#endif
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#if alpha
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#include <alpha/isa/isapnp_machdep.h>
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#endif
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#if arc
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#include <arc/isa/isapnp_machdep.h>
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#endif
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#if arm32
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#include <arm32/isa/isapnp_machdep.h>
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#endif
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