regen
This commit is contained in:
drochner
parent
2deceb396c
commit
3752421a75
@ -1,10 +1,10 @@
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/* $NetBSD: miidevs.h,v 1.14 2001/01/07 15:01:06 augustss Exp $ */
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/* $NetBSD: miidevs.h,v 1.15 2001/03/28 14:15:23 drochner Exp $ */
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/*
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* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
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*
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* generated from:
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* NetBSD: miidevs,v 1.14 2001/01/07 15:00:46 augustss Exp
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* NetBSD: miidevs,v 1.15 2001/03/28 14:14:57 drochner Exp
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*/
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/*-
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@ -48,11 +48,15 @@
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* List of known MII OUIs.
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* For a complete list see http://standards.ieee.org/regauth/oui/
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*
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* XXX Vendors do obviously not agree how OUIs (18 bit) are mapped
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* to the 16 bits available in the id registers. The MII_OUI() macro
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* in "mii.h" reflects the most obvious way. If a vendor uses a
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* different mapping, an "xx" prefixed OUI is defined here which is
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* mangled accordingly to compensate.
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* XXX Vendors do obviously not agree how OUIs (24 bit) are mapped
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* to the 22 bits available in the id registers.
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* IEEE 802.3u-1995, subclause 22.2.4.3.1, figure 22-12, depicts the right
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* mapping; the bit positions are defined in IEEE 802-1990, figure 5.2.
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* (There is a formal 802.3 interpretation, number 1-07/98 of July 09 1998,
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* about this.)
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* The MII_OUI() macro in "mii.h" reflects this.
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* If a vendor uses a different mapping, an "xx" prefixed OUI is defined here
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* which is mangled accordingly to compensate.
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*/
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#define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */
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@ -72,29 +76,27 @@
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#define MII_OUI_TSC 0x00c039 /* TDK Semiconductor */
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#define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */
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/* in the 79c873, AMD uses another OUI (which matches Davicom!) */
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#define MII_OUI_xxAMD 0x00606e /* Advanced Micro Devices */
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/* in the 79c873, AMD uses another OUI (which matches reversed Davicom!) */
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#define MII_OUI_xxAMD 0x000676 /* Advanced Micro Devices */
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/* Some Intel 82553's use an alternative OUI. */
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#define MII_OUI_xxINTEL 0x00f800 /* Intel */
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#define MII_OUI_xxINTEL 0x001f00 /* Intel */
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/* some vendors have the bits swapped within bytes
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(ie, ordered as on the wire) */
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#define MII_OUI_xxALTIMA 0x000895 /* Altima Communications */
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/* bad bitorder (bits "g" and "h" (= MSBs byte 1) lost) */
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#define MII_OUI_yyAMD 0x000058 /* Advanced Micro Devices */
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#define MII_OUI_xxBROADCOM 0x000818 /* Broadcom Corporation */
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#define MII_OUI_xxICS 0x00057d /* Integrated Circuit Systems */
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#define MII_OUI_xxSEEQ 0x0005be /* Seeq */
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#define MII_OUI_xxSIS 0x000760 /* Silicon Integrated Systems */
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#define MII_OUI_xxTI 0x100014 /* Texas Instruments */
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#define MII_OUI_xxXAQTI 0x350700 /* XaQti Corp. */
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#define MII_OUI_yyINTEL 0x005500 /* Intel */
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#define MII_OUI_xxMYSON 0x00032d /* Myson Technology */
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#define MII_OUI_xxNATSEMI 0x1000e8 /* National Semiconductor */
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#define MII_OUI_xxQUALSEMI 0x00068a /* Quality Semiconductor */
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#define MII_OUI_xxTSC 0x00039c /* TDK Semiconductor */
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/* Level 1 is completely different - from right to left.
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(Two bits get lost in the third OUI byte.) */
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#define MII_OUI_xxLEVEL1 0x1e0400 /* Level 1 */
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/* bad byteorder (bits "q" and "r" (= LSBs byte 3) lost) */
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#define MII_OUI_xxLEVEL1 0x782000 /* Level 1 */
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#define MII_OUI_xxXAQTI 0xace000 /* XaQti Corp. */
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/* Don't know what's going on here. */
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#define MII_OUI_xxDAVICOM 0x006040 /* Davicom Semiconductor */
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#define MII_OUI_xxDAVICOM 0x000602 /* Davicom Semiconductor */
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/* Contrived vendor for dcphy */
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#define MII_OUI_xxDEC 0x040440 /* Digital Clone */
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@ -105,26 +107,26 @@
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*/
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/* Altima Communications PHYs */
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#define MII_MODEL_xxALTIMA_AC101 0x0021
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#define MII_STR_xxALTIMA_AC101 "AC101 10/100 media interface"
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#define MII_MODEL_ALTIMA_AC101 0x0021
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#define MII_STR_ALTIMA_AC101 "AC101 10/100 media interface"
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/* Advanced Micro Devices PHYs */
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#define MII_MODEL_xxAMD_79C873 0x0000
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#define MII_STR_xxAMD_79C873 "Am79C873 10/100 media interface"
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#define MII_MODEL_AMD_79c973phy 0x0036
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#define MII_STR_AMD_79c973phy "Am79C973 internal PHY"
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#define MII_MODEL_AMD_79c901 0x0037
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#define MII_STR_AMD_79c901 "Am79C901 10 PHY"
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#define MII_MODEL_AMD_79c901home 0x0039
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#define MII_STR_AMD_79c901home "Am79C901 HomePHY"
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#define MII_MODEL_yyAMD_79c973phy 0x0036
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#define MII_STR_yyAMD_79c973phy "Am79C973 internal PHY"
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#define MII_MODEL_yyAMD_79c901 0x0037
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#define MII_STR_yyAMD_79c901 "Am79C901 10 PHY"
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#define MII_MODEL_yyAMD_79c901home 0x0039
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#define MII_STR_yyAMD_79c901home "Am79C901 HomePHY"
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/* Broadcom Corp. PHYs */
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#define MII_MODEL_BROADCOM_3C905C 0x0017
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#define MII_STR_BROADCOM_3C905C "Broadcom 3C905C internal PHY"
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#define MII_MODEL_BROADCOM_BCM5201 0x0021
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#define MII_STR_BROADCOM_BCM5201 "BCM5201 10/100 media interface"
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#define MII_MODEL_xxBROADCOM_BCM5400 0x0004
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#define MII_STR_xxBROADCOM_BCM5400 "BCM5400 1000baseTX PHY"
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#define MII_MODEL_xxBROADCOM_3C905C 0x0017
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#define MII_STR_xxBROADCOM_3C905C "Broadcom 3C905C internal PHY"
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#define MII_MODEL_xxBROADCOM_BCM5201 0x0021
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#define MII_STR_xxBROADCOM_BCM5201 "BCM5201 10/100 media interface"
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#define MII_MODEL_BROADCOM_BCM5400 0x0004
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#define MII_STR_BROADCOM_BCM5400 "BCM5400 1000baseTX PHY"
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/* Davicom Semiconductor PHYs */
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#define MII_MODEL_xxDAVICOM_DM9101 0x0000
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@ -135,59 +137,59 @@
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#define MII_STR_xxDEC_xxDC "DC"
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/* Integrated Circuit Systems PHYs */
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#define MII_MODEL_xxICS_1890 0x0002
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#define MII_STR_xxICS_1890 "ICS1890 10/100 media interface"
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#define MII_MODEL_ICS_1890 0x0002
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#define MII_STR_ICS_1890 "ICS1890 10/100 media interface"
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/* Intel PHYs */
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#define MII_MODEL_xxINTEL_I82553 0x0000
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#define MII_STR_xxINTEL_I82553 "i82553 10/100 media interface"
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#define MII_MODEL_INTEL_I82555 0x0015
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#define MII_STR_INTEL_I82555 "i82555 10/100 media interface"
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#define MII_MODEL_INTEL_I82553 0x0035
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#define MII_STR_INTEL_I82553 "i82553 10/100 media interface"
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#define MII_MODEL_yyINTEL_I82555 0x0015
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#define MII_STR_yyINTEL_I82555 "i82555 10/100 media interface"
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#define MII_MODEL_yyINTEL_I82553 0x0035
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#define MII_STR_yyINTEL_I82553 "i82553 10/100 media interface"
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/* Level 1 PHYs */
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#define MII_MODEL_xxLEVEL1_LXT970 0x0000
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#define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 media interface"
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/* Myson Technology PHYs */
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#define MII_MODEL_MYSON_MTD972 0x0000
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#define MII_STR_MYSON_MTD972 "MTD972 10/100 media interface"
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#define MII_MODEL_xxMYSON_MTD972 0x0000
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#define MII_STR_xxMYSON_MTD972 "MTD972 10/100 media interface"
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/* National Semiconductor PHYs */
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#define MII_MODEL_NATSEMI_DP83840 0x0000
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#define MII_STR_NATSEMI_DP83840 "DP83840 10/100 media interface"
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#define MII_MODEL_NATSEMI_DP83843 0x0001
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#define MII_STR_NATSEMI_DP83843 "DP83843 10/100 media interface"
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#define MII_MODEL_xxNATSEMI_DP83840 0x0000
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#define MII_STR_xxNATSEMI_DP83840 "DP83840 10/100 media interface"
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#define MII_MODEL_xxNATSEMI_DP83843 0x0001
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#define MII_STR_xxNATSEMI_DP83843 "DP83843 10/100 media interface"
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/* Quality Semiconductor PHYs */
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#define MII_MODEL_QUALSEMI_QS6612 0x0000
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#define MII_STR_QUALSEMI_QS6612 "QS6612 10/100 media interface"
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#define MII_MODEL_xxQUALSEMI_QS6612 0x0000
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#define MII_STR_xxQUALSEMI_QS6612 "QS6612 10/100 media interface"
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/* Seeq PHYs */
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#define MII_MODEL_xxSEEQ_80220 0x0003
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#define MII_STR_xxSEEQ_80220 "Seeq 80220 10/100 media interface"
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#define MII_MODEL_xxSEEQ_84220 0x0004
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#define MII_STR_xxSEEQ_84220 "Seeq 84220 10/100 media interface"
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#define MII_MODEL_SEEQ_80220 0x0003
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#define MII_STR_SEEQ_80220 "Seeq 80220 10/100 media interface"
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#define MII_MODEL_SEEQ_84220 0x0004
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#define MII_STR_SEEQ_84220 "Seeq 84220 10/100 media interface"
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/* Silicon Integrated Systems PHYs */
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#define MII_MODEL_xxSIS_900 0x0000
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#define MII_STR_xxSIS_900 "SiS 900 10/100 media interface"
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#define MII_MODEL_SIS_900 0x0000
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#define MII_STR_SIS_900 "SiS 900 10/100 media interface"
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/* Texas Instruments PHYs */
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#define MII_MODEL_xxTI_TLAN10T 0x0001
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#define MII_STR_xxTI_TLAN10T "ThunderLAN 10baseT media interface"
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#define MII_MODEL_xxTI_100VGPMI 0x0002
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#define MII_STR_xxTI_100VGPMI "ThunderLAN 100VG-AnyLan media interface"
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#define MII_MODEL_xxTI_TNETE2101 0x0003
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#define MII_STR_xxTI_TNETE2101 "TNETE2101 media interface"
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#define MII_MODEL_TI_TLAN10T 0x0001
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#define MII_STR_TI_TLAN10T "ThunderLAN 10baseT media interface"
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#define MII_MODEL_TI_100VGPMI 0x0002
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#define MII_STR_TI_100VGPMI "ThunderLAN 100VG-AnyLan media interface"
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#define MII_MODEL_TI_TNETE2101 0x0003
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#define MII_STR_TI_TNETE2101 "TNETE2101 media interface"
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/* TDK Semiconductor PHYs */
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#define MII_MODEL_TSC_78Q2120 0x0014
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#define MII_STR_TSC_78Q2120 "78Q2120 10/100 media interface"
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#define MII_MODEL_TSC_78Q2121 0x0015
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#define MII_STR_TSC_78Q2121 "78Q2121 100baseTX media interface"
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#define MII_MODEL_xxTSC_78Q2120 0x0014
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#define MII_STR_xxTSC_78Q2120 "78Q2120 10/100 media interface"
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#define MII_MODEL_xxTSC_78Q2121 0x0015
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#define MII_STR_xxTSC_78Q2121 "78Q2121 100baseTX media interface"
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/* XaQti Corp. PHYs */
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#define MII_MODEL_XAQTI_XMACII 0x0000
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#define MII_STR_XAQTI_XMACII "XaQti Corp. XMAC II gigabit interface"
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#define MII_MODEL_xxXAQTI_XMACII 0x0000
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#define MII_STR_xxXAQTI_XMACII "XaQti Corp. XMAC II gigabit interface"
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@ -1,10 +1,10 @@
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/* $NetBSD: miidevs_data.h,v 1.4 2001/01/07 15:01:06 augustss Exp $ */
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/* $NetBSD: miidevs_data.h,v 1.5 2001/03/28 14:15:23 drochner Exp $ */
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/*
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* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
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*
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* generated from:
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* NetBSD: miidevs,v 1.14 2001/01/07 15:00:46 augustss Exp
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* NetBSD: miidevs,v 1.15 2001/03/28 14:14:57 drochner Exp
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*/
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/*-
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@ -44,33 +44,33 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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struct mii_knowndev mii_knowndevs[] = {
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{ MII_OUI_xxALTIMA, MII_MODEL_xxALTIMA_AC101, MII_STR_xxALTIMA_AC101 },
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{ MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101, MII_STR_ALTIMA_AC101 },
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{ MII_OUI_xxAMD, MII_MODEL_xxAMD_79C873, MII_STR_xxAMD_79C873 },
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{ MII_OUI_AMD, MII_MODEL_AMD_79c973phy, MII_STR_AMD_79c973phy },
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{ MII_OUI_AMD, MII_MODEL_AMD_79c901, MII_STR_AMD_79c901 },
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{ MII_OUI_AMD, MII_MODEL_AMD_79c901home, MII_STR_AMD_79c901home },
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{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_3C905C, MII_STR_BROADCOM_3C905C },
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{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5201, MII_STR_BROADCOM_BCM5201 },
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{ MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5400, MII_STR_xxBROADCOM_BCM5400 },
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{ MII_OUI_yyAMD, MII_MODEL_yyAMD_79c973phy, MII_STR_yyAMD_79c973phy },
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{ MII_OUI_yyAMD, MII_MODEL_yyAMD_79c901, MII_STR_yyAMD_79c901 },
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{ MII_OUI_yyAMD, MII_MODEL_yyAMD_79c901home, MII_STR_yyAMD_79c901home },
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{ MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_3C905C, MII_STR_xxBROADCOM_3C905C },
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{ MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5201, MII_STR_xxBROADCOM_BCM5201 },
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{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, MII_STR_BROADCOM_BCM5400 },
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{ MII_OUI_xxDAVICOM, MII_MODEL_xxDAVICOM_DM9101, MII_STR_xxDAVICOM_DM9101 },
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{ MII_OUI_xxDEC, MII_MODEL_xxDEC_xxDC, MII_STR_xxDEC_xxDC },
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{ MII_OUI_xxICS, MII_MODEL_xxICS_1890, MII_STR_xxICS_1890 },
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{ MII_OUI_ICS, MII_MODEL_ICS_1890, MII_STR_ICS_1890 },
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{ MII_OUI_xxINTEL, MII_MODEL_xxINTEL_I82553, MII_STR_xxINTEL_I82553 },
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{ MII_OUI_INTEL, MII_MODEL_INTEL_I82555, MII_STR_INTEL_I82555 },
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{ MII_OUI_INTEL, MII_MODEL_INTEL_I82553, MII_STR_INTEL_I82553 },
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{ MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82555, MII_STR_yyINTEL_I82555 },
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{ MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82553, MII_STR_yyINTEL_I82553 },
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{ MII_OUI_xxLEVEL1, MII_MODEL_xxLEVEL1_LXT970, MII_STR_xxLEVEL1_LXT970 },
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{ MII_OUI_MYSON, MII_MODEL_MYSON_MTD972, MII_STR_MYSON_MTD972 },
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{ MII_OUI_NATSEMI, MII_MODEL_NATSEMI_DP83840, MII_STR_NATSEMI_DP83840 },
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{ MII_OUI_NATSEMI, MII_MODEL_NATSEMI_DP83843, MII_STR_NATSEMI_DP83843 },
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{ MII_OUI_QUALSEMI, MII_MODEL_QUALSEMI_QS6612, MII_STR_QUALSEMI_QS6612 },
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{ MII_OUI_xxSEEQ, MII_MODEL_xxSEEQ_80220, MII_STR_xxSEEQ_80220 },
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{ MII_OUI_xxSEEQ, MII_MODEL_xxSEEQ_84220, MII_STR_xxSEEQ_84220 },
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{ MII_OUI_xxSIS, MII_MODEL_xxSIS_900, MII_STR_xxSIS_900 },
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{ MII_OUI_xxTI, MII_MODEL_xxTI_TLAN10T, MII_STR_xxTI_TLAN10T },
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{ MII_OUI_xxTI, MII_MODEL_xxTI_100VGPMI, MII_STR_xxTI_100VGPMI },
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{ MII_OUI_xxTI, MII_MODEL_xxTI_TNETE2101, MII_STR_xxTI_TNETE2101 },
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{ MII_OUI_TSC, MII_MODEL_TSC_78Q2120, MII_STR_TSC_78Q2120 },
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{ MII_OUI_TSC, MII_MODEL_TSC_78Q2121, MII_STR_TSC_78Q2121 },
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{ MII_OUI_XAQTI, MII_MODEL_XAQTI_XMACII, MII_STR_XAQTI_XMACII },
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{ MII_OUI_xxMYSON, MII_MODEL_xxMYSON_MTD972, MII_STR_xxMYSON_MTD972 },
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{ MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83840, MII_STR_xxNATSEMI_DP83840 },
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{ MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83843, MII_STR_xxNATSEMI_DP83843 },
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{ MII_OUI_xxQUALSEMI, MII_MODEL_xxQUALSEMI_QS6612, MII_STR_xxQUALSEMI_QS6612 },
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{ MII_OUI_SEEQ, MII_MODEL_SEEQ_80220, MII_STR_SEEQ_80220 },
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{ MII_OUI_SEEQ, MII_MODEL_SEEQ_84220, MII_STR_SEEQ_84220 },
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{ MII_OUI_SIS, MII_MODEL_SIS_900, MII_STR_SIS_900 },
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{ MII_OUI_TI, MII_MODEL_TI_TLAN10T, MII_STR_TI_TLAN10T },
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{ MII_OUI_TI, MII_MODEL_TI_100VGPMI, MII_STR_TI_100VGPMI },
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{ MII_OUI_TI, MII_MODEL_TI_TNETE2101, MII_STR_TI_TNETE2101 },
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{ MII_OUI_xxTSC, MII_MODEL_xxTSC_78Q2120, MII_STR_xxTSC_78Q2120 },
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{ MII_OUI_xxTSC, MII_MODEL_xxTSC_78Q2121, MII_STR_xxTSC_78Q2121 },
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{ MII_OUI_xxXAQTI, MII_MODEL_xxXAQTI_XMACII, MII_STR_xxXAQTI_XMACII },
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{ 0, 0, NULL }
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};
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