Common m68k changes for idlelwp.
This commit is contained in:
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795d4ea06e
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36e70d8e10
@ -1,4 +1,4 @@
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/* $NetBSD: pmap_motorola.c,v 1.29 2007/04/05 13:17:11 tnn Exp $ */
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/* $NetBSD: pmap_motorola.c,v 1.30 2007/05/18 01:46:40 mhitch Exp $ */
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/*-
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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@ -124,7 +124,7 @@
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*/
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*/
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#include <sys/cdefs.h>
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap_motorola.c,v 1.29 2007/04/05 13:17:11 tnn Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap_motorola.c,v 1.30 2007/05/18 01:46:40 mhitch Exp $");
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#include "opt_compat_hpux.h"
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#include "opt_compat_hpux.h"
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@ -834,7 +834,8 @@ pmap_activate(struct lwp *l)
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PMAP_DPRINTF(PDB_FOLLOW|PDB_SEGTAB,
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PMAP_DPRINTF(PDB_FOLLOW|PDB_SEGTAB,
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("pmap_activate(%p)\n", l));
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("pmap_activate(%p)\n", l));
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PMAP_ACTIVATE(pmap, curlwp == NULL || l->l_proc == curproc);
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PMAP_ACTIVATE(pmap, (curlwp->l_flag & LW_IDLE) != 0 ||
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l->l_proc == curproc);
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}
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}
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/*
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/*
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@ -1,4 +1,4 @@
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/* $NetBSD: switch_subr.s,v 1.15 2007/02/09 21:55:06 ad Exp $ */
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/* $NetBSD: switch_subr.s,v 1.16 2007/05/18 01:46:39 mhitch Exp $ */
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/*
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/*
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* Copyright (c) 2001 The NetBSD Foundation.
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* Copyright (c) 2001 The NetBSD Foundation.
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@ -109,140 +109,22 @@ GLOBAL(curpcb)
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GLOBAL(masterpaddr) | XXXcompatibility (debuggers)
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GLOBAL(masterpaddr) | XXXcompatibility (debuggers)
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.long 0
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.long 0
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ASBSS(nullpcb,SIZEOF_PCB)
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/*
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* void switch_lwp_exit(struct lwp *);
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*
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* At exit of a lwp, do a switch for the last time.
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* Switch to a safe stack and PCB, and select a new lwp to run. The
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* old stack and u-area will be freed by the reaper.
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*
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* MUST BE CALLED AT SPLHIGH!
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*/
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ENTRY(switch_lwp_exit)
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movl %sp@(4),%a0
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/* save state into garbage pcb */
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movl #_ASM_LABEL(nullpcb),_C_LABEL(curpcb)
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lea _ASM_LABEL(tmpstk),%sp | goto a tmp stack
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/* Schedule the vmspace and stack to be freed. */
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movl %a0,%sp@- | exit2(l)
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jbsr _C_LABEL(lwp_exit2)
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lea %sp@(4),%sp | pop args
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/* Acquire sched_lock */
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jbsr _C_LABEL(sched_lock_idle)
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jra _C_LABEL(cpu_switch)
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/*
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/*
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* When no processes are on the runq, Swtch branches to Idle
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* When no processes are on the runq, Swtch branches to Idle
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* to wait for something to come ready.
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* to wait for something to come ready.
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*/
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*/
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ASENTRY_NOPROFILE(Idle)
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ASENTRY_NOPROFILE(cpu_idle)
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/* Release sched_lock */
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jbsr _C_LABEL(sched_unlock_idle)
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stop #PSL_LOWIPL
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stop #PSL_LOWIPL
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GLOBAL(_Idle) /* For sun2/sun3's clock.c ... */
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GLOBAL(_Idle) /* For sun2/sun3's clock.c ... */
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movw #PSL_HIGHIPL,%sr
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rts
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/* Acquire sched_lock */
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jbsr _C_LABEL(sched_lock_idle)
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movl _C_LABEL(sched_whichqs),%d0
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jeq _ASM_LABEL(Idle)
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#if defined(M68010)
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movw #PSL_LOWIPL,%sr
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#endif
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jra Lcpu_switch1
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Lcpu_switch_badsw:
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PANIC("switch")
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/*NOTREACHED*/
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/*
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/*
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* int cpu_switch(struct lwp *l)
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* void cpu_switchto(struct lwp *current, struct lwp *next)
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*
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*
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* NOTE: With the new VM layout we now no longer know if an inactive
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* Switch to the specific next LWP.
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* user's PTEs have been changed (formerly denoted by the SPTECHG p_flag
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* bit). For now, we just always flush the full ATC.
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*/
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*/
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ENTRY(cpu_switch)
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ENTRY(cpu_switchto)
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movl _C_LABEL(curpcb),%a0 | current pcb
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movl %sp@(4),%a1 | fetch `current' lwp
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movw %sr,%a0@(PCB_PS) | save sr before changing ipl
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movl _C_LABEL(curlwp),%sp@- | remember last LWP running
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clrl _C_LABEL(curlwp)
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/*
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* Find the highest-priority queue that isn't empty,
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* then take the first proc from that queue.
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*/
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Lcpu_switch1:
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#if defined(M68010)
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lea _C_LABEL(sched_whichqs),%a0
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movl %a0@,%d0 | Get runqueue bitmap
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jeq _ASM_LABEL(Idle) | Go idle if empty
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1: moveq #31,%d1
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2: lsrl #1,%d0 | Find first bit set (starting at 0)
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dbcs %d1,2b
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eorib #31,%d1
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movw #PSL_HIGHIPL,%sr
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movl %a0@,%d0 | check again
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btstl %d1,%d0
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beqs 1b | Rescan at HIGHIPL process moved
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moveq #1,%d0 | Double check for higher priority
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lsll %d1,%d0 | process which may have sneaked in
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subql #1,%d0 | while we were finding this one
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andl %a0@,%d0
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bnes 1b | Yup. Go scan again
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#else
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movw #PSL_HIGHIPL,%sr
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movl _C_LABEL(sched_whichqs),%d0
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jeq _ASM_LABEL(Idle) | Go idle if empty
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movl %d0,%d1
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negl %d0
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andl %d1,%d0
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bfffo %d0{#0:#32},%d1
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eorib #31,%d1
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#endif
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movl %d1,%d0
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lslb #3,%d1 | convert queue number to index
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addl #_C_LABEL(sched_qs),%d1 | locate queue (q)
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movl %d1,%a1
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movl %a1@(L_FORW),%a0 | l = q->l_forw
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cmpal %d1,%a0 | anyone on queue?
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jeq Lcpu_switch_badsw | no, panic
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#ifdef DIAGNOSTIC
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tstl %a0@(L_WCHAN)
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jne Lcpu_switch_badsw
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cmpl #LSRUN,%a0@(L_STAT)
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jne Lcpu_switch_badsw
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#endif
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movl %a0@(L_FORW),%a1@(L_FORW) | q->l_forw = l->l_forw
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movl %a0@(L_FORW),%a1 | n = l->l_forw
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movl %d1,%a1@(L_BACK) | n->l_back = q
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cmpal %d1,%a1 | anyone left on queue?
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jne Lcpu_switch_sw2 | yes, skip
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movl _C_LABEL(sched_whichqs),%d1
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bclr %d0,%d1 | no, clear bit
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movl %d1,_C_LABEL(sched_whichqs)
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Lcpu_switch_sw2:
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movl %sp@+,%a1 | Restore saved `curlwp'
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Lcpu_switch_common:
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/* l->l_cpu initialized in fork1() for single-processor */
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movl #LSONPROC,%a0@(L_STAT) | l->l_stat = LSONPROC
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clrl %a0@(L_BACK)
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movl %a0,_C_LABEL(curlwp)
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clrl _C_LABEL(want_resched)
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#if 0
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cmpal %a0,%a1 | switching to same lwp?
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jeq Lcpu_switch_same | yes, skip save and restore
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#else
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movl _C_LABEL(curpcb),%a1
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#endif
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#ifdef M68010
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#ifdef M68010
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movl %a1,%d0
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movl %a1,%d0
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tstl %d0
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tstl %d0
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/*
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/*
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* Save state of previous process in its pcb.
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* Save state of previous process in its pcb.
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*/
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*/
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#if 0
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movl %a1@(L_ADDR),%a1
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movl %a1@(L_ADDR),%a1
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#endif
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moveml %d2-%d7/%a2-%a7,%a1@(PCB_REGS) | save non-scratch registers
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moveml %d2-%d7/%a2-%a7,%a1@(PCB_REGS) | save non-scratch registers
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movl %usp,%a2 | grab USP (a2 has been saved)
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movl %usp,%a2 | grab USP (a2 has been saved)
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movl %a2,%a1@(PCB_USP) | and save it
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movl %a2,%a1@(PCB_USP) | and save it
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#endif /* !_M68K_CUSTOM_FPU_CTX */
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#endif /* !_M68K_CUSTOM_FPU_CTX */
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Lcpu_switch_noctxsave:
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Lcpu_switch_noctxsave:
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clrl %a0@(L_BACK) | clear back link
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movl 8(%sp),%a0
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movl %a0,_C_LABEL(curlwp)
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movl %a0@(L_ADDR),%a1 | get l_addr
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movl %a0@(L_ADDR),%a1 | get l_addr
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movl %a1,_C_LABEL(curpcb)
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movl %a1,_C_LABEL(curpcb)
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/*
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* Done mucking with the run queues, release the
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* scheduler lock, but keep interrupts out.
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*/
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movl %a0,%sp@- | not args...
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movl %a1,%sp@- | ...just saving
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jbsr _C_LABEL(sched_unlock_idle)
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movl %sp@+,%a1
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movl %sp@+,%a0
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#if defined(sun2) || defined(sun3)
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#if defined(sun2) || defined(sun3)
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movl %a0@(L_PROC),%a2
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movl %a0@(L_PROC),%a2
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movl %a2@(P_VMSPACE),%a2 | vm = p->p_vmspace
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movl %a2@(P_VMSPACE),%a2 | vm = p->p_vmspace
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#endif /* !_M68K_CUSTOM_FPU_CTX */
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#endif /* !_M68K_CUSTOM_FPU_CTX */
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Lcpu_switch_nofprest:
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Lcpu_switch_nofprest:
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subl %d1,%d0
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movl %d1,%d0
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beqs 1f
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movl %d0,%a0
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moveq #1,%d0
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1: movw %a1@(PCB_PS),%sr | no, restore PS
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rts
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rts
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/* Switching to the same LWP */
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Lcpu_switch_badsw:
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Lcpu_switch_same:
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PANIC("switch")
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movl %sp@(4),%d0
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/*NOTREACHED*/
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movl %a1,%d0
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movl %a1@(L_ADDR),%a1 | restore l_addr
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bras Lcpu_switch_nofprest
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/*
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* void cpu_switchto(struct lwp *current, struct lwp *next)
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*
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* Switch to the specific next LWP.
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*/
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ENTRY(cpu_switchto)
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movl %sp@(4),%a1 | fetch `current' lwp
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movl %a1@(L_ADDR),%a0
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movw %sr,%a0@(PCB_PS) | save sr before changing ipl
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clrl _C_LABEL(curlwp)
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movl %sp@(8),%a0 | fetch `next' lwp
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jbra Lcpu_switch_common
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/*
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/*
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* savectx(pcb)
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* savectx(pcb)
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@ -1,4 +1,4 @@
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/* $NetBSD: vm_machdep.c,v 1.20 2007/03/04 06:00:06 christos Exp $ */
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/* $NetBSD: vm_machdep.c,v 1.21 2007/05/18 01:46:40 mhitch Exp $ */
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/*
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/*
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* Copyright (c) 1982, 1986, 1990, 1993
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* Copyright (c) 1982, 1986, 1990, 1993
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@ -77,7 +77,7 @@
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*/
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*/
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#include <sys/cdefs.h>
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.20 2007/03/04 06:00:06 christos Exp $");
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__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.21 2007/05/18 01:46:40 mhitch Exp $");
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#include "opt_coredump.h"
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#include "opt_coredump.h"
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@ -194,21 +194,6 @@ cpu_lwp_free2(struct lwp *l)
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/* Nothing to do */
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/* Nothing to do */
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}
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}
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/*
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* cpu_exit is called as the last action during exit.
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*
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* Block context switches and then call switch_exit() which will
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* switch to another process thus we never return.
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*/
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void
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cpu_exit(struct lwp *l)
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{
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(void) splhigh();
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switch_lwp_exit(l);
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/* NOTREACHED */
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}
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#ifdef COREDUMP
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#ifdef COREDUMP
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/*
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/*
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* Dump the machine specific header information at the start of a core dump.
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* Dump the machine specific header information at the start of a core dump.
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