sun4 memory error register code
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deraadt
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03ef730e53
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360eda8453
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@ -42,7 +42,7 @@
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* @(#)locore.s 8.4 (Berkeley) 12/10/93
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*
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* from: Header: locore.s,v 1.51 93/04/21 06:19:37 torek Exp
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* $Id: locore.s,v 1.18 1994/09/20 07:48:24 deraadt Exp $
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* $Id: locore.s,v 1.19 1994/09/25 20:51:51 deraadt Exp $
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*/
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#define LOCORE
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@ -1068,12 +1068,78 @@ ctw_invalid:
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*/
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memfault:
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TRAP_SETUP(-CCFSZ-80)
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INCR(_cnt+V_FAULTS) ! cnt.v_faults++ (clobbers %o0,%o1)
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st %g1, [%sp + CCFSZ + 20] ! save g1
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rd %y, %l4 ! save y
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#if defined(SUN4) && (defined(SUN4C) || defined(SUN4M))
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sethi %hi(_cputyp), %o0 ! what cpu are we running on?
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ld [%o0 + %lo(_cputyp)], %o0
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cmp %o0, CPU_SUN4
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bne 9f
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nop
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#endif
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#if defined(SUN4)
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/*
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* registers:
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* memerr.ctrl = memory error control reg., error if 0x80 set
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* memerr.vaddr = address of memory error
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* buserr = basically just like sun4c sync error reg but
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* no SER_WRITE bit (have to figure out from code).
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*/
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set _par_err_reg, %o0 ! memerr ctrl addr -- XXX mapped?
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ld [%o0], %o0 ! get it
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std %g2, [%sp + CCFSZ + 24] ! save g2, g3
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ld [%o0], %o1 ! memerr ctrl register
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inc 4, %o0 ! now VA of memerr vaddr register
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std %g4, [%sp + CCFSZ + 32] ! (sneak g4,g5 in here)
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ld [%o0], %o2 ! memerr virt addr
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st %g0, [%o0] ! NOTE: this clears latching!!!
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btst ME_REG_IERR, %o1 ! memory error?
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! XXX this value may not be correct
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! as I got some parity errors and the
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! correct bits were not on?
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std %g6, [%sp + CCFSZ + 40]
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bz,a xnormal_mem_fault ! no, just a regular fault
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wr %l0, PSR_ET, %psr ! (and reenable traps)
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/* memory error = death for now XXX */
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clr %o3
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clr %o4
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call _memerr ! (0, ser, sva, 0, 0)
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clr %o0
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call _callrom
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nop
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xnormal_mem_fault:
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/*
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* have to make SUN4 emulate SUN4C. 4C code expects
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* SER in %o1 and the offending VA in %o2, everything else is ok.
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* (must figure out if SER_WRITE should be set)
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*/
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set AC_BUS_ERR, %o0 ! bus error register
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cmp %l3, T_TEXTFAULT ! text fault always on PC
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beq normal_mem_fault ! go
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lduba [%o0]ASI_CONTROL, %o1 ! get its value
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#define STORE_BIT 21 /* bit that indicates a store instruction for sparc */
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ld [%l1], %o3 ! offending instruction in %o3 [l1=pc]
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srl %o3, STORE_BIT, %o3 ! get load/store bit (wont fit simm13)
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btst 1, %o3 ! test for store operation
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bz normal_mem_fault ! if (z) is a load (so branch)
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sethi %hi(SER_WRITE), %o5 ! damn SER_WRITE wont fit simm13
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! or %lo(SER_WRITE), %o5, %o5! not necessary since %lo is zero
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or %o5, %o1, %o1 ! set SER_WRITE
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#if defined(SUN4C) || defined(SUN4M)
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ba normal_mem_fault
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nop ! XXX make efficient later
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#endif /* SUN4C || SUN4M */
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#endif /* SUN4 */
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9:
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#if defined(SUN4C) || defined(SUN4M)
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#if AC_SYNC_ERR + 4 != AC_SYNC_VA || \
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AC_SYNC_ERR + 8 != AC_ASYNC_ERR || AC_SYNC_ERR + 12 != AC_ASYNC_VA
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help help help ! I, I, I wanna be a lifeguard
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@ -1152,6 +1218,7 @@ memfault:
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b return_from_trap
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wr %l0, 0, %psr
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/* NOTREACHED */
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#endif /* SUN4C || SUN4M */
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normal_mem_fault:
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/*
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@ -1702,6 +1769,25 @@ nmi:
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rd %y, %l4 ! save y
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! must read the sync error register too.
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#if defined(SUN4) && (defined(SUN4C) || defined(SUN4M))
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sethi %hi(_cputyp), %o0 ! what cpu are we running on?
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ld [%o0 + %lo(_cputyp)], %o0
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cmp %o0, CPU_SUN4
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bne 1f
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nop
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#endif
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#if defined(SUN4)
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std %g4, [%sp + CCFSZ + 8] ! save g4, g5
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mov %g1, %l5 ! save g1, g6, g7
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mov %g6, %l6
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mov %g7, %l7
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#if defined(SUN4C) || defined(SUN4M)
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b 2f
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nop
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#endif /* SUN4C || SUN4M */
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#endif /* SUN4 */
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1:
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#if defined(SUN4C) || defined(SUN4M)
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set AC_SYNC_ERR, %o0
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lda [%o0] ASI_CONTROL, %o1 ! sync err reg
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inc 4, %o0
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@ -1714,7 +1800,8 @@ nmi:
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lda [%o0] ASI_CONTROL, %o3 ! async err reg
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inc 4, %o0
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lda [%o0] ASI_CONTROL, %o4 ! async virt addr
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#endif /* SUN4C || SUN4M */
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2:
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! and call C code
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call _memerr ! memerr(0, ser, sva, aer, ava)
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clr %o0
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