Many changes and updates from Dave Leonard (d@fnarg.net.au) and
Brad Parker (brad@fcr.com). I've been sitting on these for a while. Notes from Dave: redocumented z8530 stuff. Added break ioctls and detection. Pass framing/parity errors to line discipline. Added TIOC[SG]FLAG. Attempt at bringing all chip ops together. deepended s/w fifos to match chip's.
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briggs
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@ -1,9 +1,9 @@
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/* $NetBSD: serreg.h,v 1.5 1994/10/26 08:46:21 cgd Exp $ */
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/* $NetBSD: serreg.h,v 1.6 1995/02/11 19:06:59 briggs Exp $ */
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/*
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* Copyright (C) 1993 Allen K. Briggs, Chris P. Caputo,
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* Michael L. Finch, Bradley A. Grantham, and
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* Lawrence A. Kesteloot
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* Copyright (C) 1993 Allen K. Briggs, Chris P. Caputo,
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* Michael L. Finch, Bradley A. Grantham, and
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* Lawrence A. Kesteloot
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -16,7 +16,7 @@
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the Alice Group.
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* This product includes software developed by the Alice Group.
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* 4. The names of the Alice Group or any of its members may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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@ -32,77 +32,220 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Mac II serial device interface
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*
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* Information used in this source was gleaned from low-memory
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* global variables in MacOS and the Advanced Micro Devices
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* 1992 Data Book/Handbook.
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* Mac II serial device interface
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*
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* Information used in this source was gleaned from low-memory
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* global variables in MacOS and the Advanced Micro Devices
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* 1992 Data Book/Handbook.
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*/
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/* Gleaned from MacOS */
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extern volatile unsigned char *sccA;
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extern volatile unsigned char *sccA;
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#define SER_W0_RSTESINTS 0x10 /* Reset ext/status interrupts */
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#define SER_W0_ENBRXRDY 0x20 /* Enable interrupt on next receive */
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#define SER_W0_RSTTXPND 0x28 /* Reset transmit interrupt pending */
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#define SER_W0_RSTERR 0x30 /* Reset error */
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#define SER_W0_RSTIUS 0x38 /* Reset highest interrupt pending */
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#define SER_W0_RSTTXUNDERRUN 0xc0 /* Reset transmit underrun/EOM latch */
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/*
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* Following information taken from Zilog's SCC User manal(1992) and the
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* Zilog up and Peripherals databook (vol1/1992)
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*
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* Interrupt Source Priority:
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* channel A rx -highest
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* channel A tx
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* channel A ext/status
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* channel B rx
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* channel B tx
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* channel B ext/status -lowest
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*
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*/
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#define SER_W1_ENBEXTINT 0x01 /* Enable external int */
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#define SER_W1_ENBTXINT 0x02 /* Enable transmit ready interrupt */
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#define SER_W1_ENBR1INT 0x08 /* Rx Int on first char/special cond */
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#define SER_W1_ENBRXINT 0x10 /* Rx Int on all chars/special cond */
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/*
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* Write register 0 (Command Register)
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*/
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#define SER_W0_RSTESINTS 0x10 /* Reset ext/status interrupts */
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/* after an ext/status interrupt the
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* status bits are latched into RR0
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* This re-enables the bits and allows
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* further interrupts due to ext/status
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* change
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*/
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#define SER_W0_ENBRXRDY 0x20 /* Enable interrupt on next receive */
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/* if using interrupt on 1st rx'd char
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* then this is used to reactivate
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* ints on rx after youve read the rx
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* fifo, otherwise you get another int
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* straight away if there's another
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* rx char in the fifo
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*/
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#define SER_W0_RSTTXPND 0x28 /* Reset transmit interrupt pending */
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/* used when there are no more chars
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* to be sent. used to stop the tx'er
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* from int'ing when the tx buffer
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* becomes empty (with tx ints enabl'd)
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*/
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#define SER_W0_RSTERR 0x30 /* Reset error */
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/* resets error bits in RR1. the datum
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* assoc'd with the error is held in
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* rx fifo and is lost after this cmd
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*/
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#define SER_W0_RSTIUS 0x38 /* Reset highest interrupt pending */
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/* used as the last cmd in an interrupt
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* service: lets lower priority
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* interrupts to request service
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*/
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#define SER_W0_RSTTXUNDERRUN 0xc0 /* Reset transmit underrun/EOM latch */
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/* when TX underrun/eom latch has been
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* reset, the scc sends an abort and
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* flag on underrun. this command resets
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* that latch.
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*/
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/*
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* Write register 1 (tx/rx interrupt and data transfer mode definition)
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*/
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#define SER_W3_ENBRX 0x01 /* Enable reception */
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#define SER_W3_RX5DBITS 0x00 /* Receive 5 data bits */
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#define SER_W3_RX6DBITS 0x80 /* Receive 6 data bits */
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#define SER_W3_RX7DBITS 0x40 /* Receive 7 data bits */
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#define SER_W3_RX8DBITS 0xC0 /* Receive 8 data bits */
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#define SER_W1_ENBEXTINT 0x01 /* Enable external int */
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#define SER_W1_ENBTXINT 0x02 /* Enable transmit ready interrupt */
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#define SER_W1_PARISSPEC 0x04 /* parity err is a special cond */
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#define SER_W1_ENBR1INT 0x08 /* Rx Int on first char/special cond */
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#define SER_W1_ENBRXINT 0x10 /* Rx Int on all chars/special cond */
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#define SER_W4_PARNONE 0x00 /* No parity */
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#define SER_W4_PARODD 0x01 /* Odd parity */
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#define SER_W4_PAREVEN 0x03 /* Even parity */
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#define SER_W4_1SBIT 0x04 /* 1 stop bit */
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#define SER_W4_2SBIT 0x0c /* 2 stop bits */
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/*
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* Write register 2 (interrupt vector) - see WR9
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*/
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#define SER_W5_RTS 0x02 /* RTS enable */
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#define SER_W5_ENBTX 0x08 /* Enable transmission */
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#define SER_W5_BREAK 0x10 /* Send break */
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#define SER_W5_TX5DBITS 0x00 /* Send 5 data bits */
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#define SER_W5_TX6DBITS 0x40 /* Send 6 data bits */
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#define SER_W5_TX7DBITS 0x20 /* Send 7 data bits */
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#define SER_W5_TX8DBITS 0x60 /* Send 8 data bits */
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#define SER_W5_DTR 0x80 /* DTR enable */
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/*
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* Write register 3 (rx parameters and Control)
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* can read from RR9 with extended read option on (for eSCC)
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*/
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#define SER_W9_HWRESET 0xC0 /* Force Hardware Reset */
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#define SER_W9_NV 0x02 /* There is no interrupt vector */
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#define SER_W9_DLC 0x04 /* Disable lower interrupt chain */
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#define SER_W9_MIE 0x08 /* Enable master interrupt */
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#define SER_W3_ENBRX 0x01 /* rx enable */
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#define SER_W3_AUTOEN 0x20 /* auto enable */
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/* causes CTS to become the tx
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* enable and DCD to become the rx
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* enable.
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*/
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#define SER_W3_RX5DBITS 0x00 /* Receive 5 data bits */
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#define SER_W3_RX6DBITS 0x80 /* Receive 6 data bits */
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#define SER_W3_RX7DBITS 0x40 /* Receive 7 data bits */
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#define SER_W3_RX8DBITS 0xC0 /* Receive 8 data bits */
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#define SER_W10_NRZ 0x00 /* Set NRZ encoding */
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#define SER_W11_TXBR 0x80 /* Transmit clock is BR generator */
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#define SER_W11_RXBR 0x40 /* Receive clock is BR generator */
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#define SER_W14_ENBBR 0x01 /* Enable BR generator */
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#define SER_W15_ABRTINT 0x80 /* Abort pending interrups */
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/*
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* Write Register 4 (tx/rx misc param and modes)
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*/
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#define SER_R0_RXREADY 0x01 /* Received character available */
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#define SER_R0_TXREADY 0x04 /* Ready to transmit character */
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#define SER_R0_DCD 0x08 /* Carrier detect */
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#define SER_R0_CTS 0x20 /* Clear to send */
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#define SER_R0_TXUNDERRUN 0x40 /* Tx Underrun/EOM */
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#define SER_W4_PARNONE 0x00 /* No parity */
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#define SER_W4_PARODD 0x01 /* Odd parity */
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#define SER_W4_PAREVEN 0x03 /* Even parity */
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#define SER_W4_1SBIT 0x04 /* 1 stop bit */
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#define SER_W4_2SBIT 0x0c /* 2 stop bits */
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#define SER_W4_CLKX1 0x00 /* clock rate = data rate */
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#define SER_W4_CLKX16 0x40 /* clock rate = 16 * data rate */
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#define SER_W4_CLKX32 0x80 /* clock rate = 32 * data rate */
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#define SER_W4_CLKX64 0xc0 /* clock rate = 64 * data rate */
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#define SER_R1_RXOVERRUN 0x20
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#define SER_R1_PARITYERR 0x10
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#define SER_R1_CRCERR 0x40
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#define SER_R1_ENDOFFRAME 0x80
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/*
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* Write Register 5 (Tx params and control)
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*/
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#define SERBRD(x) (mac68k_machine.sccClkConst / (x) - 2)
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#define SCCCNTL(unit) (sccA[2 - ((unit) << 1)])
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#define SCCRDWR(unit) (sccA[6 - ((unit) << 1)])
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#define SER_W5_RTS 0x02 /* RTS enable */
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#define SER_W5_ENBTX 0x08 /* Enable transmission */
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#define SER_W5_BREAK 0x10 /* Send break */
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#define SER_W5_TX5DBITS 0x00 /* Send 5 data bits */
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#define SER_W5_TX6DBITS 0x40 /* Send 6 data bits */
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#define SER_W5_TX7DBITS 0x20 /* Send 7 data bits */
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#define SER_W5_TX8DBITS 0x60 /* Send 8 data bits */
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#define SER_W5_DTR 0x80 /* DTR enable */
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#define SER_DOCNTL(unit, reg, val) \
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{SCCCNTL(unit) = (reg); SCCCNTL(unit) = (val);}
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#define SER_STATUS(unit, reg) \
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(SCCCNTL(unit) = (reg), SCCCNTL(unit))
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/*
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* Write register 8 (Transmit buffer)
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*/
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/*
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* Write Register 9 (Master interrupt control)
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*/
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#define SER_W9_ARESET 0x80 /* reset channel A */
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#define SER_W9_BRESET 0x40 /* reset channel A */
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#define SER_W9_HWRESET ( SER_W9_ARESET | SER_W9_BRESET ) /* both */
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#define SER_W9_NV 0x02 /* There is no interrupt vector */
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#define SER_W9_DLC 0x04 /* Disable lower interrupt chain */
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#define SER_W9_MIE 0x08 /* Enable master interrupt */
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/* (MIE is cleared on a HWRESET) */
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/* Write Register 10 (Misc tx/rx control bits */
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#define SER_W10_NRZ 0x00 /* Set NRZ encoding */
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#define SER_W10_URFLG 0x04 /* abort/flag on underrun (sdlc only) */
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/* Write Register 11 (Clock mode control) */
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#define SER_W11_TXBR 0x10 /* Transmit clock is BR generator */
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#define SER_W11_RXBR 0x40 /* Receive clock is BR generator */
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/* Write Register 12 (Lower byte of baud constant)
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* Write Register 13 (Upper byte of baud constant)
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* Write Register 14 (Misc control of baud)
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*
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* The baud constant is computed by:
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*
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* Baud constant = ( clock_freq / ( 2* desired_rate * BR_clk_period )) - 2
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*/
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#define SERBRD(x) (mac68k_machine.sccClkConst / (x) -2 )
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#define SER_W14_ENBBR 0x01 /* Enable BR generator */
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/*
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* Write Register 15 (Ext/ststus interrupt control)
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*/
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#define SER_W15_DCDINT 0x08 /* enable DCD interrupts */
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#define SER_W15_CTSINT 0x20 /* enable CTS interrupts */
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#define SER_W15_BRKINT 0x80 /* Abort pending interrups */
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/*
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* Read Register 0 (tx/rx buffer status & ext status)
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*/
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#define SER_R0_RXREADY 0x01 /* Received character available */
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#define SER_R0_TXREADY 0x04 /* Ready to transmit character */
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#define SER_R0_DCD 0x08 /* Carrier detect */
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#define SER_R0_CTS 0x20 /* Clear to send */
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#define SER_R0_TXUNDERRUN 0x40 /* Tx Underrun/EOM */
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#define SER_R0_BREAK 0x80 /* Break/abort */
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#define SER_R1_RXOVERRUN 0x20
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#define SER_R1_PARITYERR 0x10
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#define SER_R1_CRCERR 0x40
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#define SER_R1_ENDOFFRAME 0x80
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/*
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* Read Register 2
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* channel A: is contents of WR2
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* channel B: is status of an interrupt (low here if WR9 appropriate)
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*/
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#define SER_R2_MASK 0x06 /* what kind of int was it */
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#define SER_R2_TX 0x00 /* tx buffer empty */
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#define SER_R2_EXTCHG 0x02 /* external/status change */
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#define SER_R2_RX 0x04 /* rx char avail */
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#define SER_R2_SPEC 0x06 /* special recv condition */
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#define SER_R2_CHANMASK 0x08 /* which channell caused int */
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#define SER_R2_CHANA 0x08
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#define SER_R2_CHANB 0x00
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/* only from channel A */
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#define SER_R3_BIPES 0x01 /* chanB ext/stat interrupt pending */
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#define SER_R3_BIPTX 0x02 /* chanB tx ip */
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#define SER_R3_BIPRX 0x04 /* chanB rx ip */
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#define SER_R3_AIPES 0x08 /* chanA ext/stat interrupt pending */
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#define SER_R3_AIPTX 0x10 /* chanA tx ip */
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#define SER_R3_AIPRX 0x20 /* chanA rx ip */
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#define SCCCNTL(unit) (sccA[2 - ((unit) << 1)])
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#define SCCRDWR(unit) (sccA[6 - ((unit) << 1)])
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#define SER_DOCNTL(unit, reg, val) \
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SCCCNTL(unit) = (reg), SCCCNTL(unit) = (val)
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#define SER_STATUS(unit, reg) \
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(SCCCNTL(unit) = (reg), SCCCNTL(unit))
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