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Use CPU_MIPS_USE_WAIT and CPU_MIPS_NO_WAIT in the CPU table, and use 

the generic name "mips_wait_idle" for the old function that had both
rm52xx_idle and mipsNN_idle entry points.
This commit is contained in:
simonb 2002-06-01 13:45:45 +00:00
parent 3611959ac8
commit 341ed8c0d3
3 changed files with 21 additions and 53 deletions
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11
sys/arch/mips/include/locore.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.h,v 1.61 2002/05/13 04:15:40 simonb Exp $ */
/* $NetBSD: locore.h,v 1.62 2002/06/01 13:45:45 simonb Exp $ */
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
@ -33,11 +33,6 @@
struct tlb;
/*
* locore service routine for exception vectors. Used outside locore
* only to print them by name in stack tracebacks
*/
uint32_t mips_cp0_cause_read(void);
void mips_cp0_cause_write(uint32_t);
uint32_t mips_cp0_status_read(void);
@ -198,12 +193,10 @@ typedef struct {
void (*wbflush)(void);
} mips_locore_jumpvec_t;
/* Override writebuffer-drain method. */
void mips_set_wbflush(void (*)(void));
void mips_wait_idle(void);
/* stacktrace() -- print a stack backtrace to the console */
void stacktrace(void);
/* logstacktrace() -- log a stack traceback to msgbuf */
void logstacktrace(void);
/*

13
sys/arch/mips/mips/locore_mips3.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore_mips3.S,v 1.78 2002/06/01 13:16:44 simonb Exp $ */
/* $NetBSD: locore_mips3.S,v 1.79 2002/06/01 13:45:45 simonb Exp $ */
/*
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@ -163,7 +163,7 @@ END(mips3_wbflush)
/* XXX simonb: ugg, another ugly #ifdef check... */
#if (defined(MIPS3) && !defined(MIPS3_5900)) || defined(MIPS32) || defined(MIPS64)
/*
* rm52xx_idle:
* mips_wait_idle:
*
* When no processes are on the runq, cpu_switch branches to
* idle to wait for something to come ready.
@ -172,10 +172,9 @@ END(mips3_wbflush)
* for kernel profiling.
*
* This version takes advantage of power-saving features on
* the QED RM52xx family of CPUs.
* the QED RM52xx family of CPUs, and MIPS32 & MIPS64 CPUs.
*/
LEAF(rm52xx_idle)
XLEAF(mipsNN_idle)
LEAF(mips_wait_idle)
li t0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
DYNAMIC_STATUS_MASK(t0,t1) # machine dependent masking
mtc0 t0, MIPS_COP_0_STATUS # enable all interrupts
@ -235,8 +234,8 @@ XLEAF(mipsNN_idle)
j ra
nop
#endif
END(rm52xx_idle)
#endif /* MIPS3 && !MIPS3_5900 */
END(mips_wait_idle)
#endif /* (MIPS3 && !MIPS3_5900) || MIPS32 || MIPS64 */
/*

50
sys/arch/mips/mips/mips_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mips_machdep.c,v 1.130 2002/06/01 12:27:04 simonb Exp $ */
/* $NetBSD: mips_machdep.c,v 1.131 2002/06/01 13:45:46 simonb Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -120,7 +120,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.130 2002/06/01 12:27:04 simonb Exp $");
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.131 2002/06/01 13:45:46 simonb Exp $");
#include "opt_cputype.h"
#include "opt_compat_netbsd.h"
@ -231,7 +231,7 @@ struct pridtab {
* - All MIPS3+ have a count register. MIPS_HAS_CLOCK in <mips/cpu.h>
* will need to be revised if this is false.
*/
#define MIPS32_FLAGS CPU_MIPS_R4K_MMU | CPU_MIPS_CAUSE_IV
#define MIPS32_FLAGS CPU_MIPS_R4K_MMU | CPU_MIPS_CAUSE_IV | CPU_MIPS_USE_WAIT
#define MIPS64_FLAGS MIPS32_FLAGS /* same as MIPS32 flags (for now) */
static const struct pridtab *mycpu;
@ -313,8 +313,8 @@ static const struct pridtab cputab[] = {
CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
"MIPS R5000 CPU" },
{ 0, MIPS_RM5200, -1, CPU_ARCH_MIPS4, 48,
CPU_MIPS_R4K_MMU | CPU_MIPS_CAUSE_IV | CPU_MIPS_DOUBLE_COUNT,
"QED RM5200 CPU" },
CPU_MIPS_R4K_MMU | CPU_MIPS_CAUSE_IV | CPU_MIPS_DOUBLE_COUNT |
CPU_MIPS_USE_WAIT, "QED RM5200 CPU" },
/* XXX
* The rm7000 rev 2.0 can have 64 tlbs, and has 6 extra interrupts. See
@ -322,8 +322,8 @@ static const struct pridtab cputab[] = {
* for more details.
*/
{ 0, MIPS_RM7000, -1, CPU_ARCH_MIPS4, 48,
MIPS_NOT_SUPP | CPU_MIPS_CAUSE_IV | CPU_MIPS_DOUBLE_COUNT,
"QED RM7000 CPU" },
MIPS_NOT_SUPP | CPU_MIPS_CAUSE_IV | CPU_MIPS_DOUBLE_COUNT |
CPU_MIPS_USE_WAIT, "QED RM7000 CPU" },
/*
* IDT RC32300 core is a 32 bit MIPS2 processor with
@ -364,9 +364,9 @@ static const struct pridtab cputab[] = {
MIPS64_FLAGS | CPU_MIPS_DOUBLE_COUNT, "5Kc" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU1000_R1, -1, -1, 0,
MIPS32_FLAGS, "Au1000 (Rev 1)" },
MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1000 (Rev 1)" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU1000_R2, -1, -1, 0,
MIPS32_FLAGS, "Au1000 (Rev 2)" },
MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1000 (Rev 2)" },
/* The SB1 CPUs use a CCA of 5 - "Cacheable Coherent Shareable" */
{ MIPS_PRID_CID_SIBYTE, MIPS_SB1, -1, -1, 0,
@ -880,35 +880,11 @@ mips_vector_init(void)
/*
* Install power-saving idle routines.
*/
switch (MIPS_PRID_CID(cpu_id)) {
case MIPS_PRID_CID_PREHISTORIC:
switch (MIPS_PRID_IMPL(cpu_id)) {
#if defined(MIPS3) && !defined(MIPS3_5900)
case MIPS_RM5200:
case MIPS_RM7000:
{
void rm52xx_idle(void);
if ((mips_cpu_flags & CPU_MIPS_USE_WAIT) &&
!(mips_cpu_flags & CPU_MIPS_NO_WAIT)) {
void mips_wait_idle(void); /* XXX prototype */
CPU_IDLE = (long *) rm52xx_idle;
break;
}
#endif /* MIPS3 && !MIPS3_5900 */
default:
/* Nothing. */
break;
}
#if defined(MIPS32) || defined(MIPS64)
default:
{
/*
* XXX: wait is valid on all mips32/64, but do we
* always want to use it?
*/
void mipsNN_idle(void);
CPU_IDLE = (long *) mipsNN_idle;
}
#endif
CPU_IDLE = (long *)mips_wait_idle;
}
}