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This commit is contained in:
christos 2016-04-26 21:17:20 +00:00
parent cba709e375
commit 33f25f9fb6
3 changed files with 4586 additions and 51 deletions
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3810
sys/dev/ic/rt2860.c Normal file
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616
sys/dev/ic/rt2860reg.h
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@ -1,5 +1,4 @@
/* $NetBSD: rt2860reg.h,v 1.1 2012/05/30 14:30:35 nonaka Exp $ */
/* $OpenBSD: rt2860reg.h,v 1.30 2010/05/10 18:17:10 damien Exp $ */
/* $OpenBSD: rt2860reg.h,v 1.32 2014/05/24 10:10:17 stsp Exp $ */
/*-
* Copyright (c) 2007
@ -81,6 +80,9 @@
#define RT3070_LDO_CFG0 0x05d4
#define RT3070_GPIO_SWITCH 0x05dc
/* RT5592 registers */
#define RT5592_DEBUG_INDEX 0x05e8
/* MAC registers */
#define RT2860_ASIC_VER_ID 0x1000
#define RT2860_MAC_SYS_CTRL 0x1004
@ -205,6 +207,7 @@
#define RT2860_H2M_MAILBOX 0x7010
#define RT2860_H2M_MAILBOX_CID 0x7014
#define RT2860_H2M_MAILBOX_STATUS 0x701c
#define RT2860_H2M_INTSRC 0x7024
#define RT2860_H2M_BBPAGENT 0x7028
#define RT2860_BCN_BASE(vap) (0x7800 + (vap) * 512)
@ -256,10 +259,10 @@
#define RT2860_TX_DMA_EN (1 << 0)
/* possible flags for register DELAY_INT_CFG */
#define RT2860_TXDLY_INT_EN (1 << 31)
#define RT2860_TXDLY_INT_EN (1U << 31)
#define RT2860_TXMAX_PINT_SHIFT 24
#define RT2860_TXMAX_PTIME_SHIFT 16
#define RT2860_RXDLY_INT_EN (1 << 15)
#define RT2860_RXDLY_INT_EN (1U << 15)
#define RT2860_RXMAX_PINT_SHIFT 8
#define RT2860_RXMAX_PTIME_SHIFT 0
@ -268,16 +271,16 @@
#define RT2860_GPIO_O_SHIFT 0
/* possible flags for register USB_DMA_CFG */
#define RT2860_USB_TX_BUSY (1 << 31)
#define RT2860_USB_RX_BUSY (1 << 30)
#define RT2860_USB_TX_BUSY (1U << 31)
#define RT2860_USB_RX_BUSY (1U << 30)
#define RT2860_USB_EPOUT_VLD_SHIFT 24
#define RT2860_USB_TX_EN (1 << 23)
#define RT2860_USB_RX_EN (1 << 22)
#define RT2860_USB_RX_AGG_EN (1 << 21)
#define RT2860_USB_TXOP_HALT (1 << 20)
#define RT2860_USB_TX_CLEAR (1 << 19)
#define RT2860_USB_PHY_WD_EN (1 << 16)
#define RT2860_USB_PHY_MAN_RST (1 << 15)
#define RT2860_USB_TX_EN (1U << 23)
#define RT2860_USB_RX_EN (1U << 22)
#define RT2860_USB_RX_AGG_EN (1U << 21)
#define RT2860_USB_TXOP_HALT (1U << 20)
#define RT2860_USB_TX_CLEAR (1U << 19)
#define RT2860_USB_PHY_WD_EN (1U << 16)
#define RT2860_USB_PHY_MAN_RST (1U << 15)
#define RT2860_USB_RX_AGG_LMT(x) ((x) << 8) /* in unit of 1KB */
#define RT2860_USB_RX_AGG_TO(x) ((x) & 0xff) /* in unit of 33ns */
@ -368,9 +371,9 @@
#define RT2860_TX0Q_PCNT_MASK 0x000000ff
/* possible flags for register CAP_CTRL */
#define RT2860_CAP_ADC_FEQ (1 << 31)
#define RT2860_CAP_START (1 << 30)
#define RT2860_MAN_TRIG (1 << 29)
#define RT2860_CAP_ADC_FEQ (1U << 31)
#define RT2860_CAP_START (1U << 30)
#define RT2860_MAN_TRIG (1U << 29)
#define RT2860_TRIG_OFFSET_SHIFT 16
#define RT2860_START_ADDR_SHIFT 0
@ -379,13 +382,16 @@
#define RT3070_RF_WRITE (1 << 16)
/* possible flags for register EFUSE_CTRL */
#define RT3070_SEL_EFUSE (1 << 31)
#define RT3070_EFSROM_KICK (1 << 30)
#define RT3070_SEL_EFUSE (1U << 31)
#define RT3070_EFSROM_KICK (1U << 30)
#define RT3070_EFSROM_AIN_MASK 0x03ff0000
#define RT3070_EFSROM_AIN_SHIFT 16
#define RT3070_EFSROM_MODE_MASK 0x000000c0
#define RT3070_EFUSE_AOUT_MASK 0x0000003f
/* possible flag for register DEBUG_INDEX */
#define RT5592_SEL_XTAL (1U << 31)
/* possible flags for register MAC_SYS_CTRL */
#define RT2860_RX_TS_EN (1 << 7)
#define RT2860_WLAN_HALT_EN (1 << 6)
@ -418,9 +424,9 @@
#define RT2860_BBP_DATA_SHIFT 0
/* possible flags for register RF_CSR_CFG0 */
#define RT2860_RF_REG_CTRL (1 << 31)
#define RT2860_RF_LE_SEL1 (1 << 30)
#define RT2860_RF_LE_STBY (1 << 29)
#define RT2860_RF_REG_CTRL (1U << 31)
#define RT2860_RF_LE_SEL1 (1U << 30)
#define RT2860_RF_LE_STBY (1U << 29)
#define RT2860_RF_REG_WIDTH_SHIFT 24
#define RT2860_RF_REG_0_SHIFT 0
@ -453,9 +459,9 @@
#define RT2860_SLOT_TIME 0
/* possible flags for register NAV_TIME_CFG */
#define RT2860_NAV_UPD (1 << 31)
#define RT2860_NAV_UPD (1U << 31)
#define RT2860_NAV_UPD_VAL_SHIFT 16
#define RT2860_NAV_CLR_EN (1 << 15)
#define RT2860_NAV_CLR_EN (1U << 15)
#define RT2860_NAV_TIMER_SHIFT 0
/* possible flags for register CH_TIME_CFG */
@ -507,37 +513,37 @@
#define RT2860_WAKEUP_LEAD_TIME_SHIFT 0
/* possible flags for register TX_PIN_CFG */
#define RT3593_LNA_PE_G2_POL (1 << 31)
#define RT3593_LNA_PE_A2_POL (1 << 30)
#define RT3593_LNA_PE_G2_EN (1 << 29)
#define RT3593_LNA_PE_A2_EN (1 << 28)
#define RT3593_LNA_PE_G2_POL (1U << 31)
#define RT3593_LNA_PE_A2_POL (1U << 30)
#define RT3593_LNA_PE_G2_EN (1U << 29)
#define RT3593_LNA_PE_A2_EN (1U << 28)
#define RT3593_LNA_PE2_EN (RT3593_LNA_PE_A2_EN | RT3593_LNA_PE_G2_EN)
#define RT3593_PA_PE_G2_POL (1 << 27)
#define RT3593_PA_PE_A2_POL (1 << 26)
#define RT3593_PA_PE_G2_EN (1 << 25)
#define RT3593_PA_PE_A2_EN (1 << 24)
#define RT2860_TRSW_POL (1 << 19)
#define RT2860_TRSW_EN (1 << 18)
#define RT2860_RFTR_POL (1 << 17)
#define RT2860_RFTR_EN (1 << 16)
#define RT2860_LNA_PE_G1_POL (1 << 15)
#define RT2860_LNA_PE_A1_POL (1 << 14)
#define RT2860_LNA_PE_G0_POL (1 << 13)
#define RT2860_LNA_PE_A0_POL (1 << 12)
#define RT2860_LNA_PE_G1_EN (1 << 11)
#define RT2860_LNA_PE_A1_EN (1 << 10)
#define RT3593_PA_PE_G2_POL (1U << 27)
#define RT3593_PA_PE_A2_POL (1U << 26)
#define RT3593_PA_PE_G2_EN (1U << 25)
#define RT3593_PA_PE_A2_EN (1U << 24)
#define RT2860_TRSW_POL (1U << 19)
#define RT2860_TRSW_EN (1U << 18)
#define RT2860_RFTR_POL (1U << 17)
#define RT2860_RFTR_EN (1U << 16)
#define RT2860_LNA_PE_G1_POL (1U << 15)
#define RT2860_LNA_PE_A1_POL (1U << 14)
#define RT2860_LNA_PE_G0_POL (1U << 13)
#define RT2860_LNA_PE_A0_POL (1U << 12)
#define RT2860_LNA_PE_G1_EN (1U << 11)
#define RT2860_LNA_PE_A1_EN (1U << 10)
#define RT2860_LNA_PE1_EN (RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN)
#define RT2860_LNA_PE_G0_EN (1 << 9)
#define RT2860_LNA_PE_A0_EN (1 << 8)
#define RT2860_LNA_PE_G0_EN (1U << 9)
#define RT2860_LNA_PE_A0_EN (1U << 8)
#define RT2860_LNA_PE0_EN (RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN)
#define RT2860_PA_PE_G1_POL (1 << 7)
#define RT2860_PA_PE_A1_POL (1 << 6)
#define RT2860_PA_PE_G0_POL (1 << 5)
#define RT2860_PA_PE_A0_POL (1 << 4)
#define RT2860_PA_PE_G1_EN (1 << 3)
#define RT2860_PA_PE_A1_EN (1 << 2)
#define RT2860_PA_PE_G0_EN (1 << 1)
#define RT2860_PA_PE_A0_EN (1 << 0)
#define RT2860_PA_PE_G1_POL (1U << 7)
#define RT2860_PA_PE_A1_POL (1U << 6)
#define RT2860_PA_PE_G0_POL (1U << 5)
#define RT2860_PA_PE_A0_POL (1U << 4)
#define RT2860_PA_PE_G1_EN (1U << 3)
#define RT2860_PA_PE_A1_EN (1U << 2)
#define RT2860_PA_PE_G0_EN (1U << 1)
#define RT2860_PA_PE_A0_EN (1U << 0)
/* possible flags for register TX_BAND_CFG */
#define RT2860_5G_BAND_SEL_N (1 << 2)
@ -697,6 +703,7 @@
/* possible flags for RT3020 RF register 1 */
#define RT3070_RF_BLOCK (1 << 0)
#define RT3070_PLL_PD (1 << 1)
#define RT3070_RX0_PD (1 << 2)
#define RT3070_TX0_PD (1 << 3)
#define RT3070_RX1_PD (1 << 4)
@ -735,6 +742,9 @@
/* possible flags for RT3053 RF register 6 */
#define RT3593_VCO_IC (1 << 6)
/* possible flags for RT3053 RF register 18 */
#define RT3593_AUTOTUNE_BYPASS (1 << 6)
/* possible flags for RT3053 RF register 20 */
#define RT3593_LDO_PLL_VC_MASK 0x0e
#define RT3593_LDO_RF_VC_MASK 0xe0
@ -743,9 +753,28 @@
#define RT3593_CP_IC_MASK 0xe0
#define RT3593_CP_IC_SHIFT 5
/* possible flags for RT5390 RF register 38. */
#define RT5390_RX_LO1 (1 << 5)
/* possible flags for RT5390 RF register 39. */
#define RT5390_RX_LO2 (1 << 7)
/* possible flags for RT3053 RF register 46 */
#define RT3593_RX_CTB (1 << 5)
/* possible flags for RT3053 RF register 50 */
#define RT3593_TX_LO2 (1 << 4)
/* possible flags for RT3053 RF register 51 */
#define RT3593_TX_LO1 (1 << 4)
/* Possible flags for RT5390 BBP register 4. */
#define RT5390_MAC_IF_CTRL (1 << 6)
/* possible flags for RT5390 BBP register 105. */
#define RT5390_MLD (1 << 2)
#define RT5390_EN_SIG_MODULATION (1 << 3)
#define RT3090_DEF_LNA 10
/* RT2860 TX descriptor */
@ -892,6 +921,9 @@ struct rt2860_rxwi {
#define RT3070_RF_3052 9 /* dual-band 2T2R */
#define RT3070_RF_3320 11 /* 1T1R */
#define RT3070_RF_3053 13 /* dual-band 3T3R */
#define RT5592_RF_5592 0x000f /* dual-band 2T2R */
#define RT5390_RF_5370 0x5370 /* 1T1R */
#define RT5390_RF_5372 0x5372 /* 2T2R */
/* USB commands for RT2870 only */
#define RT2870_RESET 1
@ -939,6 +971,47 @@ struct rt2860_rxwi {
#define RT2860_EEPROM_BBP_BASE 0x78
#define RT3071_EEPROM_RF_BASE 0x82
/* EEPROM registers for RT3593. */
#define RT3593_EEPROM_FREQ_LEDS 0x21
#define RT3593_EEPROM_FREQ 0x22
#define RT3593_EEPROM_LED1 0x22
#define RT3593_EEPROM_LED2 0x23
#define RT3593_EEPROM_LED3 0x24
#define RT3593_EEPROM_LNA 0x26
#define RT3593_EEPROM_LNA_5GHZ 0x27
#define RT3593_EEPROM_RSSI1_2GHZ 0x28
#define RT3593_EEPROM_RSSI2_2GHZ 0x29
#define RT3593_EEPROM_RSSI1_5GHZ 0x2a
#define RT3593_EEPROM_RSSI2_5GHZ 0x2b
#define RT3593_EEPROM_PWR2GHZ_BASE1 0x30
#define RT3593_EEPROM_PWR2GHZ_BASE2 0x37
#define RT3593_EEPROM_PWR2GHZ_BASE3 0x3e
#define RT3593_EEPROM_PWR5GHZ_BASE1 0x4b
#define RT3593_EEPROM_PWR5GHZ_BASE2 0x65
#define RT3593_EEPROM_PWR5GHZ_BASE3 0x7f
/*
* EEPROM IQ calibration.
*/
#define RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ 0x130
#define RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ 0x131
#define RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ 0x133
#define RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ 0x134
#define RT5390_EEPROM_RF_IQ_COMPENSATION_CTL 0x13c
#define RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL 0x13d
#define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ 0x144
#define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ 0x145
#define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ 0x146
#define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ 0x147
#define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ 0x148
#define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ 0x149
#define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ 0x14a
#define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ 0x14b
#define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ 0x14c
#define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ 0x14d
#define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ 0x14e
#define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ 0x14f
#define RT2860_RIDX_CCK1 0
#define RT2860_RIDX_CCK11 3
#define RT2860_RIDX_OFDM6 4
@ -1085,6 +1158,62 @@ static const struct rt2860_rate {
{ 105, 0x05 }, \
{ 106, 0x35 }
#define RT5390_DEF_BBP \
{ 31, 0x08 }, \
{ 65, 0x2c }, \
{ 66, 0x38 }, \
{ 68, 0x0b }, \
{ 69, 0x0d }, \
{ 70, 0x06 }, \
{ 73, 0x13 }, \
{ 75, 0x46 }, \
{ 76, 0x28 }, \
{ 77, 0x59 }, \
{ 81, 0x37 }, \
{ 82, 0x62 }, \
{ 83, 0x7a }, \
{ 84, 0x9a }, \
{ 86, 0x38 }, \
{ 91, 0x04 }, \
{ 92, 0x02 }, \
{ 103, 0xc0 }, \
{ 104, 0x92 }, \
{ 105, 0x3c }, \
{ 106, 0x03 }, \
{ 128, 0x12 }
#define RT5592_DEF_BBP \
{ 20, 0x06 }, \
{ 31, 0x08 }, \
{ 65, 0x2c }, \
{ 66, 0x38 }, \
{ 68, 0xdd }, \
{ 69, 0x1a }, \
{ 70, 0x05 }, \
{ 73, 0x13 }, \
{ 74, 0x0f }, \
{ 75, 0x4f }, \
{ 76, 0x28 }, \
{ 77, 0x59 }, \
{ 81, 0x37 }, \
{ 82, 0x62 }, \
{ 83, 0x6a }, \
{ 84, 0x9a }, \
{ 86, 0x38 }, \
{ 88, 0x90 }, \
{ 91, 0x04 }, \
{ 92, 0x02 }, \
{ 95, 0x9a }, \
{ 98, 0x12 }, \
{ 103, 0xc0 }, \
{ 104, 0x92 }, \
{ 105, 0x3c }, \
{ 106, 0x35 }, \
{ 128, 0x12 }, \
{ 134, 0xd0 }, \
{ 135, 0xf6 }, \
{ 137, 0x0f }
/*
* Default settings for RF registers; values derived from the reference driver.
*/
@ -1198,6 +1327,116 @@ static const struct rt2860_rate {
{ 0x61, 0, 7 }, \
{ 0x61, 0, 9 }
#define RT5592_RF5592_20MHZ \
{ 0x1e2, 4, 10, 3 }, \
{ 0x1e3, 4, 10, 3 }, \
{ 0x1e4, 4, 10, 3 }, \
{ 0x1e5, 4, 10, 3 }, \
{ 0x1e6, 4, 10, 3 }, \
{ 0x1e7, 4, 10, 3 }, \
{ 0x1e8, 4, 10, 3 }, \
{ 0x1e9, 4, 10, 3 }, \
{ 0x1ea, 4, 10, 3 }, \
{ 0x1eb, 4, 10, 3 }, \
{ 0x1ec, 4, 10, 3 }, \
{ 0x1ed, 4, 10, 3 }, \
{ 0x1ee, 4, 10, 3 }, \
{ 0x1f0, 8, 10, 3 }, \
{ 0xac, 8, 12, 1 }, \
{ 0xad, 0, 12, 1 }, \
{ 0xad, 4, 12, 1 }, \
{ 0xae, 0, 12, 1 }, \
{ 0xae, 4, 12, 1 }, \
{ 0xae, 8, 12, 1 }, \
{ 0xaf, 4, 12, 1 }, \
{ 0xaf, 8, 12, 1 }, \
{ 0xb0, 0, 12, 1 }, \
{ 0xb0, 8, 12, 1 }, \
{ 0xb1, 0, 12, 1 }, \
{ 0xb1, 4, 12, 1 }, \
{ 0xb7, 4, 12, 1 }, \
{ 0xb7, 8, 12, 1 }, \
{ 0xb8, 0, 12, 1 }, \
{ 0xb8, 8, 12, 1 }, \
{ 0xb9, 0, 12, 1 }, \
{ 0xb9, 4, 12, 1 }, \
{ 0xba, 0, 12, 1 }, \
{ 0xba, 4, 12, 1 }, \
{ 0xba, 8, 12, 1 }, \
{ 0xbb, 4, 12, 1 }, \
{ 0xbb, 8, 12, 1 }, \
{ 0xbc, 0, 12, 1 }, \
{ 0xbc, 8, 12, 1 }, \
{ 0xbd, 0, 12, 1 }, \
{ 0xbd, 4, 12, 1 }, \
{ 0xbe, 0, 12, 1 }, \
{ 0xbf, 6, 12, 1 }, \
{ 0xbf, 10, 12, 1 }, \
{ 0xc0, 2, 12, 1 }, \
{ 0xc0, 10, 12, 1 }, \
{ 0xc1, 2, 12, 1 }, \
{ 0xc1, 6, 12, 1 }, \
{ 0xc2, 2, 12, 1 }, \
{ 0xa4, 0, 12, 1 }, \
{ 0xa4, 4, 12, 1 }, \
{ 0xa5, 8, 12, 1 }, \
{ 0xa6, 0, 12, 1 }
#define RT5592_RF5592_40MHZ \
{ 0xf1, 2, 10, 3 }, \
{ 0xf1, 7, 10, 3 }, \
{ 0xf2, 2, 10, 3 }, \
{ 0xf2, 7, 10, 3 }, \
{ 0xf3, 2, 10, 3 }, \
{ 0xf3, 7, 10, 3 }, \
{ 0xf4, 2, 10, 3 }, \
{ 0xf4, 7, 10, 3 }, \
{ 0xf5, 2, 10, 3 }, \
{ 0xf5, 7, 10, 3 }, \
{ 0xf6, 2, 10, 3 }, \
{ 0xf6, 7, 10, 3 }, \
{ 0xf7, 2, 10, 3 }, \
{ 0xf8, 4, 10, 3 }, \
{ 0x56, 4, 12, 1 }, \
{ 0x56, 6, 12, 1 }, \
{ 0x56, 8, 12, 1 }, \
{ 0x57, 0, 12, 1 }, \
{ 0x57, 2, 12, 1 }, \
{ 0x57, 4, 12, 1 }, \
{ 0x57, 8, 12, 1 }, \
{ 0x57, 10, 12, 1 }, \
{ 0x58, 0, 12, 1 }, \
{ 0x58, 4, 12, 1 }, \
{ 0x58, 6, 12, 1 }, \
{ 0x58, 8, 12, 1 }, \
{ 0x5b, 8, 12, 1 }, \
{ 0x5b, 10, 12, 1 }, \
{ 0x5c, 0, 12, 1 }, \
{ 0x5c, 4, 12, 1 }, \
{ 0x5c, 6, 12, 1 }, \
{ 0x5c, 8, 12, 1 }, \
{ 0x5d, 0, 12, 1 }, \
{ 0x5d, 2, 12, 1 }, \
{ 0x5d, 4, 12, 1 }, \
{ 0x5d, 8, 12, 1 }, \
{ 0x5d, 10, 12, 1 }, \
{ 0x5e, 0, 12, 1 }, \
{ 0x5e, 4, 12, 1 }, \
{ 0x5e, 6, 12, 1 }, \
{ 0x5e, 8, 12, 1 }, \
{ 0x5f, 0, 12, 1 }, \
{ 0x5f, 9, 12, 1 }, \
{ 0x5f, 11, 12, 1 }, \
{ 0x60, 1, 12, 1 }, \
{ 0x60, 5, 12, 1 }, \
{ 0x60, 7, 12, 1 }, \
{ 0x60, 9, 12, 1 }, \
{ 0x61, 1, 12, 1 }, \
{ 0x52, 0, 12, 1 }, \
{ 0x52, 4, 12, 1 }, \
{ 0x52, 8, 12, 1 }, \
{ 0x53, 0, 12, 1 }
#define RT3070_DEF_RF \
{ 4, 0x40 }, \
{ 5, 0x03 }, \
@ -1251,3 +1490,278 @@ static const struct rt2860_rate {
{ 29, 0x9b }, \
{ 30, 0x09 }, \
{ 31, 0x10 }
#define RT3593_DEF_RF \
{ 1, 0x03 }, \
{ 3, 0x80 }, \
{ 5, 0x00 }, \
{ 6, 0x40 }, \
{ 8, 0xf1 }, \
{ 9, 0x02 }, \
{ 10, 0xd3 }, \
{ 11, 0x40 }, \
{ 12, 0x4e }, \
{ 13, 0x12 }, \
{ 18, 0x40 }, \
{ 22, 0x20 }, \
{ 30, 0x10 }, \
{ 31, 0x80 }, \
{ 32, 0x78 }, \
{ 33, 0x3b }, \
{ 34, 0x3c }, \
{ 35, 0xe0 }, \
{ 38, 0x86 }, \
{ 39, 0x23 }, \
{ 44, 0xd3 }, \
{ 45, 0xbb }, \
{ 46, 0x60 }, \
{ 49, 0x81 }, \
{ 50, 0x86 }, \
{ 51, 0x75 }, \
{ 52, 0x45 }, \
{ 53, 0x18 }, \
{ 54, 0x18 }, \
{ 55, 0x18 }, \
{ 56, 0xdb }, \
{ 57, 0x6e }
#define RT5390_DEF_RF \
{ 1, 0x0f }, \
{ 2, 0x80 }, \
{ 3, 0x88 }, \
{ 5, 0x10 }, \
{ 6, 0xa0 }, \
{ 7, 0x00 }, \
{ 10, 0x53 }, \
{ 11, 0x4a }, \
{ 12, 0x46 }, \
{ 13, 0x9f }, \
{ 14, 0x00 }, \
{ 15, 0x00 }, \
{ 16, 0x00 }, \
{ 18, 0x03 }, \
{ 19, 0x00 }, \
{ 20, 0x00 }, \
{ 21, 0x00 }, \
{ 22, 0x20 }, \
{ 23, 0x00 }, \
{ 24, 0x00 }, \
{ 25, 0xc0 }, \
{ 26, 0x00 }, \
{ 27, 0x09 }, \
{ 28, 0x00 }, \
{ 29, 0x10 }, \
{ 30, 0x10 }, \
{ 31, 0x80 }, \
{ 32, 0x80 }, \
{ 33, 0x00 }, \
{ 34, 0x07 }, \
{ 35, 0x12 }, \
{ 36, 0x00 }, \
{ 37, 0x08 }, \
{ 38, 0x85 }, \
{ 39, 0x1b }, \
{ 40, 0x0b }, \
{ 41, 0xbb }, \
{ 42, 0xd2 }, \
{ 43, 0x9a }, \
{ 44, 0x0e }, \
{ 45, 0xa2 }, \
{ 46, 0x7b }, \
{ 47, 0x00 }, \
{ 48, 0x10 }, \
{ 49, 0x94 }, \
{ 52, 0x38 }, \
{ 53, 0x84 }, \
{ 54, 0x78 }, \
{ 55, 0x44 }, \
{ 56, 0x22 }, \
{ 57, 0x80 }, \
{ 58, 0x7f }, \
{ 59, 0x8f }, \
{ 60, 0x45 }, \
{ 61, 0xdd }, \
{ 62, 0x00 }, \
{ 63, 0x00 }
#define RT5392_DEF_RF \
{ 1, 0x17 }, \
{ 3, 0x88 }, \
{ 5, 0x10 }, \
{ 6, 0xe0 }, \
{ 7, 0x00 }, \
{ 10, 0x53 }, \
{ 11, 0x4a }, \
{ 12, 0x46 }, \
{ 13, 0x9f }, \
{ 14, 0x00 }, \
{ 15, 0x00 }, \
{ 16, 0x00 }, \
{ 18, 0x03 }, \
{ 19, 0x4d }, \
{ 20, 0x00 }, \
{ 21, 0x8d }, \
{ 22, 0x20 }, \
{ 23, 0x0b }, \
{ 24, 0x44 }, \
{ 25, 0x80 }, \
{ 26, 0x82 }, \
{ 27, 0x09 }, \
{ 28, 0x00 }, \
{ 29, 0x10 }, \
{ 30, 0x10 }, \
{ 31, 0x80 }, \
{ 32, 0x20 }, \
{ 33, 0xc0 }, \
{ 34, 0x07 }, \
{ 35, 0x12 }, \
{ 36, 0x00 }, \
{ 37, 0x08 }, \
{ 38, 0x89 }, \
{ 39, 0x1b }, \
{ 40, 0x0f }, \
{ 41, 0xbb }, \
{ 42, 0xd5 }, \
{ 43, 0x9b }, \
{ 44, 0x0e }, \
{ 45, 0xa2 }, \
{ 46, 0x73 }, \
{ 47, 0x0c }, \
{ 48, 0x10 }, \
{ 49, 0x94 }, \
{ 50, 0x94 }, \
{ 51, 0x3a }, \
{ 52, 0x48 }, \
{ 53, 0x44 }, \
{ 54, 0x38 }, \
{ 55, 0x43 }, \
{ 56, 0xa1 }, \
{ 57, 0x00 }, \
{ 58, 0x39 }, \
{ 59, 0x07 }, \
{ 60, 0x45 }, \
{ 61, 0x91 }, \
{ 62, 0x39 }, \
{ 63, 0x07 }
#define RT5592_DEF_RF \
{ 1, 0x3f }, \
{ 3, 0x08 }, \
{ 5, 0x10 }, \
{ 6, 0xe4 }, \
{ 7, 0x00 }, \
{ 14, 0x00 }, \
{ 15, 0x00 }, \
{ 16, 0x00 }, \
{ 18, 0x03 }, \
{ 19, 0x4d }, \
{ 20, 0x10 }, \
{ 21, 0x8d }, \
{ 26, 0x82 }, \
{ 28, 0x00 }, \
{ 29, 0x10 }, \
{ 33, 0xc0 }, \
{ 34, 0x07 }, \
{ 35, 0x12 }, \
{ 47, 0x0c }, \
{ 53, 0x22 }, \
{ 63, 0x07 }
#define RT5592_2GHZ_DEF_RF \
{ 10, 0x90 }, \
{ 11, 0x4a }, \
{ 12, 0x52 }, \
{ 13, 0x42 }, \
{ 22, 0x40 }, \
{ 24, 0x4a }, \
{ 25, 0x80 }, \
{ 27, 0x42 }, \
{ 36, 0x80 }, \
{ 37, 0x08 }, \
{ 38, 0x89 }, \
{ 39, 0x1b }, \
{ 40, 0x0d }, \
{ 41, 0x9b }, \
{ 42, 0xd5 }, \
{ 43, 0x72 }, \
{ 44, 0x0e }, \
{ 45, 0xa2 }, \
{ 46, 0x6b }, \
{ 48, 0x10 }, \
{ 51, 0x3e }, \
{ 52, 0x48 }, \
{ 54, 0x38 }, \
{ 56, 0xa1 }, \
{ 57, 0x00 }, \
{ 58, 0x39 }, \
{ 60, 0x45 }, \
{ 61, 0x91 }, \
{ 62, 0x39 }
#define RT5592_5GHZ_DEF_RF \
{ 10, 0x97 }, \
{ 11, 0x40 }, \
{ 25, 0xbf }, \
{ 27, 0x42 }, \
{ 36, 0x00 }, \
{ 37, 0x04 }, \
{ 38, 0x85 }, \
{ 40, 0x42 }, \
{ 41, 0xbb }, \
{ 42, 0xd7 }, \
{ 45, 0x41 }, \
{ 48, 0x00 }, \
{ 57, 0x77 }, \
{ 60, 0x05 }, \
{ 61, 0x01 }
#define RT5592_CHAN_5GHZ \
{ 36, 64, 12, 0x2e }, \
{ 100, 165, 12, 0x0e }, \
{ 36, 64, 13, 0x22 }, \
{ 100, 165, 13, 0x42 }, \
{ 36, 64, 22, 0x60 }, \
{ 100, 165, 22, 0x40 }, \
{ 36, 64, 23, 0x7f }, \
{ 100, 153, 23, 0x3c }, \
{ 155, 165, 23, 0x38 }, \
{ 36, 50, 24, 0x09 }, \
{ 52, 64, 24, 0x07 }, \
{ 100, 153, 24, 0x06 }, \
{ 155, 165, 24, 0x05 }, \
{ 36, 64, 39, 0x1c }, \
{ 100, 138, 39, 0x1a }, \
{ 140, 165, 39, 0x18 }, \
{ 36, 64, 43, 0x5b }, \
{ 100, 138, 43, 0x3b }, \
{ 140, 165, 43, 0x1b }, \
{ 36, 64, 44, 0x40 }, \
{ 100, 138, 44, 0x20 }, \
{ 140, 165, 44, 0x10 }, \
{ 36, 64, 46, 0x00 }, \
{ 100, 138, 46, 0x18 }, \
{ 140, 165, 46, 0x08 }, \
{ 36, 64, 51, 0xfe }, \
{ 100, 124, 51, 0xfc }, \
{ 126, 165, 51, 0xec }, \
{ 36, 64, 52, 0x0c }, \
{ 100, 138, 52, 0x06 }, \
{ 140, 165, 52, 0x06 }, \
{ 36, 64, 54, 0xf8 }, \
{ 100, 165, 54, 0xeb }, \
{ 36, 50, 55, 0x06 }, \
{ 52, 64, 55, 0x04 }, \
{ 100, 138, 55, 0x01 }, \
{ 140, 165, 55, 0x00 }, \
{ 36, 50, 56, 0xd3 }, \
{ 52, 128, 56, 0xbb }, \
{ 130, 165, 56, 0xab }, \
{ 36, 64, 58, 0x15 }, \
{ 100, 116, 58, 0x1d }, \
{ 118, 165, 58, 0x15 }, \
{ 36, 64, 59, 0x7f }, \
{ 100, 138, 59, 0x3f }, \
{ 140, 165, 59, 0x7c }, \
{ 36, 64, 62, 0x15 }, \
{ 100, 116, 62, 0x1d }, \
{ 118, 165, 62, 0x15 }

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sys/dev/ic/rt2860var.h Normal file
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@ -0,0 +1,211 @@
/* $NetBSD: rt2860var.h,v 1.1 2016/04/26 21:17:20 christos Exp $ */
/* $OpenBSD: rt2860var.h,v 1.23 2016/03/21 21:16:30 stsp Exp $ */
/*-
* Copyright (c) 2007
* Damien Bergamini <damien.bergamini@free.fr>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#define RT2860_MAX_SCATTER 15
#define RT2860_MAX_SCATTER_TXD (1 + (RT2860_MAX_SCATTER / 2))
#define RT2860_RX_RING_COUNT 128
#define RT2860_TX_RING_COUNT 64
#define RT2860_TX_RING_MAX (RT2860_TX_RING_COUNT - 1)
#define RT2860_TX_RING_ONEMORE (RT2860_TX_RING_MAX - RT2860_MAX_SCATTER_TXD)
#define RT2860_TX_POOL_COUNT (RT2860_TX_RING_COUNT * 2)
/* HW supports up to 255 STAs */
#define RT2860_WCID_MAX 254
#define RT2860_AID2WCID(aid) ((aid) & 0xff)
struct rt2860_rx_radiotap_header {
struct ieee80211_radiotap_header wr_ihdr;
uint8_t wr_flags;
uint8_t wr_rate;
uint16_t wr_chan_freq;
uint16_t wr_chan_flags;
uint8_t wr_dbm_antsignal;
uint8_t wr_antenna;
uint8_t wr_antsignal;
} __packed;
#define RT2860_RX_RADIOTAP_PRESENT \
(1 << IEEE80211_RADIOTAP_FLAGS | \
1 << IEEE80211_RADIOTAP_RATE | \
1 << IEEE80211_RADIOTAP_CHANNEL | \
1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL | \
1 << IEEE80211_RADIOTAP_ANTENNA | \
1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL)
struct rt2860_tx_radiotap_header {
struct ieee80211_radiotap_header wt_ihdr;
uint8_t wt_flags;
uint8_t wt_rate;
uint16_t wt_chan_freq;
uint16_t wt_chan_flags;
uint8_t wt_hwqueue;
} __packed;
#define RT2860_TX_RADIOTAP_PRESENT \
(1 << IEEE80211_RADIOTAP_FLAGS | \
1 << IEEE80211_RADIOTAP_RATE | \
1 << IEEE80211_RADIOTAP_CHANNEL | \
1 << IEEE80211_RADIOTAP_HWQUEUE)
struct rt2860_tx_data {
struct rt2860_txwi *txwi;
struct mbuf *m;
struct ieee80211_node *ni;
bus_dmamap_t map;
bus_addr_t paddr;
SLIST_ENTRY(rt2860_tx_data) next;
};
struct rt2860_tx_ring {
struct rt2860_txd *txd;
bus_addr_t paddr;
bus_dmamap_t map;
bus_dma_segment_t seg;
struct rt2860_tx_data *data[RT2860_TX_RING_COUNT];
int cur;
int next;
int queued;
};
struct rt2860_rx_data {
struct mbuf *m;
bus_dmamap_t map;
};
struct rt2860_rx_ring {
struct rt2860_rxd *rxd;
bus_addr_t paddr;
bus_dmamap_t map;
bus_dma_segment_t seg;
unsigned int cur; /* must be unsigned */
struct rt2860_rx_data data[RT2860_RX_RING_COUNT];
};
struct rt2860_node {
struct ieee80211_node ni;
uint8_t wcid;
uint8_t ridx[IEEE80211_RATE_MAXSIZE];
uint8_t ctl_ridx[IEEE80211_RATE_MAXSIZE];
};
struct rt2860_softc {
struct device sc_dev;
struct ieee80211com sc_ic;
int (*sc_newstate)(struct ieee80211com *,
enum ieee80211_state, int);
struct ieee80211_amrr amrr;
int (*sc_enable)(struct rt2860_softc *);
void (*sc_disable)(struct rt2860_softc *);
bus_dma_tag_t sc_dmat;
bus_space_tag_t sc_st;
bus_space_handle_t sc_sh;
uint16_t (*sc_srom_read)(struct rt2860_softc *,
uint16_t);
int sc_flags;
#define RT2860_ENABLED (1 << 0)
#define RT2860_ADVANCED_PS (1 << 1)
#define RT2860_PCIE (1 << 2)
uint32_t sc_ic_flags;
int fixed_ridx;
u_char *ucode;
size_t ucsize;
struct rt2860_tx_ring txq[6];
struct rt2860_rx_ring rxq;
SLIST_HEAD(, rt2860_tx_data) data_pool;
struct rt2860_tx_data data[RT2860_TX_POOL_COUNT];
bus_dmamap_t txwi_map;
bus_dma_segment_t txwi_seg;
caddr_t txwi_vaddr;
int sc_tx_timer;
int mgtqid;
uint8_t qfullmsk;
uint16_t mac_ver;
uint16_t mac_rev;
uint8_t rf_rev;
uint8_t freq;
uint8_t ntxchains;
uint8_t nrxchains;
uint8_t pslevel;
int8_t txpow1[54];
int8_t txpow2[54];
int8_t rssi_2ghz[3];
int8_t rssi_5ghz[3];
uint8_t lna[4];
uint8_t rf24_20mhz;
uint8_t rf24_40mhz;
uint8_t patch_dac;
uint8_t rfswitch;
uint8_t ext_2ghz_lna;
uint8_t ext_5ghz_lna;
uint8_t calib_2ghz;
uint8_t calib_5ghz;
uint8_t txmixgain_2ghz;
uint8_t txmixgain_5ghz;
uint8_t tssi_2ghz[9];
uint8_t tssi_5ghz[9];
uint8_t step_2ghz;
uint8_t step_5ghz;
struct {
uint8_t reg;
uint8_t val;
} bbp[8], rf[10];
uint8_t leds;
uint16_t led[3];
uint32_t txpow20mhz[5];
uint32_t txpow40mhz_2ghz[5];
uint32_t txpow40mhz_5ghz[5];
struct ieee80211_amrr_node amn[RT2860_WCID_MAX + 1];
#if NBPFILTER > 0
caddr_t sc_drvbpf;
union {
struct rt2860_rx_radiotap_header th;
uint8_t pad[64];
} sc_rxtapu;
#define sc_rxtap sc_rxtapu.th
int sc_rxtap_len;
union {
struct rt2860_tx_radiotap_header th;
uint8_t pad[64];
} sc_txtapu;
#define sc_txtap sc_txtapu.th
int sc_txtap_len;
#endif
};
int rt2860_attach(void *, int);
int rt2860_detach(void *);
void rt2860_suspend(void *);
void rt2860_wakeup(void *);
int rt2860_intr(void *);