Plug support for PJ4B core into our ARM CPU support infrastructure.
Obtained from Marvell, Semihalf.
This commit is contained in:
rkujawa
parent
60dd6bd0af
commit
33587300c0
@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.c,v 1.119 2012/12/28 03:48:00 msaitoh Exp $ */
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/* $NetBSD: cpufunc.c,v 1.120 2013/05/19 15:37:06 rkujawa Exp $ */
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/*
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* arm7tdmi support code Copyright (c) 2001 John Fremlin
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@ -49,7 +49,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.119 2012/12/28 03:48:00 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.120 2013/05/19 15:37:06 rkujawa Exp $");
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#include "opt_compat_netbsd.h"
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#include "opt_cpuoptions.h"
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@ -1329,6 +1329,67 @@ struct cpu_functions cortex_cpufuncs = {
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};
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#endif /* CPU_CORTEX */
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#ifdef CPU_PJ4B
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struct cpu_functions pj4bv7_cpufuncs = {
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/* CPU functions */
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.cf_id = cpufunc_id,
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.cf_cpwait = pj4b_drain_writebuf,
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/* MMU functions */
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.cf_control = cpufunc_control,
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.cf_domains = cpufunc_domains,
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.cf_setttb = pj4b_setttb,
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.cf_faultstatus = cpufunc_faultstatus,
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.cf_faultaddress = cpufunc_faultaddress,
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/* TLB functions */
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.cf_tlb_flushID = pj4b_tlb_flushID,
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.cf_tlb_flushID_SE = pj4b_tlb_flushID_SE,
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.cf_tlb_flushI = pj4b_tlb_flushID,
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.cf_tlb_flushI_SE = pj4b_tlb_flushID_SE,
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.cf_tlb_flushD = pj4b_tlb_flushID,
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.cf_tlb_flushD_SE = pj4b_tlb_flushID_SE,
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/* Cache operations */
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.cf_icache_sync_all = armv7_idcache_wbinv_all,
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.cf_icache_sync_range = pj4b_icache_sync_range,
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.cf_dcache_wbinv_all = armv7_dcache_wbinv_all,
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.cf_dcache_wbinv_range = pj4b_dcache_wbinv_range,
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.cf_dcache_inv_range = pj4b_dcache_inv_range,
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.cf_dcache_wb_range = pj4b_dcache_wb_range,
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.cf_sdcache_wbinv_range = (void *)cpufunc_nullop,
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.cf_sdcache_inv_range = (void *)cpufunc_nullop,
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.cf_sdcache_wb_range = (void *)cpufunc_nullop,
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.cf_idcache_wbinv_all = armv7_idcache_wbinv_all,
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.cf_idcache_wbinv_range = pj4b_idcache_wbinv_range,
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/* Other functions */
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.cf_flush_prefetchbuf = pj4b_drain_readbuf,
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.cf_drain_writebuf = pj4b_drain_writebuf,
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.cf_flush_brnchtgt_C = pj4b_flush_brnchtgt_all,
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.cf_flush_brnchtgt_E = pj4b_flush_brnchtgt_va,
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.cf_sleep = (void *)cpufunc_nullop,
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/* Soft functions */
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.cf_dataabt_fixup = cpufunc_null_fixup,
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.cf_prefetchabt_fixup = cpufunc_null_fixup,
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.cf_context_switch = pj4b_context_switch,
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.cf_setup = pj4bv7_setup
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};
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#endif /* CPU_PJ4B */
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#ifdef CPU_SHEEVA
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struct cpu_functions sheeva_cpufuncs = {
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/* CPU functions */
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@ -1403,7 +1464,7 @@ u_int cputype;
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defined(CPU_FA526) || \
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defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
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defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \
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defined(CPU_CORTEX) || defined(CPU_SHEEVA)
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defined(CPU_CORTEX) || defined(CPU_PJ4B) || defined(CPU_SHEEVA)
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static void get_cachetype_cp15(void);
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/* Additional cache information local to this file. Log2 of some of the
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@ -1418,7 +1479,7 @@ get_cachesize_cp15(int cssr)
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{
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u_int csid;
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#if (CPU_CORTEX) > 0
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#if ((CPU_CORTEX) > 0) || defined(CPU_PJ4B)
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__asm volatile(".arch\tarmv7a");
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__asm volatile("mcr p15, 2, %0, c0, c0, 0" :: "r" (cssr));
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__asm volatile("isb"); /* sync to the new cssr */
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@ -2010,6 +2071,21 @@ set_cpufuncs(void)
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return 0;
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}
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#endif /* CPU_CORTEX */
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#if defined(CPU_PJ4B)
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if ((cputype == CPU_ID_MV88SV581X_V6 ||
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cputype == CPU_ID_MV88SV581X_V7 ||
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cputype == CPU_ID_MV88SV584X_V7 ||
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cputype == CPU_ID_ARM_88SV581X_V6 ||
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cputype == CPU_ID_ARM_88SV581X_V7) &&
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(cpu_pfr(0) & ARM_PFR0_THUMBEE_MASK)) {
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cpufuncs = pj4bv7_cpufuncs;
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get_cachetype_cp15();
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pmap_pte_init_armv7();
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return 0;
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}
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#endif /* CPU_PJ4B */
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/*
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* Bzzzz. And the answer was ...
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*/
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@ -2888,6 +2964,40 @@ arm11mpcore_setup(char *args)
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}
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#endif /* CPU_ARM11MPCORE */
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#ifdef CPU_PJ4B
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void
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pj4bv7_setup(char *args)
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{
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int cpuctrl;
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pj4b_config();
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cpuctrl = CPU_CONTROL_MMU_ENABLE;
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#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
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cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
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#endif
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cpuctrl |= CPU_CONTROL_DC_ENABLE;
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cpuctrl |= CPU_CONTROL_IC_ENABLE;
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cpuctrl |= (0xf << 3);
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cpuctrl |= CPU_CONTROL_BPRD_ENABLE;
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cpuctrl |= (0x5 << 16) | (1 < 22);
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cpuctrl |= CPU_CONTROL_XP_ENABLE;
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if (vector_page == ARM_VECTORS_HIGH)
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cpuctrl |= CPU_CONTROL_VECRELOC;
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/* Clear out the cache */
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cpu_idcache_wbinv_all();
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/* Set the control register */
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cpu_control(0xffffffff, cpuctrl);
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/* And again. */
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cpu_idcache_wbinv_all();
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curcpu()->ci_ctrl = cpuctrl;
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}
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#endif /* CPU_PJ4B */
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#if defined(CPU_CORTEX)
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struct cpu_option armv7_options[] = {
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