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Define a `DMA_FLUSH' macro; dma chip revs 0 & 1 have a different bit 

to reset the internal state engine.
This commit is contained in:
pk 1998-02-07 22:41:27 +00:00
parent 8e8eed4ba7
commit 334b20bbd6
1 changed files with 18 additions and 4 deletions
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22
sys/arch/sparc/dev/dma.c
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@ -1,4 +1,4 @@
/* $NetBSD: dma.c,v 1.48 1998/01/12 20:23:46 thorpej Exp $ */ /* $NetBSD: dma.c,v 1.49 1998/02/07 22:41:27 pk Exp $ */
/* /*
* Copyright (c) 1994 Paul Kranenburg. All rights reserved. * Copyright (c) 1994 Paul Kranenburg. All rights reserved.
@ -301,13 +301,27 @@ espsearch:
DMAWAIT(sc, sc->sc_regs->csr & D_DRAINING, "DRAINING", dontpanic);\ DMAWAIT(sc, sc->sc_regs->csr & D_DRAINING, "DRAINING", dontpanic);\
} while(0) } while(0)
#define DMA_FLUSH(sc, dontpanic) do { \
int csr; \
/* \
* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
* and "drain" bits while it is still thinking about a \
* request. \
* other revs: D_R_PEND bit reads as 0 \
*/ \
DMAWAIT(sc, sc->sc_regs->csr & D_R_PEND, "R_PEND", dontpanic); \
csr = DMACSR(sc); \
csr &= ~(D_WRITE|D_EN_DMA); \
csr |= D_INVALIDATE; \
DMACSR(sc) = csr; \
} while(0)
void void
dma_reset(sc, isledma) dma_reset(sc, isledma)
struct dma_softc *sc; struct dma_softc *sc;
int isledma; int isledma;
{ {
DMA_DRAIN(sc, 1); DMA_FLUSH(sc, 1);
DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */
DMACSR(sc) |= D_RESET; /* reset DMA */ DMACSR(sc) |= D_RESET; /* reset DMA */
DELAY(200); /* what should this be ? */ DELAY(200); /* what should this be ? */
/*DMAWAIT1(sc); why was this here? */ /*DMAWAIT1(sc); why was this here? */
@ -384,7 +398,7 @@ dma_setup(sc, addr, len, datain, dmasize)
{ {
u_long csr; u_long csr;
DMA_DRAIN(sc, 0); DMA_FLUSH(sc, 0);
#if 0 #if 0
DMACSR(sc) &= ~D_INT_EN; DMACSR(sc) &= ~D_INT_EN;