Totally revamp device initialization using clue from the reference
driver. I also have re-organized the code a lot.
This commit is contained in:
dyoung
parent
9ad89f8c4a
commit
3341b62f3e
387
sys/dev/ic/atw.c
387
sys/dev/ic/atw.c
@ -1,4 +1,4 @@
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/* $NetBSD: atw.c,v 1.63 2004/07/15 07:25:40 dyoung Exp $ */
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/* $NetBSD: atw.c,v 1.64 2004/07/15 07:26:17 dyoung Exp $ */
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/*-
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* Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc.
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@ -41,7 +41,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.63 2004/07/15 07:25:40 dyoung Exp $");
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__KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.64 2004/07/15 07:26:17 dyoung Exp $");
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#include "bpfilter.h"
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@ -957,6 +957,186 @@ atw_clear_sram(struct atw_softc *sc)
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* set TX rate
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*/
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/* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass
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* without receiving a beacon with the preferred BSSID & SSID.
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* atw_write_bssid & atw_write_ssid set the BSSID & SSID.
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*/
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static void
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atw_wcsr_init(struct atw_softc *sc)
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{
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uint32_t wcsr;
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wcsr = ATW_READ(sc, ATW_WCSR);
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wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE);
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wcsr |= LSHIFT(7, ATW_WCSR_BLN_MASK);
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ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */
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DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n",
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sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR)));
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}
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/* Turn off power management. Set Rx store-and-forward mode. */
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static void
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atw_cmdr_init(struct atw_softc *sc)
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{
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uint32_t cmdr;
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cmdr = ATW_READ(sc, ATW_CMDR);
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cmdr &= ~ATW_CMDR_APM;
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cmdr |= ATW_CMDR_RTE;
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cmdr &= ~ATW_CMDR_DRT_MASK;
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cmdr |= ATW_CMDR_DRT_SF;
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ATW_WRITE(sc, ATW_CMDR, cmdr);
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}
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static void
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atw_tofs2_init(struct atw_softc *sc)
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{
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uint32_t tofs2;
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/* XXX this magic can probably be figured out from the RFMD docs */
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#ifndef ATW_REFSLAVE
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tofs2 = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */
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LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */
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LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */
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LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */
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LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */
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LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */
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LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */
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LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */
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#else
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/* XXX new magic from reference driver source */
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tofs2 = LSHIFT(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */
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LSHIFT(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */
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LSHIFT(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */
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LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */
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LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */
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LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */
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LSHIFT(1, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */
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LSHIFT(8, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */
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#endif
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ATW_WRITE(sc, ATW_TOFS2, tofs2);
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}
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static void
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atw_nar_init(struct atw_softc *sc)
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{
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ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB);
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}
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static void
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atw_txlmt_init(struct atw_softc *sc)
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{
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ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) |
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LSHIFT(1, ATW_TXLMT_SRTYLIM_MASK));
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}
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static void
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atw_test1_init(struct atw_softc *sc)
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{
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uint32_t test1;
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test1 = ATW_READ(sc, ATW_TEST1);
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test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL);
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/* XXX magic 0x1 */
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test1 |= LSHIFT(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL;
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ATW_WRITE(sc, ATW_TEST1, test1);
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}
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static void
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atw_rf_reset(struct atw_softc *sc)
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{
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/* XXX this resets an Intersil RF front-end? */
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/* TBD condition on Intersil RFType? */
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ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN);
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DELAY(10 * 1000);
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ATW_WRITE(sc, ATW_SYNRF, 0);
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DELAY(5 * 1000);
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}
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/* Set 16 TU max duration for the contention-free period (CFP). */
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static void
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atw_cfp_init(struct atw_softc *sc)
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{
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uint32_t cfpp;
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cfpp = ATW_READ(sc, ATW_CFPP);
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cfpp &= ~ATW_CFPP_CFPMD;
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cfpp |= LSHIFT(16, ATW_CFPP_CFPMD);
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ATW_WRITE(sc, ATW_CFPP, cfpp);
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}
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static void
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atw_tofs0_init(struct atw_softc *sc)
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{
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/* XXX I guess that the Cardbus clock is 22MHz?
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* I am assuming that the role of ATW_TOFS0_USCNT is
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* to divide the bus clock to get a 1MHz clock---the datasheet is not
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* very clear on this point. It says in the datasheet that it is
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* possible for the ADM8211 to accomodate bus speeds between 22MHz
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* and 33MHz; maybe this is the way? I see a binary-only driver write
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* these values. These values are also the power-on default.
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*/
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ATW_WRITE(sc, ATW_TOFS0,
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LSHIFT(22, ATW_TOFS0_USCNT_MASK) |
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ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */);
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}
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/* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */
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static void
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atw_ifs_init(struct atw_softc *sc)
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{
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uint32_t ifst;
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/* XXX EIFS=0x64, SIFS=110 are used by the reference driver.
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* Go figure.
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*/
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ifst = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) |
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LSHIFT(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22MHz cycles */,
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ATW_IFST_SIFS_MASK) |
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LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) |
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LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK);
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ATW_WRITE(sc, ATW_IFST, ifst);
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}
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static void
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atw_response_times_init(struct atw_softc *sc)
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{
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/* XXX More magic. Relates to ACK timing? The datasheet seems to
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* indicate that the MAC expects at least SIFS + MIRT microseconds
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* to pass after it transmits a frame that requires a response;
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* it waits at most SIFS + MART microseconds for the response.
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* Surely this is not the ACK timeout?
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*/
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ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) |
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LSHIFT(0xff, ATW_RSPT_MIRT_MASK));
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}
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/* Set up the MMI read/write addresses for the baseband. The Tx/Rx
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* engines read and write baseband registers after Rx and before
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* Tx, respectively.
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*/
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static void
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atw_bbp_io_init(struct atw_softc *sc)
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{
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switch (sc->sc_bbptype) {
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case ATW_BBPTYPE_INTERSIL:
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ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL);
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ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL);
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ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL);
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break;
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case ATW_BBPTYPE_MARVEL:
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/* TBD find out the Marvel settings. */
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break;
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case ATW_BBPTYPE_RFMD:
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default:
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ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD);
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ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD);
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ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD);
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break;
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}
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ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK);
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}
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/*
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* atw_init: [ ifnet interface function ]
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*
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@ -969,7 +1149,6 @@ atw_init(struct ifnet *ifp)
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struct ieee80211com *ic = &sc->sc_ic;
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struct atw_txsoft *txs;
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struct atw_rxsoft *rxs;
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u_int32_t reg;
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int i, error = 0;
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if ((error = atw_enable(sc)) != 0)
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@ -985,175 +1164,52 @@ atw_init(struct ifnet *ifp)
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__func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan),
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ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags));
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/* Turn off APM??? (A binary-only driver does this.)
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*
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* Set Rx store-and-forward mode.
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*/
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reg = ATW_READ(sc, ATW_CMDR);
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reg &= ~ATW_CMDR_APM;
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reg &= ~ATW_CMDR_DRT_MASK;
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reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK);
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atw_wcsr_init(sc);
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ATW_WRITE(sc, ATW_CMDR, reg);
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atw_cmdr_init(sc);
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/* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s.
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*
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* XXX a binary-only driver sets a different service field than
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* 0. why?
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* XXX Set transmit power for ATIM, RTS, Beacon.
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*/
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reg = ATW_READ(sc, ATW_PLCPHD);
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reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK);
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reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) |
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LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK);
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ATW_WRITE(sc, ATW_PLCPHD, reg);
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ATW_WRITE(sc, ATW_PLCPHD, LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) |
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LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK));
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/* XXX this magic can probably be figured out from the RFMD docs */
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reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */
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LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */
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LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */
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LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */
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LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */
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LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */
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LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */
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LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */
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ATW_WRITE(sc, ATW_TOFS2, reg);
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atw_tofs2_init(sc);
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ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) |
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LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK));
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atw_nar_init(sc);
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/* XXX this resets an Intersil RF front-end? */
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/* TBD condition on Intersil RFType? */
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ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN);
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DELAY(10 * 1000);
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ATW_WRITE(sc, ATW_SYNRF, 0);
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DELAY(5 * 1000);
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atw_txlmt_init(sc);
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/* 16 TU max duration for contention-free period */
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reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD;
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ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD));
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atw_test1_init(sc);
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/* XXX I guess that the Cardbus clock is 22MHz?
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* I am assuming that the role of ATW_TOFS0_USCNT is
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* to divide the bus clock to get a 1MHz clock---the datasheet is not
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* very clear on this point. It says in the datasheet that it is
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* possible for the ADM8211 to accomodate bus speeds between 22MHz
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* and 33MHz; maybe this is the way? I see a binary-only driver write
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* these values. These values are also the power-on default.
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atw_rf_reset(sc);
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atw_cfp_init(sc);
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atw_tofs0_init(sc);
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atw_ifs_init(sc);
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/* XXX Fall asleep after one second of inactivity.
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* XXX A frame may only dribble in for 65536us.
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*/
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ATW_WRITE(sc, ATW_TOFS0,
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LSHIFT(22, ATW_TOFS0_USCNT_MASK) |
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ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */);
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ATW_WRITE(sc, ATW_RMD,
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LSHIFT(1, ATW_RMD_PCNT) | LSHIFT(0xffff, ATW_RMD_RMRD_MASK));
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/* Initialize interframe spacing. EIFS=0x64 is used by a binary-only
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* driver. Go figure.
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*/
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reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) |
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LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */,
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ATW_IFST_SIFS_MASK) |
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LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) |
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LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK);
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atw_response_times_init(sc);
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ATW_WRITE(sc, ATW_IFST, reg);
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atw_bbp_io_init(sc);
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/* XXX More magic. Might relate to ACK timing. */
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ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) |
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LSHIFT(0xff, ATW_RSPT_MIRT_MASK));
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/* Set up the MMI read/write addresses for the BBP.
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*
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* TBD find out the Marvel settings.
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*/
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switch (sc->sc_bbptype) {
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case ATW_BBPTYPE_INTERSIL:
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ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL);
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ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL);
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ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL);
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break;
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case ATW_BBPTYPE_MARVEL:
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break;
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case ATW_BBPTYPE_RFMD:
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ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD);
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ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD);
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ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD);
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default:
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break;
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}
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sc->sc_wepctl = 0;
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ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK);
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ATW_WRITE(sc, ATW_STSR, 0xffffffff);
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if ((error = atw_rf3000_init(sc)) != 0)
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goto out;
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/*
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* Initialize the PCI Access Register.
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*/
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sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */
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/*
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* If we're allowed to do so, use Memory Read Line
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* and Memory Read Multiple.
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*
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* XXX Should we use Memory Write and Invalidate?
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*/
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if (sc->sc_flags & ATWF_MRL)
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sc->sc_busmode |= ATW_PAR_MRLE;
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if (sc->sc_flags & ATWF_MRM)
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sc->sc_busmode |= ATW_PAR_MRME;
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if (sc->sc_flags & ATWF_MWI)
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sc->sc_busmode |= ATW_PAR_MWIE;
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if (sc->sc_maxburst == 0)
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sc->sc_maxburst = 8; /* ADM8211 default */
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switch (sc->sc_cacheline) {
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default:
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/* Use burst length. */
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break;
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case 8:
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sc->sc_busmode |= ATW_PAR_CAL_8DW;
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break;
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case 16:
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sc->sc_busmode |= ATW_PAR_CAL_16DW;
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break;
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case 32:
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sc->sc_busmode |= ATW_PAR_CAL_32DW;
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break;
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}
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switch (sc->sc_maxburst) {
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case 1:
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sc->sc_busmode |= ATW_PAR_PBL_1DW;
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break;
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case 2:
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sc->sc_busmode |= ATW_PAR_PBL_2DW;
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break;
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case 4:
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sc->sc_busmode |= ATW_PAR_PBL_4DW;
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break;
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case 8:
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sc->sc_busmode |= ATW_PAR_PBL_8DW;
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break;
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case 16:
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sc->sc_busmode |= ATW_PAR_PBL_16DW;
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break;
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||||
case 32:
|
||||
sc->sc_busmode |= ATW_PAR_PBL_32DW;
|
||||
break;
|
||||
default:
|
||||
sc->sc_busmode |= ATW_PAR_PBL_8DW;
|
||||
break;
|
||||
}
|
||||
|
||||
ATW_WRITE(sc, ATW_PAR, sc->sc_busmode);
|
||||
DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname,
|
||||
ATW_READ(sc, ATW_PAR), sc->sc_busmode));
|
||||
|
||||
/*
|
||||
* Initialize the OPMODE register. We don't write it until
|
||||
* we're ready to begin the transmit and receive processes.
|
||||
*/
|
||||
sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST |
|
||||
sc->sc_txth[sc->sc_txthresh].txth_opmode;
|
||||
|
||||
/*
|
||||
* Initialize the transmit descriptor ring.
|
||||
*/
|
||||
@ -1206,15 +1262,6 @@ atw_init(struct ifnet *ifp)
|
||||
}
|
||||
sc->sc_rxptr = 0;
|
||||
|
||||
/* disable all wake-up events */
|
||||
ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E|
|
||||
ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE|
|
||||
ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE|
|
||||
ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE);
|
||||
|
||||
/* ack all wake-up events */
|
||||
ATW_SET(sc, ATW_WCSR, 0);
|
||||
|
||||
/*
|
||||
* Initialize the interrupt mask and enable interrupts.
|
||||
*/
|
||||
@ -1246,8 +1293,12 @@ atw_init(struct ifnet *ifp)
|
||||
/*
|
||||
* Give the transmit and receive rings to the ADM8211.
|
||||
*/
|
||||
ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext));
|
||||
ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr));
|
||||
ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext));
|
||||
|
||||
sc->sc_txthresh = 0;
|
||||
sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST |
|
||||
sc->sc_txth[sc->sc_txthresh].txth_opmode;
|
||||
|
||||
/* common 802.11 configuration */
|
||||
ic->ic_flags &= ~IEEE80211_F_IBSSON;
|
||||
@ -1264,8 +1315,6 @@ atw_init(struct ifnet *ifp)
|
||||
break;
|
||||
}
|
||||
|
||||
atw_start_beacon(sc, 0);
|
||||
|
||||
switch (ic->ic_opmode) {
|
||||
case IEEE80211_M_AHDEMO:
|
||||
case IEEE80211_M_HOSTAP:
|
||||
@ -1277,11 +1326,15 @@ atw_init(struct ifnet *ifp)
|
||||
break;
|
||||
}
|
||||
|
||||
sc->sc_wepctl = 0;
|
||||
|
||||
atw_write_ssid(sc);
|
||||
atw_write_sup_rates(sc);
|
||||
if (ic->ic_caps & IEEE80211_C_WEP)
|
||||
atw_write_wep(sc);
|
||||
|
||||
ic->ic_state = IEEE80211_S_INIT;
|
||||
|
||||
/*
|
||||
* Set the receive filter. This will start the transmit and
|
||||
* receive processes.
|
||||
@ -1298,12 +1351,14 @@ atw_init(struct ifnet *ifp)
|
||||
*/
|
||||
ifp->if_flags |= IFF_RUNNING;
|
||||
ifp->if_flags &= ~IFF_OACTIVE;
|
||||
ic->ic_state = IEEE80211_S_INIT;
|
||||
|
||||
if (ic->ic_opmode != IEEE80211_M_MONITOR)
|
||||
error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
|
||||
else
|
||||
/* send no beacons, yet. */
|
||||
atw_start_beacon(sc, 0);
|
||||
|
||||
if (ic->ic_opmode == IEEE80211_M_MONITOR)
|
||||
error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
|
||||
else
|
||||
error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
|
||||
out:
|
||||
if (error) {
|
||||
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user