Switch to cacheops. This closes PR 1960.
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@ -1,4 +1,4 @@
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/* $NetBSD: db_memrw.c,v 1.8 1997/10/09 07:35:04 jtc Exp $ */
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/* $NetBSD: db_memrw.c,v 1.9 1999/09/06 21:50:47 is Exp $ */
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/*-
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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@ -55,6 +55,8 @@
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#include <machine/cpu.h>
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#include <machine/pte.h>
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#include <m68k/cacheops.h>
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static char db_read_data __P((char *src));
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void db_read_bytes __P((vm_offset_t addr, register int size, register char *data));
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static void db_write_text __P((char *dst, int ch));
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.s,v 1.109 1999/04/29 16:22:03 christos Exp $ */
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/* $NetBSD: locore.s,v 1.110 1999/09/06 21:50:47 is Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -954,7 +954,7 @@ Lunshadow:
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/* flush TLB and turn on caches */
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jbsr _TBIA | invalidate TLB
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jbsr __TBIA | invalidate TLB
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movl #CACHE_ON,d0
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tstl d5
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jeq Lcacheon
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@ -1392,7 +1392,7 @@ ENTRY(copyseg)
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movl _CMAP2,a0
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movl _CADDR2,sp@- | destination kernel VA
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movl d0,a0@ | load in page table
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jbsr _TBIS | invalidate any old mapping
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jbsr __TBIS | invalidate any old mapping
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addql #4,sp
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movl _CADDR2,a1 | destination addr
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movl sp@(4),a0 | source addr
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@ -1409,7 +1409,6 @@ Lcpydone:
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/*
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* Invalidate entire TLB.
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*/
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ENTRY(TBIA)
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__TBIA:
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cmpl #MMU_68040,_mmutype
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jeq Ltbia040
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@ -1435,7 +1434,7 @@ Ltbiano60:
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/*
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* Invalidate any TLB entry for given VA (TB Invalidate Single)
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*/
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ENTRY(TBIS)
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__TBIS:
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#ifdef DEBUG
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tstl fulltflush | being conservative?
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jne __TBIA | yes, flush entire TLB
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@ -1469,178 +1468,6 @@ Ltbisno60:
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#endif
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rts
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/*
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* Invalidate supervisor side of TLB
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*/
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ENTRY(TBIAS)
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#ifdef DEBUG
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tstl fulltflush | being conservative?
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jne __TBIA | yes, flush everything
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#endif
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cmpl #MMU_68040,_mmutype
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jeq Ltbias040
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tstl _mmutype
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jpl Lmc68851c | 68851?
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pflush #4,#4 | flush supervisor TLB entries
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movl #DC_CLEAR,d0
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movc d0,cacr | invalidate on-chip d-cache
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rts
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Lmc68851c:
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pflushs #4,#4 | flush supervisor TLB entries
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rts
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Ltbias040:
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| 68040 cannot specify supervisor/user on pflusha, so we flush all
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.word 0xf518 | pflusha
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#ifdef M68060
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cmpl #CPU_68060,_cputype
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jne Ltbiasno60
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movc cacr,d0
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orl #IC60_CABC,d0 | and clear all btc entries
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movc d0,cacr
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Ltbiasno60:
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#endif
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rts
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/*
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* Invalidate user side of TLB
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*/
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ENTRY(TBIAU)
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#ifdef DEBUG
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tstl fulltflush | being conservative?
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jne __TBIA | yes, flush everything
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#endif
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cmpl #MMU_68040,_mmutype
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jeq Ltbiau040
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tstl _mmutype
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jpl Lmc68851d | 68851?
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pflush #0,#4 | flush user TLB entries
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movl #DC_CLEAR,d0
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movc d0,cacr | invalidate on-chip d-cache
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rts
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Lmc68851d:
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pflushs #0,#4 | flush user TLB entries
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rts
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Ltbiau040:
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| 68040 cannot specify supervisor/user on pflusha, so we flush all
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.word 0xf518 | pflusha
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#ifdef M68060
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cmpl #CPU_68060,_cputype
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jne Ltbiauno60
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movc cacr,d0
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orl #IC60_CUBC,d0 | but only user btc entries
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movc d0,cacr
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Ltbiauno60:
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#endif
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rts
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/*
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* Invalidate instruction cache
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*/
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ENTRY(ICIA)
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ENTRY(ICPA)
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#if defined(M68030) || defined(M68020)
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#if defined(M68040) || defined(M68060)
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cmpl #MMU_68040,_mmutype
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jeq Licia040
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#endif
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movl #IC_CLEAR,d0
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movc d0,cacr | invalidate i-cache
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rts
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Licia040:
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#endif
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#if defined(M68040) || defined(M68060)
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.word 0xf498 | cinva ic, clears btc on 060
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rts
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#endif
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/*
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* Invalidate data cache.
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* NOTE: we do not flush 68030 on-chip cache as there are no aliasing
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* problems with DC_WA. The only cases we have to worry about are context
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* switch and TLB changes, both of which are handled "in-line" in resume
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* and TBI*.
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*/
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ENTRY(DCIA)
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__DCIA:
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cmpl #MMU_68040,_mmutype
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jne Ldciax
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.word 0xf478 | cpusha dc
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Ldciax:
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rts
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ENTRY(DCIS)
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__DCIS:
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cmpl #MMU_68040,_mmutype
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jne Ldcisx
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.word 0xf478 | cpusha dc
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nop
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Ldcisx:
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rts
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ENTRY(DCIU)
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__DCIU:
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cmpl #MMU_68040,_mmutype
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jne Ldciux
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.word 0xf478 | cpusha dc
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Ldciux:
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rts
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| Invalid single cache line
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ENTRY(DCIAS)
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__DCIAS:
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cmpl #MMU_68040,_mmutype
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jne Ldciasx
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movl sp@(4),a0
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.word 0xf468 | cpushl dc,a0@
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Ldciasx:
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rts
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#if defined(M68040) || defined(M68060)
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ENTRY(ICPL) /* invalidate instruction physical cache line */
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movl sp@(4),a0 | address
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.word 0xf488 | cinvl ic,a0@
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rts
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ENTRY(ICPP) /* invalidate instruction physical cache page */
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movl sp@(4),a0 | address
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.word 0xf490 | cinvp ic,a0@
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rts
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ENTRY(DCPL) /* invalidate data physical cache line */
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movl sp@(4),a0 | address
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.word 0xf448 | cinvl dc,a0@
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rts
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ENTRY(DCPP) /* invalidate data physical cache page */
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movl sp@(4),a0 | address
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.word 0xf450 | cinvp dc,a0@
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rts
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ENTRY(DCPA) /* invalidate data physical all */
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.word 0xf458 | cinva dc
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rts
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ENTRY(DCFL) /* data cache flush line */
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movl sp@(4),a0 | address
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.word 0xf468 | cpushl dc,a0@
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rts
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ENTRY(DCFP) /* data cache flush page */
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movl sp@(4),a0 | address
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.word 0xf470 | cpushp dc,a0@
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rts
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#endif /* M68040 */
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ENTRY(PCIA)
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#if defined(M68030) || defined(M68030)
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#if defined(M68040) || defined(M68060)
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cmpl #MMU_68040,_mmutype
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jeq Lpcia040
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#endif
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movl #DC_CLEAR,d0
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movc d0,cacr | invalidate on-chip d-cache
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rts
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#endif
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#if defined(M68040) || defined(M68060)
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ENTRY(DCFA)
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Lpcia040:
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.word 0xf478 | cpusha dc
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rts
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#endif
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ENTRY(ecacheon)
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rts
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.70 1999/08/03 21:50:18 is Exp $ */
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/* $NetBSD: pmap.c,v 1.71 1999/09/06 21:50:47 is Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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@ -125,6 +125,9 @@
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#include <machine/pte.h>
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#include <machine/cpu.h>
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#include <machine/vmparam.h>
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#include <m68k/cacheops.h>
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#include <amiga/amiga/memlist.h>
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/*
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* Allocate various and sundry SYSMAPs used in the days of old VM
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@ -1,4 +1,4 @@
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/* $NetBSD: sys_machdep.c,v 1.24 1999/07/08 23:44:57 thorpej Exp $ */
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/* $NetBSD: sys_machdep.c,v 1.25 1999/09/06 21:50:48 is Exp $ */
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/*
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* Copyright (c) 1982, 1986 Regents of the University of California.
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@ -51,6 +51,9 @@
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#include <vm/vm.h>
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#include <machine/cpu.h>
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#include <m68k/cacheops.h>
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#ifdef TRACE
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int nvualarm;
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@ -108,8 +111,6 @@ vdoualarm(arg)
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}
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#endif
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#include <machine/cpu.h>
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/* XXX should be in an include file somewhere */
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#define CC_PURGE 1
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#define CC_FLUSH 2
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@ -1,4 +1,4 @@
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/* $NetBSD: trap.c,v 1.69 1999/03/24 05:50:53 mrg Exp $ */
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/* $NetBSD: trap.c,v 1.70 1999/09/06 21:50:48 is Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -76,6 +76,7 @@
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#include <machine/pte.h>
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#include <m68k/fpe/fpu_emulate.h>
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#include <m68k/cacheops.h>
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#ifdef COMPAT_SUNOS
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#include <compat/sunos/sunos_syscall.h>
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@ -1,4 +1,4 @@
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/* $NetBSD: vm_machdep.c,v 1.48 1999/08/03 21:54:50 is Exp $ */
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/* $NetBSD: vm_machdep.c,v 1.49 1999/09/06 21:50:48 is Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -53,6 +53,7 @@
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#include <m68k/reg.h>
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#include <machine/cpu.h>
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#include <m68k/cacheops.h>
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#include <vm/vm.h>
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#include <sys/user.h>
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@ -1,4 +1,4 @@
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# $NetBSD: files.amiga,v 1.89 1999/07/09 02:32:28 thorpej Exp $
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# $NetBSD: files.amiga,v 1.90 1999/09/06 21:50:47 is Exp $
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# maxpartitions must be first item in files.${ARCH}.newconf
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maxpartitions 16 # NOTE THAT AMIGA IS SPECIAL!
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@ -394,6 +394,8 @@ file arch/amiga/amiga/cc.c
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file arch/amiga/amiga/db_memrw.c ddb
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file arch/amiga/dev/md_root.c memory_disk_hooks
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file arch/m68k/m68k/cacheops.c
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major {md = 15} # Memory disk (for mini-kernel)
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# Compatibility modules
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@ -1,4 +1,4 @@
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/* $NetBSD: siop.c,v 1.41 1999/03/28 19:30:07 is Exp $ */
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/* $NetBSD: siop.c,v 1.42 1999/09/06 21:50:48 is Exp $ */
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/*
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* Copyright (c) 1994 Michael L. Hitch
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@ -56,6 +56,9 @@
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <machine/cpu.h>
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#ifdef __m68k__
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#include <m68k/cacheops.h>
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#endif
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#include <amiga/amiga/custom.h>
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#include <amiga/amiga/isr.h>
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#include <amiga/dev/siopreg.h>
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