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Add an exponential back-off to the loop that tries to lock the

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PCI configuration-access registers, to avoid excessive cacheline
ping-ponging.  Thanks to rmind@ for the tip.
This commit is contained in:
dyoung 2010-04-30 21:05:27 +00:00
parent 66708c492e
commit 327fd4b29c
1 changed files with 16 additions and 4 deletions
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20
sys/arch/x86/pci/pci_machdep.c
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@ -1,4 +1,4 @@
/* $NetBSD: pci_machdep.c,v 1.43 2010/04/28 21:27:14 dyoung Exp $ */
/* $NetBSD: pci_machdep.c,v 1.44 2010/04/30 21:05:27 dyoung Exp $ */
/*-
* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
@ -73,7 +73,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.43 2010/04/28 21:27:14 dyoung Exp $");
__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.44 2010/04/30 21:05:27 dyoung Exp $");
#include <sys/types.h>
#include <sys/param.h>
@ -269,9 +269,21 @@ pci_conf_lock(struct pci_conf_lock *ocl, uint32_t sel)
if (cpuno == cl->cl_cpuno) {
ocl->cl_cpuno = cpuno;
} else {
u_int spins;
ocl->cl_cpuno = 0;
while (atomic_cas_32(&cl->cl_cpuno, 0, cpuno) != 0)
;
spins = SPINLOCK_BACKOFF_MIN;
while (atomic_cas_32(&cl->cl_cpuno, 0, cpuno) != 0) {
SPINLOCK_BACKOFF(spins);
#ifdef LOCKDEBUG
if (SPINLOCK_SPINOUT(spins)) {
panic("%s: cpu %" PRId32
" spun out waiting for cpu %" PRId32,
__func__, cpuno, cl->cl_cpuno);
}
#endif /* LOCKDEBUG */
}
}
/* Only one CPU can be here, so an interlocked atomic_swap(3)