Add Marvell Gigabit Ethernet Controller on SC/SoC.
Will support on ofppc soon. Tested on G4+PegasosII (kiyohara@) G3+PegasosII (phx@)
This commit is contained in:
kiyohara
parent
e9d9dba532
commit
3224e25a97
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@ -1,4 +1,4 @@
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# $NetBSD: files.discovery,v 1.12 2010/05/07 17:06:32 kiyohara Exp $
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# $NetBSD: files.discovery,v 1.13 2010/06/02 06:18:11 kiyohara Exp $
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#
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# Config file and device description for machine-independent support for
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# the Marvell (formerly Galileo Technology) Discovery system controllers.
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@ -62,12 +62,12 @@ file dev/marvell/obio.c obio
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#file dev/marvell/mvsata_mv.c mvsata_gt | mvsata_mbus
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# Gigabit Ethernet Controller Interface
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#define mvgbec { [port = -1], [irq = -1] }
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#device mvgbec: mvgbec
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#attach mvgbec at gt with mvgbec_gt
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#device mvgbe: ether, ifnet, arp, mii
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#attach mvgbe at mvgbec
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#file dev/marvell/if_mvgbe.c mvgbec | mvgbe
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define mvgbec { [port = -1], [irq = -1] }
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device mvgbec: mvgbec
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attach mvgbec at gt with mvgbec_gt
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device mvgbe: ether, ifnet, arp, mii
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attach mvgbe at mvgbec
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file dev/marvell/if_mvgbe.c mvgbec | mvgbe
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# USB 2.0 Interface
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#attach ehci at gt with mvusb_gt
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,419 @@
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/* $NetBSD: mvgbereg.h,v 1.1 2010/06/02 06:18:11 kiyohara Exp $ */
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/*
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* Copyright (c) 2007 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MVGBEREG_H_
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#define _MVGBEREG_H_
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#define MVGBE_SIZE 0x4000
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#define MVGBE_NWINDOW 6
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#define MVGBE_NREMAP 4
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#define MVGBE_PHY_TIMEOUT 10000 /* msec */
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#define MVGBE_RX_CSUM_MIN_BYTE 72
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/*
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* Ethernet Unit Registers
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*/
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/* Ethernet Unit Global Registers */
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#define MVGBE_PHYADDR 0x2000
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#if defined(MV88W8660)
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#define MVGBE_SMI 0x8010
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#else
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#define MVGBE_SMI 0x2004
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#endif
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#define MVGBE_EUDA 0x2008 /* Ethernet Unit Default Address */
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#define MVGBE_EUDID 0x200c /* Ethernet Unit Default ID */
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#define MVGBE_EU 0x2014 /* Ethernet Unit Reserved */
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#define MVGBE_EUIC 0x2080 /* Ethernet Unit Interrupt Cause */
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#define MVGBE_EUIM 0x2084 /* Ethernet Unit Interrupt Mask */
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#define MVGBE_EUEA 0x2094 /* Ethernet Unit Error Address */
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#define MVGBE_EUIAE 0x2098 /* Ethernet Unit Internal Addr Error */
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#define MVGBE_EUPCR 0x20a0 /* EthernetUnit Port Pads Calibration */
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#define MVGBE_EUC 0x20b0 /* Ethernet Unit Control */
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#define MVGBE_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */
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#define MVGBE_S(n) (0x2204 + ((n) << 3)) /* Size */
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#define MVGBE_HA(n) (0x2280 + ((n) << 2)) /* High Address Remap */
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#define MVGBE_BARE 0x2290 /* Base Address Enable */
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#define MVGBE_EPAP 0x2294 /* Ethernet Port Access Protect */
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/* Ethernet Unit Port Registers */
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#define MVGBE_PORTR_BASE 0x2400
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#define MVGBE_PORTR_SIZE 0x400
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#define MVGBE_PXC 0x000 /* Port Configuration */
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#define MVGBE_PXCX 0x004 /* Port Configuration Extend */
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#define MVGBE_MIISP 0x008 /* MII Serial Parameters */
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#define MVGBE_GMIISP 0x00c /* GMII Serial Params */
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#define MVGBE_EVLANE 0x010 /* VLAN EtherType */
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#define MVGBE_MACAL 0x014 /* MAC Address Low */
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#define MVGBE_MACAH 0x018 /* MAC Address High */
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#define MVGBE_SDC 0x01c /* SDMA Configuration */
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#define MVGBE_DSCP(n) (0x020 + ((n) << 2))
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#define MVGBE_PSC 0x03c
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#define MVGBE_VPT2P 0x040 /* VLAN Priority Tag to Priority */
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#define MVGBE_PS 0x044 /* Ethernet Port Status */
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#define MVGBE_TQC 0x048 /* Transmit Queue Command */
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#define MVGBE_MTU 0x058 /* Max Transmit Unit */
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#define MVGBE_IC 0x060 /* Port Interrupt Cause */
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#define MVGBE_ICE 0x064 /* Port Interrupt Cause Extend */
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#define MVGBE_PIM 0x068 /* Port Interrupt Mask */
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#define MVGBE_PEIM 0x06c /* Port Extend Interrupt Mask */
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#define MVGBE_PRFUT 0x070 /* Port Rx FIFO Urgent Threshold */
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#define MVGBE_PTFUT 0x074 /* Port Tx FIFO Urgent Threshold */
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#define MVGBE_PMFS 0x07c /* Port Rx Minimal Frame Size */
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#define MVGBE_PXDFC 0x084 /* Port Rx Discard Frame Counter */
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#define MVGBE_POFC 0x088 /* Port Overrun Frame Counter */
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#define MVGBE_PIAE 0x094 /* Port Internal Address Error */
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#define MVGBE_CRDP(n) (0x20c + ((n) << 4))
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/* Ethernet Current Receive Descriptor Pointers */
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#define MVGBE_RQC 0x280 /* Receive Queue Command */
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#define MVGBE_TCSDP 0x284 /* Tx Current Served Desc Pointer */
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#define MVGBE_TCQDP 0x2c0 /* Tx Current Queue Desc Pointer */
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#define MVGBE_TQTBCOUNT(q) (0x300 + ((q) << 4))
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/* Transmit Queue Token-Bucket Counter */
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#define MVGBE_TQTBCONFIG(q) (0x304 + ((q) << 4))
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/* Transmit Queue Token-Bucket Configuration */
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#define MVGBE_TQAC(q) (0x308 + ((q) << 4))
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/* Transmit Queue Arbiter Configuration */
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#define MVGBE_PORTDAFR_BASE 0x3400
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#define MVGBE_PORTDAFR_SIZE 0x400
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#define MVGBE_NDFSMT 0x40
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#define MVGBE_DFSMT 0x000
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/* Destination Address Filter Special Multicast Table */
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#define MVGBE_NDFOMT 0x40
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#define MVGBE_DFOMT 0x100
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/* Destination Address Filter Other Multicast Table */
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#define MVGBE_NDFUT 0x4
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#define MVGBE_DFUT 0x200
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/* Destination Address Filter Unicast Table */
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/* MAC MIB Counters 0x3000 - 0x307c */
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/* PHY Address (MVGBE_PHYADDR) */
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#define MVGBE_PHYADDR_PHYAD_MASK 0x1f
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#define MVGBE_PHYADDR_PHYAD(port, phy) ((phy) << ((port) * 5))
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/* SMI register fields (MVGBE_SMI) */
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#define MVGBE_SMI_DATA_MASK 0x0000ffff
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#define MVGBE_SMI_PHYAD(phy) (((phy) & 0x1f) << 16)
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#define MVGBE_SMI_REGAD(reg) (((reg) & 0x1f) << 21)
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#define MVGBE_SMI_OPCODE_WRITE (0 << 26)
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#define MVGBE_SMI_OPCODE_READ (1 << 26)
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#define MVGBE_SMI_READVALID (1 << 27)
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#define MVGBE_SMI_BUSY (1 << 28)
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/* Ethernet Unit Default ID (MVGBE_EUDID) */
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#define MVGBE_EUDID_DIDR_MASK 0x0000000f
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#define MVGBE_EUDID_DATTR_MASK 0x00000ff0
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/* Ethernet Unit Reserved (MVGBE_EU) */
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#define MVGBE_EU_FASTMDC (1 << 0)
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#define MVGBE_EU_ACCS (1 << 1)
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/* Ethernet Unit Interrupt Cause (MVGBE_EUIC) */
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#define MVGBE_EUIC_ETHERINTSUM (1 << 0)
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#define MVGBE_EUIC_PARITY (1 << 1)
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#define MVGBE_EUIC_ADDRVIOL (1 << 2)
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#define MVGBE_EUIC_ADDRVNOMATCH (1 << 3)
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#define MVGBE_EUIC_SMIDONE (1 << 4)
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#define MVGBE_EUIC_COUNTWA (1 << 5)
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#define MVGBE_EUIC_INTADDRERR (1 << 7)
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#define MVGBE_EUIC_PORT0DPERR (1 << 9)
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#define MVGBE_EUIC_TOPDPERR (1 << 12)
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/* Ethernet Unit Internal Addr Error (MVGBE_EUIAE) */
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#define MVGBE_EUIAE_INTADDR_MASK 0x000001ff
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/* Ethernet Unit Port Pads Calibration (MVGBE_EUPCR) */
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#define MVGBE_EUPCR_DRVN_MASK 0x0000001f
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#define MVGBE_EUPCR_TUNEEN (1 << 16)
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#define MVGBE_EUPCR_LOCKN_MASK 0x003e0000
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#define MVGBE_EUPCR_OFFSET_MASK 0x1f000000 /* Reserved */
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#define MVGBE_EUPCR_WREN (1 << 31)
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/* Ethernet Unit Control (MVGBE_EUC) */
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#define MVGBE_EUC_PORT0DPPAR (1 << 0)
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#define MVGBE_EUC_TOPDPPAR (1 << 3)
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#define MVGBE_EUC_PORT0PW (1 << 16)
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/* Base Address (MVGBE_BASEADDR) */
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#define MVGBE_BASEADDR_TARGET(target) ((target) & 0xf)
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#define MVGBE_BASEADDR_ATTR(attr) (((attr) & 0xff) << 8)
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#define MVGBE_BASEADDR_BASE(base) ((base) & 0xffff0000)
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/* Size (MVGBE_S) */
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#define MVGBE_S_SIZE(size) (((size) - 1) & 0xffff0000)
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/* Base Address Enable (MVGBE_BARE) */
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#define MVGBE_BARE_EN_MASK ((1 << MVGBE_NWINDOW) - 1)
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#define MVGBE_BARE_EN(win) ((1 << (win)) & MVGBE_BARE_EN_MASK)
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/* Ethernet Port Access Protect (MVGBE_EPAP) */
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#define MVGBE_EPAP_AC_NAC 0x0 /* No access allowed */
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#define MVGBE_EPAP_AC_RO 0x1 /* Read Only */
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#define MVGBE_EPAP_AC_FA 0x3 /* Full access (r/w) */
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#define MVGBE_EPAP_EPAR(win, ac) ((ac) << ((win) * 2))
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/* Port Configuration (MVGBE_PXC) */
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#define MVGBE_PXC_UPM (1 << 0) /* Uni Promisc mode */
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#define MVGBE_PXC_RXQ(q) ((q) << 1)
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#define MVGBE_PXC_RXQ_MASK MVGBE_PXC_RXQ(7)
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#define MVGBE_PXC_RXQARP(q) ((q) << 4)
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#define MVGBE_PXC_RXQARP_MASK MVGBE_PXC_RXQARP(7)
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#define MVGBE_PXC_RB (1 << 7) /* Rej mode of MAC */
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#define MVGBE_PXC_RBIP (1 << 8)
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#define MVGBE_PXC_RBARP (1 << 9)
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#define MVGBE_PXC_AMNOTXES (1 << 12)
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#define MVGBE_PXC_TCPCAPEN (1 << 14)
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#define MVGBE_PXC_UDPCAPEN (1 << 15)
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#define MVGBE_PXC_TCPQ(q) ((q) << 16)
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#define MVGBE_PXC_TCPQ_MASK MVGBE_PXC_TCPQ(7)
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#define MVGBE_PXC_UDPQ(q) ((q) << 19)
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#define MVGBE_PXC_UDPQ_MASK MVGBE_PXC_UDPQ(7)
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#define MVGBE_PXC_BPDUQ(q) ((q) << 22)
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#define MVGBE_PXC_BPDUQ_MASK MVGBE_PXC_BPDUQ(7)
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#define MVGBE_PXC_RXCS (1 << 25)
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/* Port Configuration Extend (MVGBE_PXCX) */
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#define MVGBE_PXCX_SPAN (1 << 1)
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/* MII Serial Parameters (MVGBE_MIISP) */
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#define MVGBE_MIISP_JAMLENGTH_12KBIT 0x00000000
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#define MVGBE_MIISP_JAMLENGTH_24KBIT 0x00000001
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#define MVGBE_MIISP_JAMLENGTH_32KBIT 0x00000002
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#define MVGBE_MIISP_JAMLENGTH_48KBIT 0x00000003
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#define MVGBE_MIISP_JAMIPG(x) (((x) & 0x7c) << 0)
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#define MVGBE_MIISP_IPGJAMTODATA(x) (((x) & 0x7c) << 5)
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#define MVGBE_MIISP_IPGDATA(x) (((x) & 0x7c) << 10)
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#define MVGBE_MIISP_DATABLIND(x) (((x) & 0x1f) << 17)
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/* GMII Serial Parameters (MVGBE_GMIISP) */
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#define MVGBE_GMIISP_IPGDATA(x) (((x) >> 4) & 0x7)
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/* SDMA Configuration (MVGBE_SDC) */
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#define MVGBE_SDC_RIFB (1 << 0)
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#define MVGBE_SDC_RXBSZ(x) ((x) << 1)
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#define MVGBE_SDC_RXBSZ_MASK MVGBE_SDC_RXBSZ(7)
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#define MVGBE_SDC_RXBSZ_1_64BITWORDS MVGBE_SDC_RXBSZ(0)
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#define MVGBE_SDC_RXBSZ_2_64BITWORDS MVGBE_SDC_RXBSZ(1)
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#define MVGBE_SDC_RXBSZ_4_64BITWORDS MVGBE_SDC_RXBSZ(2)
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#define MVGBE_SDC_RXBSZ_8_64BITWORDS MVGBE_SDC_RXBSZ(3)
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#define MVGBE_SDC_RXBSZ_16_64BITWORDS MVGBE_SDC_RXBSZ(4)
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#define MVGBE_SDC_BLMR (1 << 4)
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#define MVGBE_SDC_BLMT (1 << 5)
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#define MVGBE_SDC_SWAPMODE (1 << 6)
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#define MVGBE_SDC_IPGINTRX(n) ((n) << 8)
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#define MVGBE_SDC_IPGINTRX_MASK MVGBE_SDC_IPGINTRX(0x3fff)
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#define MVGBE_SDC_TXBSZ(x) ((x) << 22)
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#define MVGBE_SDC_TXBSZ_MASK MVGBE_SDC_TXBSZ(7)
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#define MVGBE_SDC_TXBSZ_1_64BITWORDS MVGBE_SDC_TXBSZ(0)
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#define MVGBE_SDC_TXBSZ_2_64BITWORDS MVGBE_SDC_TXBSZ(1)
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#define MVGBE_SDC_TXBSZ_4_64BITWORDS MVGBE_SDC_TXBSZ(2)
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#define MVGBE_SDC_TXBSZ_8_64BITWORDS MVGBE_SDC_TXBSZ(3)
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#define MVGBE_SDC_TXBSZ_16_64BITWORDS MVGBE_SDC_TXBSZ(4)
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/* Port Serial Control (MVGBE_PSC) */
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#define MVGBE_PSC_PORTEN (1 << 0)
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#define MVGBE_PSC_FLP (1 << 1) /* Force_Link_Pass */
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#define MVGBE_PSC_ANDUPLEX (1 << 2) /* auto nego */
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#define MVGBE_PSC_ANFC (1 << 3)
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#define MVGBE_PSC_PAUSEADV (1 << 4)
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#define MVGBE_PSC_FFCMODE (1 << 5) /* Force FC */
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#define MVGBE_PSC_FBPMODE (1 << 7) /* Back pressure */
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#define MVGBE_PSC_RESERVED (1 << 9) /* Must be set to 1 */
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#define MVGBE_PSC_FLFAIL (1 << 10) /* Force Link Fail */
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#define MVGBE_PSC_ANSPEED (1 << 13)
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#define MVGBE_PSC_DTEADVERT (1 << 14)
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#define MVGBE_PSC_MRU(x) ((x) << 17)
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#define MVGBE_PSC_MRU_MASK MVGBE_PSC_MRU(7)
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#define MVGBE_PSC_MRU_1518 0
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#define MVGBE_PSC_MRU_1522 1
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#define MVGBE_PSC_MRU_1552 2
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#define MVGBE_PSC_MRU_9022 3
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#define MVGBE_PSC_MRU_9192 4
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#define MVGBE_PSC_MRU_9700 5
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#define MVGBE_PSC_SETFULLDX (1 << 21)
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#define MVGBE_PSC_SETFCEN (1 << 22)
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#define MVGBE_PSC_SETGMIISPEED (1 << 23)
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#define MVGBE_PSC_SETMIISPEED (1 << 24)
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/* Ethernet Port Status (MVGBE_PS) */
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#define MVGBE_PS_LINKUP (1 << 1)
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#define MVGBE_PS_FULLDX (1 << 2)
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#define MVGBE_PS_ENFC (1 << 3)
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#define MVGBE_PS_GMIISPEED (1 << 4)
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#define MVGBE_PS_MIISPEED (1 << 5)
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#define MVGBE_PS_TXINPROG (1 << 7)
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#define MVGBE_PS_TXFIFOEMP (1 << 10) /* FIFO Empty */
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/* Transmit Queue Command (MVGBE_TQC) */
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#define MVGBE_TQC_ENQ (1 << 0) /* Enable Q */
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#define MVGBE_TQC_DISQ (1 << 8) /* Disable Q */
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/* Port Interrupt Cause (MVGBE_IC) */
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#define MVGBE_IC_RXBUF (1 << 0)
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#define MVGBE_IC_EXTEND (1 << 1)
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#define MVGBE_IC_RXBUFQ_MASK (0xff << 2)
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#define MVGBE_IC_RXBUFQ(q) (1 << ((q) + 2))
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#define MVGBE_IC_RXERROR (1 << 10)
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#define MVGBE_IC_RXERRQ_MASK (0xff << 11)
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#define MVGBE_IC_RXERRQ(q) (1 << ((q) + 11))
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#define MVGBE_IC_TXEND (1 << 19)
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#define MVGBE_IC_ETHERINTSUM (1 << 31)
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/* Port Interrupt Cause Extend (MVGBE_ICE) */
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#define MVGBE_ICE_TXBUF (1 << 0)
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#define MVGBE_ICE_TXERR (1 << 8)
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#define MVGBE_ICE_PHYSTC (1 << 16)
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#define MVGBE_ICE_RXOVR (1 << 18)
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#define MVGBE_ICE_TXUDR (1 << 19)
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#define MVGBE_ICE_LINKCHG (1 << 20)
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#define MVGBE_ICE_INTADDRERR (1 << 23)
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#define MVGBE_ICE_ETHERINTSUM (1 << 31)
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/* Port Rx Minimal Frame Size (MVGBE_PMFS) */
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#define MVGBE_PMFS_RXMFS(rxmfs) (((rxmfs) - 40) & 0x7c)
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/* RxMFS = 40,44,48,52,56,60,64 bytes */
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/* Receive Queue Command (MVGBE_RQC) */
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#define MVGBE_RQC_ENQ_MASK (0xff << 0) /* Enable Q */
|
||||
#define MVGBE_RQC_ENQ(n) (1 << (0 + (n)))
|
||||
#define MVGBE_RQC_DISQ_MASK (0xff << 8) /* Disable Q */
|
||||
#define MVGBE_RQC_DISQ(n) (1 << (8 + (n)))
|
||||
#define MVGBE_RQC_DISQ_DISABLE(q) ((q) << 8)
|
||||
|
||||
/* Destination Address Filter Registers (MVGBE_DF{SM,OM,U}T) */
|
||||
#define MVGBE_DF(n, x) ((x) << (8 * (n)))
|
||||
#define MVGBE_DF_PASS (1 << 0)
|
||||
#define MVGBE_DF_QUEUE(q) ((q) << 1)
|
||||
#define MVGBE_DF_QUEUE_MASK ((7) << 1)
|
||||
|
||||
|
||||
#define MVGBE_MRU 9700 /* The Maximal Receive Packet Size */
|
||||
|
||||
#define MVGBE_BUF_ALIGN 8
|
||||
#define MVGBE_BUF_MASK (MVGBE_BUF_ALIGN - 1)
|
||||
#define MVGBE_HWHEADER_SIZE 2
|
||||
|
||||
|
||||
/*
|
||||
* DMA descriptors
|
||||
* It is 32byte alignment.
|
||||
*/
|
||||
struct mvgbe_tx_desc {
|
||||
#if BYTE_ORDER == BIG_ENDIAN
|
||||
uint16_t bytecnt; /* Descriptor buffer byte count */
|
||||
uint16_t l4ichk; /* CPU provided TCP Checksum */
|
||||
uint32_t cmdsts; /* Descriptor command status */
|
||||
uint32_t nextdescptr; /* Next descriptor pointer */
|
||||
uint32_t bufptr; /* Descriptor buffer pointer */
|
||||
#else /* LITTLE_ENDIAN */
|
||||
uint32_t cmdsts; /* Descriptor command status */
|
||||
uint16_t l4ichk; /* CPU provided TCP Checksum */
|
||||
uint16_t bytecnt; /* Descriptor buffer byte count */
|
||||
uint32_t bufptr; /* Descriptor buffer pointer */
|
||||
uint32_t nextdescptr; /* Next descriptor pointer */
|
||||
#endif
|
||||
u_long returninfo; /* User resource return information */
|
||||
uint8_t *alignbufptr; /* Pointer to 8 byte aligned buffer */
|
||||
|
||||
uint32_t padding[2]; /* XXXX: required */
|
||||
} __packed;
|
||||
|
||||
struct mvgbe_rx_desc {
|
||||
#if BYTE_ORDER == BIG_ENDIAN
|
||||
uint16_t bytecnt; /* Descriptor buffer byte count */
|
||||
uint16_t bufsize; /* Buffer size */
|
||||
uint32_t cmdsts; /* Descriptor command status */
|
||||
uint32_t nextdescptr; /* Next descriptor pointer */
|
||||
uint32_t bufptr; /* Descriptor buffer pointer */
|
||||
#else /* LITTLE_ENDIAN */
|
||||
uint32_t cmdsts; /* Descriptor command status */
|
||||
uint16_t bufsize; /* Buffer size */
|
||||
uint16_t bytecnt; /* Descriptor buffer byte count */
|
||||
uint32_t bufptr; /* Descriptor buffer pointer */
|
||||
uint32_t nextdescptr; /* Next descriptor pointer */
|
||||
#endif
|
||||
u_long returninfo; /* User resource return information */
|
||||
|
||||
uint32_t padding[3]; /* XXXX: required */
|
||||
} __packed;
|
||||
|
||||
#define MVGBE_ERROR_SUMMARY (1 << 0)
|
||||
#define MVGBE_BUFFER_OWNED_MASK (1 << 31)
|
||||
#define MVGBE_BUFFER_OWNED_BY_HOST (0 << 31)
|
||||
#define MVGBE_BUFFER_OWNED_BY_DMA (1 << 31)
|
||||
|
||||
#define MVGBE_TX_ERROR_CODE_MASK (3 << 1)
|
||||
#define MVGBE_TX_LATE_COLLISION_ERROR (0 << 1)
|
||||
#define MVGBE_TX_UNDERRUN_ERROR (1 << 1)
|
||||
#define MVGBE_TX_EXCESSIVE_COLLISION_ERRO (2 << 1)
|
||||
#define MVGBE_TX_LLC_SNAP_FORMAT (1 << 9)
|
||||
#define MVGBE_TX_IP_NO_FRAG (1 << 10)
|
||||
#define MVGBE_TX_IP_HEADER_LEN(len) ((len) << 11)
|
||||
#define MVGBE_TX_VLAN_TAGGED_FRAME (1 << 15)
|
||||
#define MVGBE_TX_L4_TYPE_TCP (0 << 16)
|
||||
#define MVGBE_TX_L4_TYPE_UDP (1 << 16)
|
||||
#define MVGBE_TX_GENERATE_L4_CHKSUM (1 << 17)
|
||||
#define MVGBE_TX_GENERATE_IP_CHKSUM (1 << 18)
|
||||
#define MVGBE_TX_ZERO_PADDING (1 << 19)
|
||||
#define MVGBE_TX_LAST_DESC (1 << 20)
|
||||
#define MVGBE_TX_FIRST_DESC (1 << 21)
|
||||
#define MVGBE_TX_GENERATE_CRC (1 << 22)
|
||||
#define MVGBE_TX_ENABLE_INTERRUPT (1 << 23)
|
||||
#define MVGBE_TX_AUTO_MODE (1 << 30)
|
||||
|
||||
#define MVGBE_RX_ERROR_CODE_MASK (3 << 1)
|
||||
#define MVGBE_RX_CRC_ERROR (0 << 1)
|
||||
#define MVGBE_RX_OVERRUN_ERROR (1 << 1)
|
||||
#define MVGBE_RX_MAX_FRAME_LEN_ERROR (2 << 1)
|
||||
#define MVGBE_RX_RESOURCE_ERROR (3 << 1)
|
||||
#define MVGBE_RX_L4_CHECKSUM_MASK (0xffff << 3)
|
||||
#define MVGBE_RX_VLAN_TAGGED_FRAME (1 << 19)
|
||||
#define MVGBE_RX_BPDU_FRAME (1 << 20)
|
||||
#define MVGBE_RX_L4_TYPE_MASK (3 << 21)
|
||||
#define MVGBE_RX_L4_TYPE_TCP (0 << 21)
|
||||
#define MVGBE_RX_L4_TYPE_UDP (1 << 21)
|
||||
#define MVGBE_RX_L4_TYPE_OTHER (2 << 21)
|
||||
#define MVGBE_RX_NOT_LLC_SNAP_FORMAT (1 << 23)
|
||||
#define MVGBE_RX_IP_FRAME_TYPE (1 << 24)
|
||||
#define MVGBE_RX_IP_HEADER_OK (1 << 25)
|
||||
#define MVGBE_RX_LAST_DESC (1 << 26)
|
||||
#define MVGBE_RX_FIRST_DESC (1 << 27)
|
||||
#define MVGBE_RX_UNKNOWN_DA (1 << 28)
|
||||
#define MVGBE_RX_ENABLE_INTERRUPT (1 << 29)
|
||||
#define MVGBE_RX_L4_CHECKSUM (1 << 30)
|
||||
|
||||
#endif /* _MVGEREG_H_ */
|
||||
Loading…
Reference in New Issue