Some initial MULTIPROCESSOR spin code. Doesn't work yet.
This commit is contained in:
matt
parent
bd38a7a8c6
commit
3162fd7666
@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.13 2011/06/25 00:07:10 matt Exp $ */
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/* $NetBSD: machdep.c,v 1.14 2011/06/29 05:53:05 matt Exp $ */
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/*-
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* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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@ -66,7 +66,7 @@ __KERNEL_RCSID(0, "$NetSBD$");
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#include <prop/proplib.h>
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#include <machine/stdarg.h>
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#include <powerpc/stdarg.h>
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#include <dev/cons.h>
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@ -77,6 +77,7 @@ __KERNEL_RCSID(0, "$NetSBD$");
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#include <net/if_media.h>
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#include <dev/mii/miivar.h>
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#include <powerpc/cpuset.h>
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#include <powerpc/pcb.h>
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#include <powerpc/spr.h>
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#include <powerpc/booke/spr.h>
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@ -663,27 +664,10 @@ e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg)
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}
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static void
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e500_cpu_attach(device_t self, u_int instance)
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cpu_print_info(struct cpu_info *ci)
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{
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struct cpu_info * const ci = &cpu_info[instance - (instance > 0)];
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if (instance > 1) {
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#ifdef MULTIPROCESSOR
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#error still needs to be written
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ci->ci_idepth = -1;
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cpu_probe_cache();
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#else
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aprint_error_dev(self, "disabled (uniprocessor kernel)\n");
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return;
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#endif
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}
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self->dv_private = ci;
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ci->ci_cpuid = instance - (instance > 0);
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ci->ci_dev = self;
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//ci->ci_idlespin = cpu_idlespin;
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uint64_t freq = board_info_get_number("processor-frequency");
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device_t self = ci->ci_dev;
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char freqbuf[10];
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if (freq >= 999500000) {
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@ -736,12 +720,238 @@ e500_cpu_attach(device_t self, u_int instance)
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e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG));
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e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG));
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}
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#ifdef MULTIPROCESSOR
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static void
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e500_cpu_spinup(device_t self, struct cpu_info *ci)
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{
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uintptr_t spinup_table_addr = board_info_get_number("mp-spin-up-table");
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struct pglist splist;
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if (spinup_table_addr == 0) {
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aprint_error_dev(self, "hatch failed (no spin-up table)");
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return;
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}
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struct uboot_spinup_entry * const e = (void *)spinup_table_addr;
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volatile struct cpu_hatch_data * const h = &cpu_hatch_data;
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const size_t id = cpu_index(ci);
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volatile __cpuset_t * const hatchlings = &cpuset_info.cpus_hatched;
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if (h->hatch_sp == 0) {
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int error = uvm_pglistalloc(PAGE_SIZE, PAGE_SIZE,
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64*1024*1024, PAGE_SIZE, 0, &splist, 1, 1);
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if (error) {
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aprint_error_dev(self,
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"unable to allocate hatch stack\n");
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return;
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}
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h->hatch_sp = VM_PAGE_TO_PHYS(TAILQ_FIRST(&splist))
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+ PAGE_SIZE - CALLFRAMELEN;
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}
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for (size_t i = 1; e[i].entry_pir != 0; i++) {
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printf("%s: cpu%u: entry#%zu(%p): pir=%u\n",
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__func__, ci->ci_cpuid, i, &e[i], e[i].entry_pir);
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if (e[i].entry_pir == ci->ci_cpuid) {
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ci->ci_curlwp = ci->ci_data.cpu_idlelwp;
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ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp);
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ci->ci_curpm = pmap_kernel();
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ci->ci_lasttb = cpu_info[0].ci_lasttb;
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ci->ci_data.cpu_cc_freq =
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cpu_info[0].ci_data.cpu_cc_freq;
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h->hatch_self = self;
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h->hatch_ci = ci;
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h->hatch_running = -1;
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h->hatch_pir = e[i].entry_pir;
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h->hatch_hid0 = mfspr(SPR_HID0);
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KASSERT(h->hatch_sp != 0);
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/*
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* Get new timebase. We don't want to deal with
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* timebase crossing a 32-bit boundary so make sure
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* that we have enough headroom to do the timebase
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* synchronization.
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*/
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#define TBSYNC_SLOP 2000
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uint32_t tbl;
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uint32_t tbu;
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do {
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tbu = mfspr(SPR_RTBU);
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tbl = mfspr(SPR_RTBL) + TBSYNC_SLOP;
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} while (tbl < TBSYNC_SLOP);
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h->hatch_tbu = tbu;
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h->hatch_tbl = tbl;
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__asm("sync;isync");
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dcache_wbinv((vaddr_t)h, sizeof(*h));
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#if 1
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/*
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* And here we go...
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*/
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e[i].entry_addr_lower =
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(uint32_t)e500_spinup_trampoline;
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dcache_wbinv((vaddr_t)&e[i], sizeof(e[i]));
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__asm __volatile("sync;isync");
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__insn_barrier();
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for (u_int timo = 0; timo++ < 10000; ) {
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dcache_inv((vaddr_t)&e[i], sizeof(e[i]));
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if (e[i].entry_addr_lower == 3) {
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printf(
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"%s: cpu%u started in %u spins\n",
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__func__, cpu_index(ci), timo);
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break;
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}
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}
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for (u_int timo = 0; timo++ < 10000; ) {
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dcache_inv((vaddr_t)h, sizeof(*h));
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if (h->hatch_running == 0) {
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printf(
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"%s: cpu%u cracked in %u spins: (running=%d)\n",
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__func__, cpu_index(ci),
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timo, h->hatch_running);
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break;
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}
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}
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if (h->hatch_running == -1) {
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aprint_error_dev(self,
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"hatch failed (timeout): running=%d"
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", entry=%#x\n",
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h->hatch_running, e[i].entry_addr_lower);
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goto out;
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}
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#endif
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/*
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* First then we do is to synchronize timebases.
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* TBSYNC_SLOP*16 should be more than enough
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* instructions.
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*/
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while (tbl != mftbl())
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continue;
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h->hatch_running = 1;
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dcache_wbinv((vaddr_t)h, sizeof(*h));
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__asm("sync;isync");
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__insn_barrier();
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for (u_int timo = 10000; timo-- > 0; ) {
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dcache_inv((vaddr_t)h, sizeof(*h));
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if (h->hatch_running > 1)
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break;
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}
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if (h->hatch_running == 1) {
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printf(
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"%s: tb sync failed: offset from %"PRId64"=%"PRId64" (running=%d)\n",
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__func__,
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((int64_t)tbu << 32) + tbl,
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(int64_t)
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(((uint64_t)h->hatch_tbu << 32)
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+ (uint64_t)h->hatch_tbl),
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h->hatch_running);
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goto out;
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}
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printf(
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"%s: tb synced: offset=%"PRId64" (running=%d)\n",
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__func__,
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(int64_t)
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(((uint64_t)h->hatch_tbu << 32)
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+ (uint64_t)h->hatch_tbl),
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h->hatch_running);
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/*
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* Now we wait for the hatching to complete. 10ms
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* should be long enough.
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*/
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for (u_int timo = 10000; timo-- > 0; ) {
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if (CPUSET_HAS_P(*hatchlings, id)) {
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aprint_normal_dev(self,
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"hatch successful (%u spins, "
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"timebase adjusted by %"PRId64")\n",
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10000 - timo,
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(int64_t)
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(((uint64_t)h->hatch_tbu << 32)
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+ (uint64_t)h->hatch_tbl));
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goto out;
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}
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DELAY(1);
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}
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aprint_error_dev(self,
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"hatch failed (timeout): running=%u\n",
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h->hatch_running);
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goto out;
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}
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}
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aprint_error_dev(self, "hatch failed (no spin-up entry for PIR %u)",
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ci->ci_cpuid);
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out:
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if (h->hatch_sp == 0)
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uvm_pglistfree(&splist);
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}
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#endif
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void
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e500_cpu_hatch(struct cpu_info *ci)
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{
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mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE);
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/*
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* Make sure interrupts are blocked.
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*/
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cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */
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intr_cpu_hatch(ci);
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cpu_print_info(ci);
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/*
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*/
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}
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static void
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e500_cpu_attach(device_t self, u_int instance)
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{
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struct cpu_info * const ci = &cpu_info[instance - (instance > 0)];
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if (instance > 1) {
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#if defined(MULTIPROCESSOR)
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ci->ci_idepth = -1;
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self->dv_private = ci;
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ci->ci_cpuid = instance - (instance > 0);
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ci->ci_dev = self;
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ci->ci_tlb_info = cpu_info[0].ci_tlb_info;
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mi_cpu_attach(ci);
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intr_cpu_attach(ci);
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cpu_evcnt_attach(ci);
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e500_cpu_spinup(self, ci);
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return;
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#else
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aprint_error_dev(self, "disabled (uniprocessor kernel)\n");
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return;
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#endif
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}
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self->dv_private = ci;
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ci->ci_cpuid = instance - (instance > 0);
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ci->ci_dev = self;
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intr_cpu_attach(ci);
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cpu_evcnt_attach(ci);
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if (ci == curcpu())
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intr_cpu_hatch(ci);
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KASSERT(ci == curcpu());
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intr_cpu_hatch(ci);
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cpu_print_info(ci);
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}
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void
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@ -900,7 +1110,9 @@ initppc(vaddr_t startkernel, vaddr_t endkernel,
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* Initialize exception vectors and interrupts
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*/
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exception_init(&e500_intrsw);
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printf(" exception_init=%p", &e500_intrsw);
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mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR));
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/*
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@ -1117,9 +1329,11 @@ cpu_startup(void)
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break;
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}
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}
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if (!found)
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if (!found) {
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printf("Found MP boot page @ %#"PRIxPADDR
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" with missing U-boot signature!\n", boot_page);
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board_info_add_number("mp-spin-up-table", 0);
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}
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}
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board_info_add_number("l2-cache-size", l2siz);
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board_info_add_number("l2-cache-line-size", 32);
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