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These are replaced by drivers in <sys/dev/sbus>.

This commit is contained in:
pk 1998-09-05 17:46:33 +00:00
parent 5b005d9e2a
commit 315ac1f6f7
6 changed files with 0 additions and 1677 deletions
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713
sys/arch/sparc64/dev/dma.c
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@ -1,713 +0,0 @@
/* $NetBSD: dma.c,v 1.5 1998/09/05 16:50:37 pk Exp $ */
/*
* Copyright (c) 1994 Paul Kranenburg. All rights reserved.
* Copyright (c) 1994 Peter Galbavy. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Peter Galbavy.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/errno.h>
#include <sys/ioctl.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/buf.h>
#include <sys/proc.h>
#include <sys/user.h>
#include <vm/vm.h>
#include <machine/bus.h>
#include <machine/autoconf.h>
#include <machine/cpu.h>
/* #include <sparc/sparc/cpuvar.h> */
#include <dev/scsipi/scsi_all.h>
#include <dev/scsipi/scsipi_all.h>
#include <dev/scsipi/scsiconf.h>
#include <dev/ic/ncr53c9xreg.h>
#include <dev/ic/ncr53c9xvar.h>
#include <dev/sbus/sbusvar.h>
#include <sparc64/dev/dmareg.h>
#include <sparc64/dev/dmavar.h>
#include <sparc64/dev/espvar.h>
int dmamatch_sbus __P((struct device *, struct cfdata *, void *));
void dmaattach_sbus __P((struct device *, struct device *, void *));
int dmamatch_obio __P((struct device *, struct cfdata *, void *));
void dmaattach_obio __P((struct device *, struct device *, void *));
void dma_identify __P((struct dma_softc *));
int dmaprint __P((void *, const char *));
void dma_reset __P((struct dma_softc *, int));
void espdma_reset __P((struct dma_softc *));
void ledma_reset __P((struct dma_softc *));
void dma_enintr __P((struct dma_softc *));
int dma_isintr __P((struct dma_softc *));
int espdmaintr __P((void *));
int ledmaintr __P((void *));
int dma_setup __P((struct dma_softc *, caddr_t *, size_t *,
int, size_t *));
void dma_go __P((struct dma_softc *));
void *dmabus_intr_establish __P((
bus_space_tag_t,
int, /*level*/
int, /*flags*/
int (*) __P((void *)), /*handler*/
void *)); /*handler arg*/
static bus_space_tag_t dma_alloc_bustag __P((struct dma_softc *sc));
struct cfattach dma_ca = {
sizeof(struct dma_softc), dmamatch_sbus, dmaattach_sbus
};
struct cfattach ledma_ca = {
sizeof(struct dma_softc), dmamatch_sbus, dmaattach_sbus
};
struct cfattach dma_obio_ca = {
sizeof(struct dma_softc), dmamatch_obio, dmaattach_obio
};
int
dmaprint(aux, busname)
void *aux;
const char *busname;
{
struct sbus_attach_args *sa = aux;
bus_space_tag_t t = sa->sa_bustag;
struct dma_softc *sc = t->cookie;
sa->sa_bustag = sc->sc_bustag; /* XXX */
sbus_print(aux, busname); /* XXX */
sa->sa_bustag = t; /* XXX */
return (UNCONF);
}
int
dmamatch_sbus(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct sbus_attach_args *sa = aux;
return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0 ||
strcmp("espdma", sa->sa_name) == 0 ||
strcmp("fas", sa->sa_name) == 0);
}
int
dmamatch_obio(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
union obio_attach_args *uoba = aux;
struct obio4_attach_args *oba;
if (uoba->uoba_isobio4 == 0)
return (0);
oba = &uoba->uoba_oba4;
return (bus_space_probe(oba->oba_bustag, 0,
oba->oba_paddr,
4, /* probe size */
0, /* offset */
0, /* flags */
NULL, NULL));
}
void
dmaattach_sbus(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct sbus_attach_args *sa = aux;
struct dma_softc *sc = (void *)self;
bus_space_handle_t bh;
struct bootpath *bp;
bus_space_tag_t sbt;
int sbusburst;
int node;
sc->sc_bustag = sa->sa_bustag;
sc->sc_dmatag = sa->sa_dmatag;
/* Map registers */
if (sa->sa_promvaddrs != 0)
sc->sc_regs = (struct dma_regs *)sa->sa_promvaddrs[0];
else {
if (sbus_bus_map(sa->sa_bustag,
sa->sa_slot,
sa->sa_offset,
sizeof(struct dma_regs),
0, 0, &bh) != 0) {
printf("dmaattach_sbus: cannot map registers\n");
return;
}
sc->sc_regs = (struct dma_regs *)bh;
}
/*
* Get transfer burst size from PROM and plug it into the
* controller registers. This is needed on the Sun4m; do
* others need it too?
*/
sbusburst = ((struct sbus_softc *)parent)->sc_burst;
if (sbusburst == 0)
sbusburst = SBUS_BURST_32 - 1; /* 1->16 */
sc->sc_burst = getpropint(sa->sa_node, "burst-sizes", -1);
if (sc->sc_burst == -1)
/* take SBus burst sizes */
sc->sc_burst = sbusburst;
/* Clamp at parent's burst sizes */
sc->sc_burst &= sbusburst;
if (sc->sc_dev.dv_cfdata->cf_attach == &ledma_ca) {
char *cabletype;
/*
* Check to see which cable type is currently active and set the
* appropriate bit in the ledma csr so that it gets used. If we
* didn't netboot, the PROM won't have the "cable-selection"
* property; default to TP and then the user can change it via
* a "media" option to ifconfig.
*/
cabletype = getpropstring(sa->sa_node, "cable-selection");
if (strcmp(cabletype, "tpe") == 0) {
sc->sc_regs->csr |= DE_AUI_TP;
} else if (strcmp(cabletype, "aui") == 0) {
sc->sc_regs->csr &= ~DE_AUI_TP;
} else {
/* assume TP if nothing there */
sc->sc_regs->csr |= DE_AUI_TP;
}
delay(20000); /* manual says we need 20ms delay */
}
/* Propagate bootpath */
bp = NULL;
if (sa->sa_bp != NULL) {
char *bpname = sa->sa_bp->name;
if (strcmp(bpname, "espdma") == 0)
/* We call everything "dma" */
bpname = "dma";
if (strcmp(bpname, self->dv_cfdata->cf_driver->cd_name) == 0)
bp = sa->sa_bp + 1;
}
/* Allocate a dmamap */
bus_dmamap_create(sc->sc_dmatag, 16*1024*1024, 1, 16*1024*1024,
0, BUS_DMA_WAITOK, &sc->sc_dmamap);
sbus_establish(&sc->sc_sd, &sc->sc_dev);
sbt = dma_alloc_bustag(sc);
dma_identify(sc);
/* Attach children */
for (node = firstchild(sa->sa_node); node; node = nextsibling(node)) {
struct sbus_attach_args sa;
sbus_setup_attach_args((struct sbus_softc *)parent,
sbt, sc->sc_dmatag, node, bp, &sa);
(void) config_found(&sc->sc_dev, (void *)&sa, dmaprint);
sbus_destroy_attach_args(&sa);
}
}
void
dmaattach_obio(parent, self, aux)
struct device *parent, *self;
void *aux;
{
union obio_attach_args *uoba = aux;
struct obio4_attach_args *oba = &uoba->uoba_oba4;
struct dma_softc *sc = (void *)self;
bus_space_handle_t bh;
sc->sc_bustag = oba->oba_bustag;
sc->sc_dmatag = oba->oba_dmatag;
if (obio_bus_map(oba->oba_bustag, oba->oba_paddr,
0, sizeof(struct dma_regs),
0, 0,
&bh) != 0) {
printf("dmaattach_obio: cannot map registers\n");
return;
}
sc->sc_regs = (struct dma_regs *)bh;
dma_identify(sc);
}
/*
* Attach all the sub-devices we can find
*/
void
dma_identify(sc)
struct dma_softc *sc;
{
printf(": rev ");
sc->sc_rev = sc->sc_regs->csr & D_DEV_ID;
switch (sc->sc_rev) {
case DMAREV_0:
printf("0");
break;
case DMAREV_ESC:
printf("esc");
break;
case DMAREV_1:
printf("1");
break;
case DMAREV_PLUS:
printf("1+");
break;
case DMAREV_2:
printf("2");
break;
default:
printf("unknown (0x%x)", sc->sc_rev);
}
printf("\n");
/* indirect functions */
if (sc->sc_dev.dv_cfdata->cf_attach == &ledma_ca) {
sc->reset = ledma_reset;
sc->intr = ledmaintr;
} else {
sc->reset = espdma_reset;
sc->intr = espdmaintr;
}
sc->enintr = dma_enintr;
sc->isintr = dma_isintr;
sc->setup = dma_setup;
sc->go = dma_go;
}
void *
dmabus_intr_establish(t, level, flags, handler, arg)
bus_space_tag_t t;
int level;
int flags;
int (*handler) __P((void *));
void *arg;
{
struct dma_softc *sc = t->cookie;
if (sc->intr == ledmaintr) { /* XXX - for now; do esp later */
sc->sc_intrchain = handler;
sc->sc_intrchainarg = arg;
handler = ledmaintr;
arg = sc;
}
return (bus_intr_establish(sc->sc_bustag, level, flags, handler, arg));
}
#define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \
int count = 500000; \
while ((COND) && --count > 0) DELAY(1); \
if (count == 0) { \
printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \
(SC)->sc_regs->csr); \
if (DONTPANIC) \
printf(MSG); \
else \
panic(MSG); \
} \
} while (0)
#define DMA_DRAIN(sc, dontpanic) do { \
/* \
* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
* and "drain" bits while it is still thinking about a \
* request. \
* other revs: D_R_PEND bit reads as 0 \
*/ \
DMAWAIT(sc, sc->sc_regs->csr & D_R_PEND, "R_PEND", dontpanic); \
/* \
* Select drain bit based on revision \
* also clears errors and D_TC flag \
*/ \
if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \
DMACSR(sc) |= D_DRAIN; \
else \
DMACSR(sc) |= D_INVALIDATE; \
/* \
* Wait for draining to finish \
* rev0 & rev1 call this PACKCNT \
*/ \
DMAWAIT(sc, sc->sc_regs->csr & D_DRAINING, "DRAINING", dontpanic);\
} while(0)
#define DMA_FLUSH(sc, dontpanic) do { \
int csr; \
/* \
* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
* and "drain" bits while it is still thinking about a \
* request. \
* other revs: D_R_PEND bit reads as 0 \
*/ \
DMAWAIT(sc, sc->sc_regs->csr & D_R_PEND, "R_PEND", dontpanic); \
csr = DMACSR(sc); \
csr &= ~(D_WRITE|D_EN_DMA); \
csr |= D_INVALIDATE; \
DMACSR(sc) = csr; \
} while(0)
void
dma_reset(sc, isledma)
struct dma_softc *sc;
int isledma;
{
DMA_FLUSH(sc, 1);
DMACSR(sc) |= D_RESET; /* reset DMA */
DELAY(200); /* what should this be ? */
/*DMAWAIT1(sc); why was this here? */
DMACSR(sc) &= ~D_RESET; /* de-assert reset line */
DMACSR(sc) |= D_INT_EN; /* enable interrupts */
if (sc->sc_rev > DMAREV_1 && isledma == 0)
DMACSR(sc) |= D_FASTER;
switch (sc->sc_rev) {
case DMAREV_2:
sc->sc_regs->csr &= ~D_BURST_SIZE; /* must clear first */
if (sc->sc_burst & SBUS_BURST_32) {
DMACSR(sc) |= D_BURST_32;
} else if (sc->sc_burst & SBUS_BURST_16) {
DMACSR(sc) |= D_BURST_16;
} else {
DMACSR(sc) |= D_BURST_0;
}
break;
case DMAREV_ESC:
DMACSR(sc) |= D_AUTODRAIN; /* Auto-drain */
if (sc->sc_burst & SBUS_BURST_32) {
DMACSR(sc) &= ~0x800;
} else
DMACSR(sc) |= 0x800;
break;
default:
}
sc->sc_active = 0; /* and of course we aren't */
}
void
espdma_reset(sc)
struct dma_softc *sc;
{
dma_reset(sc, 0);
}
void
ledma_reset(sc)
struct dma_softc *sc;
{
dma_reset(sc, 1);
}
void
dma_enintr(sc)
struct dma_softc *sc;
{
sc->sc_regs->csr |= D_INT_EN;
}
int
dma_isintr(sc)
struct dma_softc *sc;
{
return (sc->sc_regs->csr & (D_INT_PEND|D_ERR_PEND));
}
#define DMAMAX(a) (0x01000000 - ((a) & 0x00ffffff))
/*
* setup a dma transfer
*/
int
dma_setup(sc, addr, len, datain, dmasize)
struct dma_softc *sc;
caddr_t *addr;
size_t *len;
int datain;
size_t *dmasize; /* IN-OUT */
{
u_long csr;
DMA_FLUSH(sc, 0);
#if 0
DMACSR(sc) &= ~D_INT_EN;
#endif
sc->sc_dmaaddr = addr;
sc->sc_dmalen = len;
NCR_DMA(("%s: start %d@%p,%d ", sc->sc_dev.dv_xname,
*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
/*
* the rules say we cannot transfer more than the limit
* of this DMA chip (64k for old and 16Mb for new),
* and we cannot cross a 16Mb boundary.
*/
*dmasize = sc->sc_dmasize =
min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
NCR_DMA((": dmasize = %d", sc->sc_dmasize));
/* Program the DMA address */
if (sc->sc_dmasize) {
if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap,
*sc->sc_dmaaddr, sc->sc_dmasize,
NULL /* This should already be mapped into the kernel */,
BUS_DMA_NOWAIT)
|| (sc->sc_dmamap->dm_segs[0].ds_addr == NULL))
panic("dma: cannot allocate DVMA address");
DMADDR(sc) = sc->sc_dvmakaddr = (caddr_t)sc->sc_dmamap->dm_segs[0].ds_addr;
} else {
DMADDR(sc) = *sc->sc_dmaaddr;
NCR_DMA((" dmakaddr = %p\n", sc->sc_dmaaddr));
}
if (sc->sc_rev == DMAREV_ESC) {
/* DMA ESC chip bug work-around */
register long bcnt = sc->sc_dmasize;
register long eaddr = bcnt + (long)*sc->sc_dmaaddr;
if ((eaddr & PGOFSET) != 0)
bcnt = roundup(bcnt, NBPG);
DMACNT(sc) = bcnt;
}
/* Setup DMA control register */
csr = DMACSR(sc);
if (datain)
csr |= D_WRITE;
else
csr &= ~D_WRITE;
csr |= D_INT_EN;
DMACSR(sc) = csr;
return 0;
}
void
dma_go(sc)
struct dma_softc *sc;
{
/* Start DMA */
DMACSR(sc) |= D_EN_DMA;
sc->sc_active = 1;
}
/*
* Pseudo (chained) interrupt from the esp driver to kick the
* current running DMA transfer. I am replying on espintr() to
* pickup and clean errors for now
*
* return 1 if it was a DMA continue.
*/
int
espdmaintr(arg)
void *arg;
{
struct dma_softc *sc = arg;
struct ncr53c9x_softc *nsc = &sc->sc_esp->sc_ncr53c9x;
char bits[64];
int trans, resid;
u_long csr;
csr = DMACSR(sc);
NCR_DMA(("%s: intr: addr %p, csr %s\n", sc->sc_dev.dv_xname,
DMADDR(sc), bitmask_snprintf(csr, DMACSRBITS, bits,
sizeof(bits))));
if (csr & D_ERR_PEND) {
DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */
DMACSR(sc) |= D_INVALIDATE;
printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname,
bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits)));
return -1;
}
/* This is an "assertion" :) */
if (sc->sc_active == 0)
panic("dmaintr: DMA wasn't active");
DMA_DRAIN(sc, 0);
/* DMA has stopped */
DMACSR(sc) &= ~D_EN_DMA;
sc->sc_active = 0;
if (sc->sc_dmasize == 0) {
/* A "Transfer Pad" operation completed */
NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
NCR_READ_REG(nsc, NCR_TCL) |
(NCR_READ_REG(nsc, NCR_TCM) << 8),
NCR_READ_REG(nsc, NCR_TCL),
NCR_READ_REG(nsc, NCR_TCM)));
return 0;
}
resid = 0;
/*
* If a transfer onto the SCSI bus gets interrupted by the device
* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
* as residual since the ESP counter registers get decremented as
* bytes are clocked into the FIFO.
*/
if (!(csr & D_WRITE) &&
(resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid));
}
if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
/*
* `Terminal count' is off, so read the residue
* out of the ESP counter registers.
*/
resid += (NCR_READ_REG(nsc, NCR_TCL) |
(NCR_READ_REG(nsc, NCR_TCM) << 8) |
((nsc->sc_cfg2 & NCRCFG2_FE)
? (NCR_READ_REG(nsc, NCR_TCH) << 16)
: 0));
if (resid == 0 && sc->sc_dmasize == 65536 &&
(nsc->sc_cfg2 & NCRCFG2_FE) == 0)
/* A transfer of 64K is encoded as `TCL=TCM=0' */
resid = 65536;
}
trans = sc->sc_dmasize - resid;
if (trans < 0) { /* transferred < 0 ? */
#if 0
/*
* This situation can happen in perfectly normal operation
* if the ESP is reselected while using DMA to select
* another target. As such, don't print the warning.
*/
printf("%s: xfer (%d) > req (%d)\n",
sc->sc_dev.dv_xname, trans, sc->sc_dmasize);
#endif
trans = sc->sc_dmasize;
}
NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
NCR_READ_REG(nsc, NCR_TCL),
NCR_READ_REG(nsc, NCR_TCM),
(nsc->sc_cfg2 & NCRCFG2_FE)
? NCR_READ_REG(nsc, NCR_TCH) : 0,
trans, resid));
if (csr & D_WRITE)
cache_flush(*sc->sc_dmaaddr, trans);
if (sc->sc_dvmakaddr)
bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
*sc->sc_dmalen -= trans;
*sc->sc_dmaaddr += trans;
#if 0 /* this is not normal operation just yet */
if (*sc->sc_dmalen == 0 ||
nsc->sc_phase != nsc->sc_prevphase)
return 0;
/* and again */
dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE);
return 1;
#endif
return 0;
}
/*
* Pseudo (chained) interrupt to le driver to handle DMA errors.
*/
int
ledmaintr(arg)
void *arg;
{
struct dma_softc *sc = arg;
char bits[64];
u_long csr;
static int dodrain=0;
csr = DMACSR(sc);
if (csr & D_ERR_PEND) {
DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */
DMACSR(sc) |= D_INVALIDATE;
printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname,
bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits)));
DMA_RESET(sc);
dodrain = 1;
}
if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */
#define E_DRAIN 0x400 /* XXX: fix dmareg.h */
int i = 10;
while (i-- > 0 && (sc->sc_regs->csr & D_DRAINING))
delay(1);
}
return (*sc->sc_intrchain)(sc->sc_intrchainarg);
}
bus_space_tag_t
dma_alloc_bustag(sc)
struct dma_softc *sc;
{
bus_space_tag_t sbt;
sbt = (bus_space_tag_t)
malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT);
if (sbt == NULL)
return (NULL);
bzero(sbt, sizeof *sbt);
sbt->cookie = sc;
sbt->parent = sc->sc_bustag;
sbt->sparc_intr_establish = dmabus_intr_establish;
return (sbt);
}

94
sys/arch/sparc64/dev/dmareg.h
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@ -1,94 +0,0 @@
/* $NetBSD: dmareg.h,v 1.1.1.1 1998/06/20 04:58:51 eeh Exp $ */
/*
* Copyright (c) 1994 Peter Galbavy. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Peter Galbavy.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#define DMACSRBITS "\020\01INT\02ERR\03DR1\04DR2\05IEN\011WRITE\016ENCNT\017TC\032DMAON"
struct dma_regs {
volatile u_long csr; /* DMA CSR */
#define D_INT_PEND 0x00000001 /* interrupt pending */
#define D_ERR_PEND 0x00000002 /* error pending */
#define D_DRAINING 0x0000000c /* fifo draining */
#define D_INT_EN 0x00000010 /* interrupt enable */
#define D_INVALIDATE 0x00000020 /* invalidate fifo */
#define D_SLAVE_ERR 0x00000040 /* slave access size error */
#define D_DRAIN 0x00000040 /* rev0,1,esc: drain fifo */
#define D_RESET 0x00000080 /* reset scsi */
#define D_WRITE 0x00000100 /* 1 = dev -> mem */
#define D_EN_DMA 0x00000200 /* enable DMA requests */
#define D_R_PEND 0x00000400 /* rev0,1: request pending */
#define D_ESC_BURST 0x00000800 /* DMA ESC: 16 byte bursts */
#define D_EN_CNT 0x00002000 /* enable byte counter */
#define D_TC 0x00004000 /* terminal count */
#define D_DSBL_CSR_DRN 0x00010000 /* disable fifo drain on csr */
#define D_DSBL_SCSI_DRN 0x00020000 /* disable fifo drain on reg */
#define D_BURST_SIZE 0x000c0000 /* sbus read/write burst size */
#define D_BURST_0 0x00080000 /* no bursts (SCSI-only) */
#define D_BURST_16 0x00000000 /* 16-byte bursts */
#define D_BURST_32 0x00040000 /* 32-byte bursts */
#define D_AUTODRAIN 0x00040000 /* DMA ESC: Auto-drain */
#define D_DIAG 0x00100000 /* disable fifo drain on addr */
#define D_TWO_CYCLE 0x00200000 /* 2 clocks per transfer */
#define D_FASTER 0x00400000 /* 3 clocks per transfer */
#define DE_AUI_TP 0x00400000 /* 1 for TP, 0 for AUI */
#define D_TCI_DIS 0x00800000 /* disable intr on D_TC */
#define D_EN_NEXT 0x01000000 /* enable auto next address */
#define D_DMA_ON 0x02000000 /* enable dma from scsi */
#define D_A_LOADED 0x04000000 /* address loaded */
#define D_NA_LOADED 0x08000000 /* next address loaded */
#define D_DEV_ID 0xf0000000 /* device ID */
#define DMAREV_0 0x00000000 /* Sunray DMA */
#define DMAREV_ESC 0x40000000 /* DMA ESC array */
#define DMAREV_1 0x80000000 /* 'DMA' */
#define DMAREV_PLUS 0x90000000 /* 'DMA+' */
#define DMAREV_2 0xa0000000 /* 'DMA2' */
volatile caddr_t addr;
#define DMA_D_ADDR 0x01 /* DMA ADDR (in u_longs) */
volatile u_long bcnt; /* DMA COUNT (in u_longs) */
#define D_BCNT_MASK 0x00ffffff /* only 24 bits */
volatile u_long test; /* DMA TEST (in u_longs) */
#define en_testcsr addr /* enet registers overlap */
#define en_cachev bcnt
#define en_bar test
};
/*
* PROM-reported DMA burst sizes for the SBus
*/
#define SBUS_BURST_1 0x1
#define SBUS_BURST_2 0x2
#define SBUS_BURST_4 0x4
#define SBUS_BURST_8 0x8
#define SBUS_BURST_16 0x10
#define SBUS_BURST_32 0x20
#define SBUS_BURST_64 0x40

70
sys/arch/sparc64/dev/dmavar.h
View File

@ -1,70 +0,0 @@
/* $NetBSD: dmavar.h,v 1.1.1.1 1998/06/20 04:58:51 eeh Exp $ */
/*
* Copyright (c) 1994 Peter Galbavy. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Peter Galbavy.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
struct dma_softc {
struct device sc_dev; /* us as a device */
struct sbusdev sc_sd; /* sbus device */
bus_space_tag_t sc_bustag; /* bus tags */
bus_dma_tag_t sc_dmatag;
struct esp_softc *sc_esp; /* my scsi */
struct le_softc *sc_le; /* my ethernet */
struct dma_regs *sc_regs; /* the registers */
int sc_active; /* DMA active ? */
u_int sc_rev; /* revision */
int sc_node; /* PROM node ID */
int sc_burst; /* DVMA burst size in effect */
caddr_t sc_dvmakaddr; /* DVMA cookies */
caddr_t sc_dvmaaddr; /* */
size_t sc_dmasize;
caddr_t *sc_dmaaddr;
size_t *sc_dmalen;
bus_dmamap_t sc_dmamap; /* DMA map for bus_dma_* */
void (*reset)(struct dma_softc *); /* reset routine */
void (*enintr)(struct dma_softc *); /* enable interrupts */
int (*isintr)(struct dma_softc *); /* interrupt ? */
int (*intr)(void *); /* interrupt ! */
int (*setup)(struct dma_softc *, caddr_t *, size_t *, int, size_t *);
void (*go)(struct dma_softc *);
int (*sc_intrchain)(void *); /* next handler in intr chain */
void *sc_intrchainarg; /* arg for next intr handler */
};
#define DMACSR(sc) (sc->sc_regs->csr)
#define DMADDR(sc) (sc->sc_regs->addr)
#define DMACNT(sc) (sc->sc_regs->bcnt)
/* DMA engine functions */
#define DMA_ENINTR(r) (((r)->enintr)(r))
#define DMA_ISINTR(r) (((r)->isintr)(r))
#define DMA_RESET(r) (((r)->reset)(r))
#define DMA_INTR(r) (((r)->intr)(r))
#define DMA_ISACTIVE(r) ((r)->sc_active)
#define DMA_SETUP(a, b, c, d, e) (((a)->setup)(a, b, c, d, e))
#define DMA_GO(r) (((r)->go)(r))

595
sys/arch/sparc64/dev/esp.c
View File

@ -1,595 +0,0 @@
/* $NetBSD: esp.c,v 1.6 1998/09/05 16:50:37 pk Exp $ */
/*-
* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
* Simulation Facility, NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright (c) 1994 Peter Galbavy
* Copyright (c) 1995 Paul Kranenburg
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Peter Galbavy
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Based on aic6360 by Jarle Greipsland
*
* Acknowledgements: Many of the algorithms used in this driver are
* inspired by the work of Julian Elischer (julian@tfs.com) and
* Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million!
*/
#include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/errno.h>
#include <sys/ioctl.h>
#include <sys/device.h>
#include <sys/buf.h>
#include <sys/proc.h>
#include <sys/user.h>
#include <sys/queue.h>
#include <dev/scsipi/scsi_all.h>
#include <dev/scsipi/scsipi_all.h>
#include <dev/scsipi/scsiconf.h>
#include <dev/scsipi/scsi_message.h>
#include <machine/bus.h>
#include <machine/autoconf.h>
#include <machine/cpu.h>
#include <dev/ic/ncr53c9xreg.h>
#include <dev/ic/ncr53c9xvar.h>
#include <dev/sbus/sbusvar.h>
#include <sparc64/dev/dmareg.h>
#include <sparc64/dev/dmavar.h>
#include <sparc64/dev/espvar.h>
void espattach_sbus __P((struct device *, struct device *, void *));
void espattach_obio __P((struct device *, struct device *, void *));
void espattach_dma __P((struct device *, struct device *, void *));
int espmatch_sbus __P((struct device *, struct cfdata *, void *));
int espmatch_obio __P((struct device *, struct cfdata *, void *));
void espattach __P((struct esp_softc *));
/* Linkup to the rest of the kernel */
struct cfattach esp_sbus_ca = {
sizeof(struct esp_softc), espmatch_sbus, espattach_sbus
};
struct cfattach esp_ca = {
sizeof(struct esp_softc), espmatch_sbus, espattach_dma
};
struct cfattach fas_ca = {
sizeof(struct esp_softc), espmatch_sbus, espattach_sbus
};
struct cfattach esp_obio_ca = {
sizeof(struct esp_softc), espmatch_obio, espattach_obio
};
struct scsipi_adapter esp_switch = {
ncr53c9x_scsi_cmd,
minphys, /* no max at this level; handled by DMA code */
NULL,
NULL,
};
struct scsipi_device esp_dev = {
NULL, /* Use default error handler */
NULL, /* have a queue, served by this */
NULL, /* have no async handler */
NULL, /* Use default 'done' routine */
};
/*
* Functions and the switch for the MI code.
*/
u_char esp_read_reg __P((struct ncr53c9x_softc *, int));
void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char));
int esp_dma_isintr __P((struct ncr53c9x_softc *));
void esp_dma_reset __P((struct ncr53c9x_softc *));
int esp_dma_intr __P((struct ncr53c9x_softc *));
int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
size_t *, int, size_t *));
void esp_dma_go __P((struct ncr53c9x_softc *));
void esp_dma_stop __P((struct ncr53c9x_softc *));
int esp_dma_isactive __P((struct ncr53c9x_softc *));
struct ncr53c9x_glue esp_glue = {
esp_read_reg,
esp_write_reg,
esp_dma_isintr,
esp_dma_reset,
esp_dma_intr,
esp_dma_setup,
esp_dma_go,
esp_dma_stop,
esp_dma_isactive,
NULL, /* gl_clear_latched_intr */
};
int
espmatch_sbus(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct sbus_attach_args *sa = aux;
return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0);
}
int
espmatch_obio(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
union obio_attach_args *uoba = aux;
struct obio4_attach_args *oba;
if (uoba->uoba_isobio4 == 0)
return (0);
oba = &uoba->uoba_oba4;
return (bus_space_probe(oba->oba_bustag, 0,
oba->oba_paddr,
1, /* probe size */
0, /* offset */
0, /* flags */
NULL, NULL));
}
void
espattach_sbus(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct esp_softc *esc = (void *)self;
struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
struct sbus_attach_args *sa = aux;
esc->sc_bustag = sa->sa_bustag;
esc->sc_dmatag = sa->sa_dmatag;
sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7);
sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1);
if (sc->sc_freq < 0)
sc->sc_freq = ((struct sbus_softc *)
sc->sc_dev.dv_parent)->sc_clockfreq;
/*
* Find the DMA by poking around the dma device structures
*
* What happens here is that if the dma driver has not been
* configured, then this returns a NULL pointer. Then when the
* dma actually gets configured, it does the opposing test, and
* if the sc->sc_esp field in it's softc is NULL, then tries to
* find the matching esp driver.
*/
esc->sc_dma = (struct dma_softc *)getdevunit("dma", sc->sc_dev.dv_unit);
/*
* and a back pointer to us, for DMA
*/
if (esc->sc_dma)
esc->sc_dma->sc_esp = esc;
else {
/*
* FAS chips have the DMA in the fas node. The first set
* of "reg" is the DMA controller, the second set is the FAS366
* itself. Need to deal w/this somehow.
*/
printf("\n");
panic("espattach: no dma found");
}
/*
* Map my registers in, if they aren't already in virtual
* address space.
*/
if (sa->sa_promvaddr)
esc->sc_reg = (volatile u_char *) sa->sa_promvaddr;
else {
bus_space_handle_t bh;
if (sbus_bus_map(sa->sa_bustag,
sa->sa_slot,
sa->sa_offset,
sa->sa_size,
BUS_SPACE_MAP_LINEAR,
0, &bh) != 0) {
printf("%s @ sbus: cannot map registers\n",
self->dv_xname);
return;
}
esc->sc_reg = (volatile u_char *)bh;
}
esc->sc_pri = sa->sa_pri;
/* add me to the sbus structures */
esc->sc_sd.sd_reset = (void *) ncr53c9x_reset;
sbus_establish(&esc->sc_sd, &sc->sc_dev);
if (sa->sa_bp != NULL && strcmp(sa->sa_bp->name, "esp") == 0 &&
SAME_ESP(sc, sa->sa_bp, sa))
bootpath_store(1, sa->sa_bp + 1);
espattach(esc);
}
void
espattach_dma(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct esp_softc *esc = (void *)self;
struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
struct sbus_attach_args *sa = aux;
esc->sc_bustag = sa->sa_bustag;
esc->sc_dmatag = sa->sa_dmatag;
sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7);
sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1);
esc->sc_dma = (struct dma_softc *)parent;
esc->sc_dma->sc_esp = esc;
/*
* Map my registers in, if they aren't already in virtual
* address space.
*/
if (sa->sa_npromvaddrs)
esc->sc_reg = (volatile u_char *) sa->sa_promvaddrs[0];
else {
bus_space_handle_t bh;
if (sbus_bus_map(sa->sa_bustag, sa->sa_slot,
sa->sa_offset,
sa->sa_size,
BUS_SPACE_MAP_LINEAR,
0, &bh) != 0) {
printf("%s @ dma: cannot map registers\n",
self->dv_xname);
return;
}
esc->sc_reg = (volatile u_char *)bh;
}
/* Establish interrupt handler */
esc->sc_pri = sa->sa_pri;
/* Assume SBus is grandparent */
esc->sc_sd.sd_reset = (void *) ncr53c9x_reset;
sbus_establish(&esc->sc_sd, parent);
if (sa->sa_bp != NULL && strcmp(sa->sa_bp->name, "esp") == 0 &&
SAME_ESP(sc, sa->sa_bp, sa))
bootpath_store(1, sa->sa_bp + 1);
espattach(esc);
}
void
espattach_obio(parent, self, aux)
struct device *parent, *self;
void *aux;
{
union obio_attach_args *uoba = aux;
struct obio4_attach_args *oba = &uoba->uoba_oba4;
struct esp_softc *esc = (void *)self;
struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
bus_space_handle_t bh;
esc->sc_bustag = oba->oba_bustag;
esc->sc_dmatag = oba->oba_dmatag;
sc->sc_id = 7;
sc->sc_freq = 24000000;
/*
* Find the DMA by poking around the dma device structures
*/
esc->sc_dma = (struct dma_softc *)getdevunit("dma", sc->sc_dev.dv_unit);
/*
* and a back pointer to us, for DMA
*/
if (esc->sc_dma)
esc->sc_dma->sc_esp = esc;
else {
printf("\n");
panic("espattach: no dma found");
}
if (obio_bus_map(oba->oba_bustag, oba->oba_paddr,
0, /* offset */
16, /* size (of ncr53c9xreg) */
BUS_SPACE_MAP_LINEAR,
0, &bh) != 0) {
printf("%s @ obio: cannot map registers\n", self->dv_xname);
return;
}
esc->sc_reg = (volatile u_char *)bh;
esc->sc_pri = oba->oba_pri;
if (oba->oba_bp != NULL && strcmp(oba->oba_bp->name, "esp") == 0 &&
oba->oba_bp->val[0] == -1 &&
oba->oba_bp->val[1] == sc->sc_dev.dv_unit)
bootpath_store(1, oba->oba_bp + 1);
espattach(esc);
}
/*
* Attach this instance, and then all the sub-devices
*/
void
espattach(esc)
struct esp_softc *esc;
{
struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
void *icookie;
/*
* Set up glue for MI code early; we use some of it here.
*/
sc->sc_glue = &esp_glue;
#if 0
printf(" pri %d", esc->sc_pri);
#endif
/* gimme Mhz */
sc->sc_freq /= 1000000;
/*
* XXX More of this should be in ncr53c9x_attach(), but
* XXX should we really poke around the chip that much in
* XXX the MI code? Think about this more...
*/
/*
* It is necessary to try to load the 2nd config register here,
* to find out what rev the esp chip is, else the ncr53c9x_reset
* will not set up the defaults correctly.
*/
sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE;
sc->sc_cfg3 = NCRCFG3_CDB;
NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) !=
(NCRCFG2_SCSI2 | NCRCFG2_RPE)) {
sc->sc_rev = NCR_VARIANT_ESP100;
} else {
sc->sc_cfg2 = NCRCFG2_SCSI2;
NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
sc->sc_cfg3 = 0;
NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK);
NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
if (NCR_READ_REG(sc, NCR_CFG3) !=
(NCRCFG3_CDB | NCRCFG3_FCLK)) {
sc->sc_rev = NCR_VARIANT_ESP100A;
} else {
/* NCRCFG2_FE enables > 64K transfers */
sc->sc_cfg2 |= NCRCFG2_FE;
sc->sc_cfg3 = 0;
NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
sc->sc_rev = NCR_VARIANT_ESP200;
}
}
/*
* XXX minsync and maxxfer _should_ be set up in MI code,
* XXX but it appears to have some dependency on what sort
* XXX of DMA we're hooked up to, etc.
*/
/*
* This is the value used to start sync negotiations
* Note that the NCR register "SYNCTP" is programmed
* in "clocks per byte", and has a minimum value of 4.
* The SCSI period used in negotiation is one-fourth
* of the time (in nanoseconds) needed to transfer one byte.
* Since the chip's clock is given in MHz, we have the following
* formula: 4 * period = (1000 / freq) * 4
*/
sc->sc_minsync = 1000 / sc->sc_freq;
/*
* Alas, we must now modify the value a bit, because it's
* only valid when can switch on FASTCLK and FASTSCSI bits
* in config register 3...
*/
switch (sc->sc_rev) {
case NCR_VARIANT_ESP100:
sc->sc_maxxfer = 64 * 1024;
sc->sc_minsync = 0; /* No synch on old chip? */
break;
case NCR_VARIANT_ESP100A:
sc->sc_maxxfer = 64 * 1024;
/* Min clocks/byte is 5 */
sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);
break;
case NCR_VARIANT_ESP200:
sc->sc_maxxfer = 16 * 1024 * 1024;
/* XXX - do actually set FAST* bits */
break;
}
/* Establish interrupt channel */
icookie = bus_intr_establish(esc->sc_bustag,
esc->sc_pri, 0,
(int(*)__P((void*)))ncr53c9x_intr, sc);
/* register interrupt stats */
evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt);
/* Do the common parts of attachment. */
ncr53c9x_attach(sc, &esp_switch, &esp_dev);
/* Turn on target selection using the `dma' method */
ncr53c9x_dmaselect = 1;
bootpath_store(1, NULL);
}
/*
* Glue functions.
*/
u_char
esp_read_reg(sc, reg)
struct ncr53c9x_softc *sc;
int reg;
{
struct esp_softc *esc = (struct esp_softc *)sc;
return (esc->sc_reg[reg * 4]);
}
void
esp_write_reg(sc, reg, val)
struct ncr53c9x_softc *sc;
int reg;
u_char val;
{
struct esp_softc *esc = (struct esp_softc *)sc;
u_char v = val;
esc->sc_reg[reg * 4] = v;
}
int
esp_dma_isintr(sc)
struct ncr53c9x_softc *sc;
{
struct esp_softc *esc = (struct esp_softc *)sc;
return (DMA_ISINTR(esc->sc_dma));
}
void
esp_dma_reset(sc)
struct ncr53c9x_softc *sc;
{
struct esp_softc *esc = (struct esp_softc *)sc;
DMA_RESET(esc->sc_dma);
}
int
esp_dma_intr(sc)
struct ncr53c9x_softc *sc;
{
struct esp_softc *esc = (struct esp_softc *)sc;
return (DMA_INTR(esc->sc_dma));
}
int
esp_dma_setup(sc, addr, len, datain, dmasize)
struct ncr53c9x_softc *sc;
caddr_t *addr;
size_t *len;
int datain;
size_t *dmasize;
{
struct esp_softc *esc = (struct esp_softc *)sc;
return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize));
}
void
esp_dma_go(sc)
struct ncr53c9x_softc *sc;
{
struct esp_softc *esc = (struct esp_softc *)sc;
DMA_GO(esc->sc_dma);
}
void
esp_dma_stop(sc)
struct ncr53c9x_softc *sc;
{
struct esp_softc *esc = (struct esp_softc *)sc;
DMACSR(esc->sc_dma) &= ~D_EN_DMA;
}
int
esp_dma_isactive(sc)
struct ncr53c9x_softc *sc;
{
struct esp_softc *esc = (struct esp_softc *)sc;
return (DMA_ISACTIVE(esc->sc_dma));
}

148
sys/arch/sparc64/dev/espreg.h
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@ -1,148 +0,0 @@
/* $NetBSD: espreg.h,v 1.1.1.1 1998/06/20 04:58:51 eeh Exp $ */
/*
* Copyright (c) 1994 Peter Galbavy. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Peter Galbavy.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Register addresses, relative to some base address
*/
#define ESP_TCL 0x00 /* RW - Transfer Count Low */
#define ESP_TCM 0x01 /* RW - Transfer Count Mid */
#define ESP_TCH 0x0e /* RW - Transfer Count High */
/* NOT on 53C90 */
#define ESP_FIFO 0x02 /* RW - FIFO data */
#define ESP_CMD 0x03 /* RW - Command (2 deep) */
#define ESPCMD_DMA 0x80 /* DMA Bit */
#define ESPCMD_NOP 0x00 /* No Operation */
#define ESPCMD_FLUSH 0x01 /* Flush FIFO */
#define ESPCMD_RSTCHIP 0x02 /* Reset Chip */
#define ESPCMD_RSTSCSI 0x03 /* Reset SCSI Bus */
#define ESPCMD_RESEL 0x40 /* Reselect Sequence */
#define ESPCMD_SELNATN 0x41 /* Select without ATN */
#define ESPCMD_SELATN 0x42 /* Select with ATN */
#define ESPCMD_SELATNS 0x43 /* Select with ATN & Stop */
#define ESPCMD_ENSEL 0x44 /* Enable (Re)Selection */
#define ESPCMD_DISSEL 0x45 /* Disable (Re)Selection */
#define ESPCMD_SELATN3 0x46 /* Select with ATN3 */
#define ESPCMD_RESEL3 0x47 /* Reselect3 Sequence */
#define ESPCMD_SNDMSG 0x20 /* Send Message */
#define ESPCMD_SNDSTAT 0x21 /* Send Status */
#define ESPCMD_SNDDATA 0x22 /* Send Data */
#define ESPCMD_DISCSEQ 0x23 /* Disconnect Sequence */
#define ESPCMD_TERMSEQ 0x24 /* Terminate Sequence */
#define ESPCMD_TCCS 0x25 /* Target Command Comp Seq */
#define ESPCMD_DISC 0x27 /* Disconnect */
#define ESPCMD_RECMSG 0x28 /* Receive Message */
#define ESPCMD_RECCMD 0x29 /* Receive Command */
#define ESPCMD_RECDATA 0x2a /* Receive Data */
#define ESPCMD_RECCSEQ 0x2b /* Receive Command Sequence*/
#define ESPCMD_ABORT 0x04 /* Target Abort DMA */
#define ESPCMD_TRANS 0x10 /* Transfer Information */
#define ESPCMD_ICCS 0x11 /* Initiator Cmd Comp Seq */
#define ESPCMD_MSGOK 0x12 /* Message Accepted */
#define ESPCMD_TRPAD 0x18 /* Transfer Pad */
#define ESPCMD_SETATN 0x1a /* Set ATN */
#define ESPCMD_RSTATN 0x1b /* Reset ATN */
#define ESP_STAT 0x04 /* RO - Status */
#define ESPSTAT_INT 0x80 /* Interrupt */
#define ESPSTAT_GE 0x40 /* Gross Error */
#define ESPSTAT_PE 0x20 /* Parity Error */
#define ESPSTAT_TC 0x10 /* Terminal Count */
#define ESPSTAT_VGC 0x08 /* Valid Group Code */
#define ESPSTAT_PHASE 0x07 /* Phase bits */
#define ESP_SELID 0x04 /* WO - Select/Reselect Bus ID */
#define ESP_INTR 0x05 /* RO - Interrupt */
#define ESPINTR_SBR 0x80 /* SCSI Bus Reset */
#define ESPINTR_ILL 0x40 /* Illegal Command */
#define ESPINTR_DIS 0x20 /* Disconnect */
#define ESPINTR_BS 0x10 /* Bus Service */
#define ESPINTR_FC 0x08 /* Function Complete */
#define ESPINTR_RESEL 0x04 /* Reselected */
#define ESPINTR_SELATN 0x02 /* Select with ATN */
#define ESPINTR_SEL 0x01 /* Selected */
#define ESP_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */
#define ESP_STEP 0x06 /* RO - Sequence Step */
#define ESPSTEP_MASK 0x07 /* the last 3 bits */
#define ESPSTEP_DONE 0x04 /* command went out */
#define ESP_SYNCTP 0x06 /* WO - Synch Transfer Period */
/* Default 5 (53C9X) */
#define ESP_FFLAG 0x07 /* RO - FIFO Flags */
#define ESPFIFO_SS 0xe0 /* Sequence Step (Dup) */
#define ESPFIFO_FF 0x1f /* Bytes in FIFO */
#define ESP_SYNCOFF 0x07 /* WO - Synch Offset */
/* 0 = ASYNC */
/* 1 - 15 = SYNC bytes */
#define ESP_CFG1 0x08 /* RW - Configuration #1 */
#define ESPCFG1_SLOW 0x80 /* Slow Cable Mode */
#define ESPCFG1_SRR 0x40 /* SCSI Reset Rep Int Dis */
#define ESPCFG1_PTEST 0x20 /* Parity Test Mod */
#define ESPCFG1_PARENB 0x10 /* Enable Parity Check */
#define ESPCFG1_CTEST 0x08 /* Enable Chip Test */
#define ESPCFG1_BUSID 0x07 /* Bus ID */
#define ESP_CCF 0x09 /* WO - Clock Conversion Factor */
/* 0 = 35.01 - 40Mhz */
/* NEVER SET TO 1 */
/* 2 = 10Mhz */
/* 3 = 10.01 - 15Mhz */
/* 4 = 15.01 - 20Mhz */
/* 5 = 20.01 - 25Mhz */
/* 6 = 25.01 - 30Mhz */
/* 7 = 30.01 - 35Mhz */
#define ESP_TEST 0x0a /* WO - Test (Chip Test Only) */
#define ESP_CFG2 0x0b /* RW - Configuration #2 */
#define ESPCFG2_RSVD 0xa0 /* reserved */
#define ESPCFG2_FE 0x40 /* Features Enable */
#define ESPCFG2_DREQ 0x10 /* DREQ High Impedance */
#define ESPCFG2_SCSI2 0x08 /* SCSI-2 Enable */
#define ESPCFG2_BPA 0x04 /* Target Bad Parity Abort */
#define ESPCFG2_RPE 0x02 /* Register Parity Error */
#define ESPCFG2_DPE 0x01 /* DMA Parity Error */
/* Config #3 only on 53C9X */
#define ESP_CFG3 0x0c /* RW - Configuration #3 */
#define ESPCFG3_RSVD 0xe0 /* reserved */
#define ESPCFG3_IDM 0x10 /* ID Message Res Check */
#define ESPCFG3_QTE 0x08 /* Queue Tag Enable */
#define ESPCFG3_CDB 0x04 /* CDB 10-bytes OK */
#define ESPCFG3_FSCSI 0x02 /* Fast SCSI */
#define ESPCFG3_FCLK 0x01 /* Fast Clock (>25Mhz) */

57
sys/arch/sparc64/dev/espvar.h
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@ -1,57 +0,0 @@
/* $NetBSD: espvar.h,v 1.1.1.1 1998/06/20 04:58:51 eeh Exp $ */
/*-
* Copyright (c) 1997 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
struct esp_softc {
struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
bus_space_tag_t sc_bustag;
bus_dma_tag_t sc_dmatag;
struct sbusdev sc_sd; /* sbus device */
struct intrhand sc_ih; /* intr handler */
volatile u_char *sc_reg; /* the registers */
struct dma_softc *sc_dma; /* pointer to my dma */
/* openprom stuff */
int sc_node; /* PROM node ID */
int sc_pri; /* SBUS priority */
};
#define SAME_ESP(sc, bp, sa) \
((bp->val[0] == sa->sa_slot && bp->val[1] == sa->sa_offset) || \
(bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit))