From 304b305c9e45644b18bd2eb34bd21b73e5391490 Mon Sep 17 00:00:00 2001 From: tsutsui Date: Fri, 3 Nov 2006 17:01:54 +0000 Subject: [PATCH] Minor cleanups: - move some driver specific definitions from rtl81x9reg.h to rtl81x9var.h - move several macro where related structures are declared - remove unused macro - fix some comments - unwrap some lines --- sys/dev/ic/rtl81x9reg.h | 43 +++--------------------- sys/dev/ic/rtl81x9var.h | 73 ++++++++++++++++++++++++++++------------- 2 files changed, 56 insertions(+), 60 deletions(-) diff --git a/sys/dev/ic/rtl81x9reg.h b/sys/dev/ic/rtl81x9reg.h index 3914aae9679c..b3a77c3ab0f2 100644 --- a/sys/dev/ic/rtl81x9reg.h +++ b/sys/dev/ic/rtl81x9reg.h @@ -1,4 +1,4 @@ -/* $NetBSD: rtl81x9reg.h,v 1.19 2006/11/03 14:41:40 tsutsui Exp $ */ +/* $NetBSD: rtl81x9reg.h,v 1.20 2006/11/03 17:01:54 tsutsui Exp $ */ /* * Copyright (c) 1997, 1998 @@ -253,6 +253,7 @@ #define RTK_RXBUF_16 0x00000800 #define RTK_RXBUF_32 0x00001000 #define RTK_RXBUF_64 0x00001800 +#define RTK_RXBUF_LEN(x) (1 << (((x) >> 11) + 13)) #define RTK_RXFIFO_16BYTES 0x00000000 #define RTK_RXFIFO_32BYTES 0x00002000 @@ -411,28 +412,7 @@ #define RTK_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ #define RTK_GMEDIASTAT_TBI 0x80 /* TBI enabled */ -/* - * The RealTek doesn't use a fragment-based descriptor mechanism. - * Instead, there are only four register sets, each or which represents - * one 'descriptor.' Basically, each TX descriptor is just a contiguous - * packet buffer (32-bit aligned!) and we place the buffer addresses in - * the registers so the chip knows where they are. - * - * We can sort of kludge together the same kind of buffer management - * used in previous drivers, but we have to do buffer copies almost all - * the time, so it doesn't really buy us much. - * - * For reception, there's just one large buffer where the chip stores - * all received packets. - */ -#ifdef dreamcast -#define RTK_RX_BUF_SZ RTK_RXBUF_16 -#else -#define RTK_RX_BUF_SZ RTK_RXBUF_64 -#endif -#define RTK_RXBUFLEN (1 << ((RTK_RX_BUF_SZ >> 11) + 13)) -#define RTK_TX_LIST_CNT 4 #define RTK_TX_EARLYTHRESH ((256 / 32) << 16) #define RTK_RX_FIFOTHRESH RTK_RXFIFO_256BYTES #define RTK_RX_MAXDMA RTK_RXDMA_256BYTES @@ -442,13 +422,6 @@ #define RTK_TXCFG_CONFIG (RTK_TXCFG_IFG|RTK_TX_MAXDMA) -/* - * The 8139C+ and 8160 gigE chips support descriptor-based TX - * and RX. In fact, they even support TCP large send. Descriptors - * must be allocated in contiguous blocks that are aligned on a - * 256-byte boundary. The rings can hold a maximum of 64 descriptors. - */ - /* * RX/TX descriptor definition. When large send mode is enabled, the * lower 11 bits of the TX rtk_cmd word are used to hold the MSS, and @@ -533,6 +506,9 @@ struct rtk_desc { #define RTK_UDPPKT(x) (((x) & RTK_RDESC_STAT_PROTOID) == \ RTK_PROTOID_UDPIP) +#define RTK_ADDR_LO(y) ((uint64_t)(y) & 0xFFFFFFFF) +#define RTK_ADDR_HI(y) ((uint64_t)(y) >> 32) + /* * Statistics counter structure (8139C+ and 8169 only) */ @@ -555,16 +531,7 @@ struct rtk_stats { uint16_t rtk_rx_underruns; }; -#define RTK_RX_DESC_CNT 64 -#define RTK_TX_DESC_CNT_8139 64 -#define RTK_TX_DESC_CNT_8169 1024 -#define RTK_RX_LIST_SZ (RTK_RX_DESC_CNT * sizeof(struct rtk_desc)) -#define RTK_RING_ALIGN 256 #define RTK_IFQ_MAXLEN 512 -#define RTK_PKTSZ(x) ((x)/* >> 3*/) - -#define RTK_ADDR_LO(y) ((uint64_t)(y) & 0xFFFFFFFF) -#define RTK_ADDR_HI(y) ((uint64_t)(y) >> 32) #define RTK_JUMBO_FRAMELEN 9018 #define RTK_JUMBO_MTU (RTK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) diff --git a/sys/dev/ic/rtl81x9var.h b/sys/dev/ic/rtl81x9var.h index 2a2c81e41628..27eb3056dbc9 100644 --- a/sys/dev/ic/rtl81x9var.h +++ b/sys/dev/ic/rtl81x9var.h @@ -1,4 +1,4 @@ -/* $NetBSD: rtl81x9var.h,v 1.29 2006/11/03 14:41:41 tsutsui Exp $ */ +/* $NetBSD: rtl81x9var.h,v 1.30 2006/11/03 17:01:54 tsutsui Exp $ */ /* * Copyright (c) 1997, 1998 @@ -60,6 +60,15 @@ struct rtk_hwrev { const char *rtk_desc; }; +#define RTK_8129 1 +#define RTK_8139 2 +#define RTK_8139CPLUS 3 +#define RTK_8169 4 + +#define RTK_ISCPLUS(x) ((x)->rtk_type == RTK_8139CPLUS || \ + (x)->rtk_type == RTK_8169) + + struct rtk_mii_frame { uint8_t mii_stdelim; uint8_t mii_opcode; @@ -77,22 +86,44 @@ struct rtk_mii_frame { #define RTK_MII_WRITEOP 0x01 #define RTK_MII_TURNAROUND 0x02 -#define RTK_8129 1 -#define RTK_8139 2 -#define RTK_8139CPLUS 3 -#define RTK_8169 4 - -#define RTK_ISCPLUS(x) ((x)->rtk_type == RTK_8139CPLUS || \ - (x)->rtk_type == RTK_8169) - -#define RTK_TX_QLEN 64 /* - * The 8139C+ and 8160 gigE chips support descriptor-based TX + * The RealTek doesn't use a fragment-based descriptor mechanism. + * Instead, there are only four register sets, each or which represents + * one 'descriptor.' Basically, each TX descriptor is just a contiguous + * packet buffer (32-bit aligned!) and we place the buffer addresses in + * the registers so the chip knows where they are. + * + * We can sort of kludge together the same kind of buffer management + * used in previous drivers, but we have to do buffer copies almost all + * the time, so it doesn't really buy us much. + * + * For reception, there's just one large buffer where the chip stores + * all received packets. + */ + +#ifdef dreamcast +#define RTK_RX_BUF_SZ RTK_RXBUF_16 +#else +#define RTK_RX_BUF_SZ RTK_RXBUF_64 +#endif +#define RTK_RXBUFLEN RTK_RXBUF_LEN(RTK_RX_BUF_SZ) +#define RTK_TX_LIST_CNT 4 + +/* + * The 8139C+ and 8169 gigE chips support descriptor-based TX * and RX. In fact, they even support TCP large send. Descriptors * must be allocated in contiguous blocks that are aligned on a - * 256-byte boundary. The rings can hold a maximum of 64 descriptors. + * 256-byte boundary. The RX rings can hold a maximum of 64 descriptors. + * The TX rings can hold upto 64 descriptors on 8139C+, and + * 1024 descriptors on 8169 gigE chips. */ +#define RTK_RING_ALIGN 256 + +#define RTK_RX_DESC_CNT 64 +#define RTK_TX_DESC_CNT_8139 64 +#define RTK_TX_DESC_CNT_8169 1024 +#define RTK_TX_QLEN 64 struct rtk_rxsoft { struct mbuf *rxs_mbuf; @@ -170,16 +201,14 @@ struct rtk_softc { #endif }; -#define RTK_TX_DESC_CNT(sc) \ - ((sc)->rtk_ldata.rtk_tx_desc_cnt) -#define RTK_TX_LIST_SZ(sc) \ - (RTK_TX_DESC_CNT(sc) * sizeof(struct rtk_desc)) -#define RTK_NEXT_TX_DESC(sc, x) \ - (((x) + 1) % RTK_TX_DESC_CNT(sc)) -#define RTK_NEXT_RX_DESC(sc, x) \ - (((x) + 1) % RTK_RX_DESC_CNT) -#define RTK_NEXT_TXQ(sc, x) \ - (((x) + 1) % RTK_TX_QLEN) +#define RTK_TX_DESC_CNT(sc) ((sc)->rtk_ldata.rtk_tx_desc_cnt) +#define RTK_TX_LIST_SZ(sc) (RTK_TX_DESC_CNT(sc) * sizeof(struct rtk_desc)) +#define RTK_NEXT_TX_DESC(sc, x) (((x) + 1) % RTK_TX_DESC_CNT(sc)) + +#define RTK_RX_LIST_SZ (RTK_RX_DESC_CNT * sizeof(struct rtk_desc)) +#define RTK_NEXT_RX_DESC(sc, x) (((x) + 1) % RTK_RX_DESC_CNT) + +#define RTK_NEXT_TXQ(sc, x) (((x) + 1) % RTK_TX_QLEN) #define RTK_TXDESCSYNC(sc, idx, ops) \ bus_dmamap_sync((sc)->sc_dmat, \