Rework this driver to support other dsrtc than just the DS1307.
Support both BCD and 32-bit binary type RTCs. Supports DS1339, DS1672, and DS3232. To select variant, put the module # in flags in the the config file. dsrtc at iic0 addr 0x69 flags 1339 If the flags is not supplied, a 1307 is assumed (compatible).
This commit is contained in:
matt
parent
081df64308
commit
303782ebd0
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@ -1,4 +1,4 @@
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/* $NetBSD: ds1307.c,v 1.14 2012/01/07 15:03:11 phx Exp $ */
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/* $NetBSD: ds1307.c,v 1.15 2012/02/23 20:59:19 matt Exp $ */
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/*
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* Copyright (c) 2003 Wasabi Systems, Inc.
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@ -36,7 +36,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.14 2012/01/07 15:03:11 phx Exp $");
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__KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.15 2012/02/23 20:59:19 matt Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -52,11 +52,55 @@ __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.14 2012/01/07 15:03:11 phx Exp $");
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#include <dev/i2c/i2cvar.h>
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#include <dev/i2c/ds1307reg.h>
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struct dsrtc_model {
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uint16_t dm_model;
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uint8_t dm_ch_reg;
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uint8_t dm_ch_value;
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uint8_t dm_rtc_start;
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uint8_t dm_rtc_size;
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uint8_t dm_nvram_start;
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uint8_t dm_nvram_size;
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uint8_t dm_flags;
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#define DSRTC_FLAG_CLOCK_HOLD 1
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#define DSRTC_FLAG_BCD 2
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};
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static const struct dsrtc_model dsrtc_models[] = {
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{
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.dm_model = 1307,
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.dm_ch_reg = DSXXXX_SECONDS,
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.dm_ch_value = DS1307_SECONDS_CH,
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.dm_rtc_start = DS1307_RTC_START,
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.dm_rtc_size = DS1307_RTC_SIZE,
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.dm_nvram_start = DS1307_NVRAM_START,
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.dm_nvram_size = DS1307_NVRAM_SIZE,
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.dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD,
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}, {
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.dm_model = 1339,
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.dm_rtc_start = DS1339_RTC_START,
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.dm_rtc_size = DS1339_RTC_SIZE,
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.dm_flags = DSRTC_FLAG_BCD,
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}, {
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.dm_model = 1672,
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.dm_rtc_start = DS1672_RTC_START,
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.dm_rtc_size = DS1672_RTC_SIZE,
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.dm_flags = 0,
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}, {
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.dm_model = 3232,
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.dm_rtc_start = DS3232_RTC_START,
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.dm_rtc_size = DS3232_RTC_SIZE,
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.dm_nvram_start = DS3232_NVRAM_START,
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.dm_nvram_size = DS3232_NVRAM_SIZE,
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.dm_flags = DSRTC_FLAG_BCD,
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},
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};
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struct dsrtc_softc {
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device_t sc_dev;
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i2c_tag_t sc_tag;
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int sc_address;
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int sc_open;
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uint8_t sc_address;
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bool sc_open;
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struct dsrtc_model sc_model;
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struct todr_chip_handle sc_todr;
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};
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@ -77,10 +121,30 @@ const struct cdevsw dsrtc_cdevsw = {
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nostop, notty, nopoll, nommap, nokqfilter, D_OTHER
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};
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static int dsrtc_clock_read(struct dsrtc_softc *, struct clock_ymdhms *);
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static int dsrtc_clock_write(struct dsrtc_softc *, struct clock_ymdhms *);
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static int dsrtc_gettime(struct todr_chip_handle *, struct clock_ymdhms *);
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static int dsrtc_settime(struct todr_chip_handle *, struct clock_ymdhms *);
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static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *);
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static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *);
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static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *);
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static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *);
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static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *);
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static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *);
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static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *);
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static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t);
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static const struct dsrtc_model *
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dsrtc_model(u_int model)
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{
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/* no model given, assume it's a DS1307 (the first one) */
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if (model == 0)
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return &dsrtc_models[0];
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for (const struct dsrtc_model *dm = dsrtc_models;
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dm < dsrtc_models + __arraycount(dsrtc_models); dm++) {
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if (dm->dm_model == model)
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return dm;
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}
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return NULL;
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}
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static int
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dsrtc_match(device_t parent, cfdata_t cf, void *arg)
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@ -94,7 +158,7 @@ dsrtc_match(device_t parent, cfdata_t cf, void *arg)
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} else {
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/* indirect config - check typical address */
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if (ia->ia_addr == DS1307_ADDR)
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return 1;
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return dsrtc_model(cf->cf_flags & 0xffff) != NULL;
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}
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return 0;
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}
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@ -104,19 +168,27 @@ dsrtc_attach(device_t parent, device_t self, void *arg)
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{
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struct dsrtc_softc *sc = device_private(self);
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struct i2c_attach_args *ia = arg;
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const struct dsrtc_model * const dm =
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dsrtc_model(device_cfdata(self)->cf_flags);
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aprint_naive(": Real-time Clock/NVRAM\n");
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aprint_normal(": DS1307 Real-time Clock/NVRAM\n");
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aprint_naive(": Real-time Clock%s\n",
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dm->dm_nvram_size > 0 ? "/NVRAM" : "");
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aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model,
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dm->dm_nvram_size > 0 ? "/NVRAM" : "");
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sc->sc_tag = ia->ia_tag;
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sc->sc_address = ia->ia_addr;
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sc->sc_model = *dm;
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sc->sc_dev = self;
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sc->sc_open = 0;
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sc->sc_todr.cookie = sc;
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sc->sc_todr.todr_gettime = NULL;
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sc->sc_todr.todr_settime = NULL;
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sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime;
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sc->sc_todr.todr_settime_ymdhms = dsrtc_settime;
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if (dm->dm_flags & DSRTC_FLAG_BCD) {
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sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms;
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sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms;
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} else {
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sc->sc_todr.todr_gettime = dsrtc_gettime_timeval;
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sc->sc_todr.todr_settime = dsrtc_settime_timeval;
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}
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sc->sc_todr.todr_setwen = NULL;
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todr_attach(&sc->sc_todr);
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@ -132,11 +204,10 @@ dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l)
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return ENXIO;
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/* XXX: Locking */
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if (sc->sc_open)
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return EBUSY;
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sc->sc_open = 1;
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sc->sc_open = true;
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return 0;
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}
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@ -149,7 +220,7 @@ dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l)
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if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL)
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return ENXIO;
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sc->sc_open = 0;
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sc->sc_open = false;
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return 0;
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}
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@ -158,24 +229,26 @@ int
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dsrtc_read(dev_t dev, struct uio *uio, int flags)
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{
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struct dsrtc_softc *sc;
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u_int8_t ch, cmdbuf[1];
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int a, error;
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int error;
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if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL)
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return ENXIO;
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if (uio->uio_offset >= DS1307_NVRAM_SIZE)
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const struct dsrtc_model * const dm = &sc->sc_model;
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if (uio->uio_offset >= dm->dm_nvram_size)
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return EINVAL;
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if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0)
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return error;
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while (uio->uio_resid && uio->uio_offset < DS1307_NVRAM_SIZE) {
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a = (int)uio->uio_offset;
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cmdbuf[0] = a + DS1307_NVRAM_START;
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if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP,
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sc->sc_address, cmdbuf, 1,
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&ch, 1, 0)) != 0) {
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KASSERT(uio->uio_offset >= 0);
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while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) {
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uint8_t ch, cmd;
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const u_int a = uio->uio_offset;
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cmd = a + dm->dm_nvram_start;
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if ((error = iic_exec(sc->sc_tag,
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uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP,
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sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) {
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iic_release_bus(sc->sc_tag, 0);
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aprint_error_dev(sc->sc_dev,
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"dsrtc_read: read failed at 0x%x\n", a);
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@ -197,21 +270,22 @@ int
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dsrtc_write(dev_t dev, struct uio *uio, int flags)
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{
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struct dsrtc_softc *sc;
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u_int8_t cmdbuf[2];
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int a, error;
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int error;
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if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL)
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return ENXIO;
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if (uio->uio_offset >= DS1307_NVRAM_SIZE)
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const struct dsrtc_model * const dm = &sc->sc_model;
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if (uio->uio_offset >= dm->dm_nvram_size)
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return EINVAL;
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if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0)
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return error;
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while (uio->uio_resid && uio->uio_offset < DS1307_NVRAM_SIZE) {
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a = (int)uio->uio_offset;
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cmdbuf[0] = a + DS1307_NVRAM_START;
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while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) {
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uint8_t cmdbuf[2];
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const u_int a = (int)uio->uio_offset;
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cmdbuf[0] = a + dm->dm_nvram_start;
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if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0)
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break;
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@ -230,7 +304,7 @@ dsrtc_write(dev_t dev, struct uio *uio, int flags)
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}
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static int
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dsrtc_gettime(struct todr_chip_handle *ch, struct clock_ymdhms *dt)
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dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt)
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{
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struct dsrtc_softc *sc = ch->cookie;
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struct clock_ymdhms check;
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@ -245,29 +319,31 @@ dsrtc_gettime(struct todr_chip_handle *ch, struct clock_ymdhms *dt)
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*/
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retries = 5;
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do {
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dsrtc_clock_read(sc, dt);
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dsrtc_clock_read(sc, &check);
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dsrtc_clock_read_ymdhms(sc, dt);
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dsrtc_clock_read_ymdhms(sc, &check);
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} while (memcmp(dt, &check, sizeof(check)) != 0 && --retries);
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return 0;
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}
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static int
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dsrtc_settime(struct todr_chip_handle *ch, struct clock_ymdhms *dt)
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dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt)
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{
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struct dsrtc_softc *sc = ch->cookie;
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if (dsrtc_clock_write(sc, dt) == 0)
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if (dsrtc_clock_write_ymdhms(sc, dt) == 0)
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return -1;
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return 0;
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}
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static int
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dsrtc_clock_read(struct dsrtc_softc *sc, struct clock_ymdhms *dt)
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dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt)
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{
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u_int8_t bcd[DS1307_NRTC_REGS], cmdbuf[1];
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int i;
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struct dsrtc_model * const dm = &sc->sc_model;
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uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1];
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KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size);
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if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) {
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aprint_error_dev(sc->sc_dev,
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@ -276,8 +352,8 @@ dsrtc_clock_read(struct dsrtc_softc *sc, struct clock_ymdhms *dt)
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}
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/* Read each RTC register in order. */
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for (i = DS1307_SECONDS; i < DS1307_NRTC_REGS; i++) {
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cmdbuf[0] = i;
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for (u_int i = 0; i < dm->dm_rtc_size; i++) {
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cmdbuf[0] = dm->dm_rtc_start + i;
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if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP,
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sc->sc_address, cmdbuf, 1,
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@ -294,46 +370,52 @@ dsrtc_clock_read(struct dsrtc_softc *sc, struct clock_ymdhms *dt)
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iic_release_bus(sc->sc_tag, I2C_F_POLL);
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/*
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* Convert the DS1307's register values into something useable
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* Convert the RTC's register values into something useable
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*/
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dt->dt_sec = FROMBCD(bcd[DS1307_SECONDS] & DS1307_SECONDS_MASK);
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dt->dt_min = FROMBCD(bcd[DS1307_MINUTES] & DS1307_MINUTES_MASK);
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dt->dt_sec = FROMBCD(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK);
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dt->dt_min = FROMBCD(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK);
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if ((bcd[DS1307_HOURS] & DS1307_HOURS_12HRS_MODE) != 0) {
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dt->dt_hour = FROMBCD(bcd[DS1307_HOURS] &
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DS1307_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */
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if (bcd[DS1307_HOURS] & DS1307_HOURS_12HRS_PM)
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if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) {
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dt->dt_hour = FROMBCD(bcd[DSXXXX_HOURS] &
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DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */
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if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM)
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dt->dt_hour += 12;
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} else
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dt->dt_hour = FROMBCD(bcd[DS1307_HOURS] &
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DS1307_HOURS_24MASK);
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dt->dt_hour = FROMBCD(bcd[DSXXXX_HOURS] &
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DSXXXX_HOURS_24MASK);
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dt->dt_day = FROMBCD(bcd[DS1307_DATE] & DS1307_DATE_MASK);
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dt->dt_mon = FROMBCD(bcd[DS1307_MONTH] & DS1307_MONTH_MASK);
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dt->dt_day = FROMBCD(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK);
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dt->dt_mon = FROMBCD(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK);
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/* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */
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dt->dt_year = FROMBCD(bcd[DS1307_YEAR]) + POSIX_BASE_YEAR;
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dt->dt_year = FROMBCD(bcd[DSXXXX_YEAR]) + POSIX_BASE_YEAR;
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if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY)
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dt->dt_year += 100;
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return 1;
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}
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static int
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dsrtc_clock_write(struct dsrtc_softc *sc, struct clock_ymdhms *dt)
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dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt)
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{
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uint8_t bcd[DS1307_NRTC_REGS], cmdbuf[2];
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int i;
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struct dsrtc_model * const dm = &sc->sc_model;
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uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2];
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KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size);
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/*
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* Convert our time representation into something the DS1307
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* Convert our time representation into something the DSXXXX
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* can understand.
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*/
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bcd[DS1307_SECONDS] = TOBCD(dt->dt_sec);
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bcd[DS1307_MINUTES] = TOBCD(dt->dt_min);
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bcd[DS1307_HOURS] = TOBCD(dt->dt_hour); /* DS1307_HOURS_12HRS_MODE=0 */
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bcd[DS1307_DATE] = TOBCD(dt->dt_day);
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bcd[DS1307_DAY] = TOBCD(dt->dt_wday);
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bcd[DS1307_MONTH] = TOBCD(dt->dt_mon);
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bcd[DS1307_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100);
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bcd[DSXXXX_SECONDS] = TOBCD(dt->dt_sec);
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bcd[DSXXXX_MINUTES] = TOBCD(dt->dt_min);
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bcd[DSXXXX_HOURS] = TOBCD(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */
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bcd[DSXXXX_DATE] = TOBCD(dt->dt_day);
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bcd[DSXXXX_DAY] = TOBCD(dt->dt_wday);
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bcd[DSXXXX_MONTH] = TOBCD(dt->dt_mon);
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bcd[DSXXXX_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100);
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if (dt->dt_year - POSIX_BASE_YEAR >= 100)
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bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY;
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|
||||
if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) {
|
||||
aprint_error_dev(sc->sc_dev,
|
||||
|
|
@ -342,14 +424,23 @@ dsrtc_clock_write(struct dsrtc_softc *sc, struct clock_ymdhms *dt)
|
|||
}
|
||||
|
||||
/* Stop the clock */
|
||||
cmdbuf[0] = DS1307_SECONDS;
|
||||
cmdbuf[1] = DS1307_SECONDS_CH;
|
||||
cmdbuf[0] = dm->dm_ch_reg;
|
||||
|
||||
if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
|
||||
cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) {
|
||||
if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address,
|
||||
cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) {
|
||||
iic_release_bus(sc->sc_tag, I2C_F_POLL);
|
||||
aprint_error_dev(sc->sc_dev,
|
||||
"dsrtc_clock_write: failed to Hold Clock\n");
|
||||
"dsrtc_clock_write: failed to read Hold Clock\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
cmdbuf[1] |= dm->dm_ch_value;
|
||||
|
||||
if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
|
||||
cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) {
|
||||
iic_release_bus(sc->sc_tag, I2C_F_POLL);
|
||||
aprint_error_dev(sc->sc_dev,
|
||||
"dsrtc_clock_write: failed to write Hold Clock\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -357,12 +448,14 @@ dsrtc_clock_write(struct dsrtc_softc *sc, struct clock_ymdhms *dt)
|
|||
* Write registers in reverse order. The last write (to the Seconds
|
||||
* register) will undo the Clock Hold, above.
|
||||
*/
|
||||
for (i = DS1307_NRTC_REGS - 1; i >= 0; i--) {
|
||||
cmdbuf[0] = i;
|
||||
if (iic_exec(sc->sc_tag,
|
||||
i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP,
|
||||
sc->sc_address, cmdbuf, 1, &bcd[i], 1,
|
||||
I2C_F_POLL)) {
|
||||
uint8_t op = I2C_OP_WRITE;
|
||||
for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) {
|
||||
cmdbuf[0] = dm->dm_rtc_start + i;
|
||||
if (dm->dm_rtc_start + i == dm->dm_ch_reg) {
|
||||
op = I2C_OP_WRITE_WITH_STOP;
|
||||
}
|
||||
if (iic_exec(sc->sc_tag, op, sc->sc_address,
|
||||
cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) {
|
||||
iic_release_bus(sc->sc_tag, I2C_F_POLL);
|
||||
aprint_error_dev(sc->sc_dev,
|
||||
"dsrtc_clock_write: failed to write rtc "
|
||||
|
|
@ -371,8 +464,134 @@ dsrtc_clock_write(struct dsrtc_softc *sc, struct clock_ymdhms *dt)
|
|||
return 0;
|
||||
}
|
||||
}
|
||||
/*
|
||||
* If the clock hold register isn't the same register as seconds,
|
||||
* we need to reeanble the clock.
|
||||
*/
|
||||
if (op != I2C_OP_WRITE_WITH_STOP) {
|
||||
cmdbuf[0] = dm->dm_ch_reg;
|
||||
cmdbuf[1] &= ~dm->dm_ch_value;
|
||||
|
||||
if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address,
|
||||
cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) {
|
||||
iic_release_bus(sc->sc_tag, I2C_F_POLL);
|
||||
aprint_error_dev(sc->sc_dev,
|
||||
"dsrtc_clock_write: failed to Hold Clock\n");
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
iic_release_bus(sc->sc_tag, I2C_F_POLL);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int
|
||||
dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv)
|
||||
{
|
||||
struct dsrtc_softc *sc = ch->cookie;
|
||||
struct timeval check;
|
||||
int retries;
|
||||
|
||||
memset(tv, 0, sizeof(*tv));
|
||||
memset(&check, 0, sizeof(check));
|
||||
|
||||
/*
|
||||
* Since we don't support Burst Read, we have to read the clock twice
|
||||
* until we get two consecutive identical results.
|
||||
*/
|
||||
retries = 5;
|
||||
do {
|
||||
dsrtc_clock_read_timeval(sc, &tv->tv_sec);
|
||||
dsrtc_clock_read_timeval(sc, &check.tv_sec);
|
||||
} while (memcmp(tv, &check, sizeof(check)) != 0 && --retries);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv)
|
||||
{
|
||||
struct dsrtc_softc *sc = ch->cookie;
|
||||
|
||||
if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* The RTC probably has a nice Clock Burst Read/Write command, but we can't use
|
||||
* it, since some I2C controllers don't support anything other than single-byte
|
||||
* transfers.
|
||||
*/
|
||||
static int
|
||||
dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp)
|
||||
{
|
||||
const struct dsrtc_model * const dm = &sc->sc_model;
|
||||
uint8_t buf[4];
|
||||
|
||||
if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) {
|
||||
aprint_error_dev(sc->sc_dev, "%s: failed to acquire I2C bus\n",
|
||||
__func__);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* read all registers: */
|
||||
uint8_t reg = dm->dm_rtc_start;
|
||||
if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, ®, 1,
|
||||
buf, 4, I2C_F_POLL)) {
|
||||
iic_release_bus(sc->sc_tag, I2C_F_POLL);
|
||||
aprint_error_dev(sc->sc_dev, "%s: failed to read rtc\n",
|
||||
__func__);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* Done with I2C */
|
||||
iic_release_bus(sc->sc_tag, I2C_F_POLL);
|
||||
|
||||
uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
|
||||
*tp = v;
|
||||
|
||||
aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n",
|
||||
__func__, v);
|
||||
|
||||
return (1);
|
||||
}
|
||||
|
||||
static int
|
||||
dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t)
|
||||
{
|
||||
const struct dsrtc_model * const dm = &sc->sc_model;
|
||||
size_t buflen = dm->dm_rtc_size + 2;
|
||||
uint8_t buf[buflen];
|
||||
|
||||
KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0);
|
||||
KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4);
|
||||
|
||||
buf[0] = dm->dm_rtc_start;
|
||||
buf[1] = (t >> 0) & 0xff;
|
||||
buf[2] = (t >> 8) & 0xff;
|
||||
buf[3] = (t >> 16) & 0xff;
|
||||
buf[4] = (t >> 24) & 0xff;
|
||||
buf[5] = 0;
|
||||
|
||||
if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) {
|
||||
aprint_error_dev(sc->sc_dev, "%s: failed to acquire I2C bus\n",
|
||||
__func__);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* send data */
|
||||
if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address,
|
||||
&buf, buflen, NULL, 0, I2C_F_POLL)) {
|
||||
iic_release_bus(sc->sc_tag, I2C_F_POLL);
|
||||
aprint_error_dev(sc->sc_dev, "%s: failed to set time\n",
|
||||
__func__);
|
||||
return (0);
|
||||
}
|
||||
|
||||
iic_release_bus(sc->sc_tag, I2C_F_POLL);
|
||||
|
||||
return (1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: ds1307reg.h,v 1.3 2012/01/07 15:03:11 phx Exp $ */
|
||||
/* $NetBSD: ds1307reg.h,v 1.4 2012/02/23 20:59:19 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2003 Wasabi Systems, Inc.
|
||||
|
|
@ -44,33 +44,62 @@
|
|||
|
||||
#define DS1307_ADDR 0x68 /* Fixed I2C Slave Address */
|
||||
|
||||
#define DS1307_SECONDS 0x00
|
||||
#define DS1307_MINUTES 0x01
|
||||
#define DS1307_HOURS 0x02
|
||||
#define DS1307_DAY 0x03
|
||||
#define DS1307_DATE 0x04
|
||||
#define DS1307_MONTH 0x05
|
||||
#define DS1307_YEAR 0x06
|
||||
#define DS1307_CONTROL 0x07
|
||||
#define DS1307_NVRAM_START 0x08
|
||||
#define DS1307_NVRAM_END 0x3f
|
||||
#define DSXXXX_SECONDS 0x00
|
||||
#define DSXXXX_MINUTES 0x01
|
||||
#define DSXXXX_HOURS 0x02
|
||||
#define DSXXXX_DAY 0x03
|
||||
#define DSXXXX_DATE 0x04
|
||||
#define DSXXXX_MONTH 0x05
|
||||
#define DSXXXX_YEAR 0x06
|
||||
#define DSXXXX_RTC_SIZE 7
|
||||
|
||||
#define DS1307_CONTROL 0x07
|
||||
#define DS1307_RTC_START 0
|
||||
#define DS1307_RTC_SIZE DSXXXX_RTC_SIZE
|
||||
#define DS1307_NVRAM_START 0x08
|
||||
#define DS1307_NVRAM_SIZE 0x38
|
||||
|
||||
#define DS1339_CONTROL 0x0e
|
||||
#define DS1339_RTC_START 0
|
||||
#define DS1339_RTC_SIZE DSXXXX_RTC_SIZE
|
||||
#define DS1339_NVRAM_START 0
|
||||
#define DS1339_NVRAM_SIZE 0
|
||||
|
||||
#define DS1672_CNTR1 0x00
|
||||
#define DS1672_CNTR2 0x01
|
||||
#define DS1672_CNTR3 0x02
|
||||
#define DS1672_CNTR4 0x03
|
||||
#define DS1672_CONTROL 0x04
|
||||
#define DS1672_TRICKLE 0x05
|
||||
|
||||
#define DS1672_RTC_START 0
|
||||
#define DS1672_RTC_SIZE 4
|
||||
#define DS1672_NVRAM_START 0
|
||||
#define DS1672_NVRAM_SIZE 0
|
||||
|
||||
#define DS3232_CONTROL 0x0e
|
||||
#define DS3232_CSR 0x0f
|
||||
#define DS3232_RTC_START 0
|
||||
#define DS3232_RTC_SIZE DSXXXX_RTC_SIZE
|
||||
#define DS3232_NVRAM_START 0x14
|
||||
#define DS3232_NVRAM_SIZE 0xec
|
||||
|
||||
#define DS1307_NRTC_REGS 7
|
||||
#define DS1307_NVRAM_SIZE ((DS1307_NVRAM_END - DS1307_NVRAM_START) + 1)
|
||||
|
||||
/*
|
||||
* Bit definitions.
|
||||
*/
|
||||
#define DSXXXX_SECONDS_MASK 0x7f
|
||||
#define DSXXXX_MINUTES_MASK 0x7f
|
||||
#define DSXXXX_HOURS_12HRS_MODE (1u << 6) /* Set for 12 hour mode */
|
||||
#define DSXXXX_HOURS_12HRS_PM (1u << 5) /* If 12 hr mode, set = PM */
|
||||
#define DSXXXX_HOURS_12MASK 0x1f
|
||||
#define DSXXXX_HOURS_24MASK 0x3f
|
||||
#define DSXXXX_DAY_MASK 0x07
|
||||
#define DSXXXX_DATE_MASK 0x3f
|
||||
#define DSXXXX_MONTH_MASK 0x1f
|
||||
#define DSXXXX_MONTH_CENTURY 0x80
|
||||
|
||||
#define DS1307_SECONDS_CH (1u << 7) /* Clock Hold */
|
||||
#define DS1307_SECONDS_MASK 0x7f
|
||||
#define DS1307_MINUTES_MASK 0x7f
|
||||
#define DS1307_HOURS_12HRS_MODE (1u << 6) /* Set for 12 hour mode */
|
||||
#define DS1307_HOURS_12HRS_PM (1u << 5) /* If 12 hr mode, set = PM */
|
||||
#define DS1307_HOURS_12MASK 0x1f
|
||||
#define DS1307_HOURS_24MASK 0x3f
|
||||
#define DS1307_DAY_MASK 0x07
|
||||
#define DS1307_DATE_MASK 0x3f
|
||||
#define DS1307_MONTH_MASK 0x1f
|
||||
#define DS1307_CONTROL_OUT (1u << 7) /* OSC/OUT pin value */
|
||||
#define DS1307_CONTROL_SQWE (1u << 4) /* Enable square wave output */
|
||||
#define DS1307_CONTROL_1HZ 0
|
||||
|
|
@ -78,4 +107,6 @@
|
|||
#define DS1307_CONTROL_8192HZ 2
|
||||
#define DS1307_CONTROL_32768HZ 3
|
||||
|
||||
#define DSXXXX_CONTROL_DOSC (1u << 7) /* Disable Oscillator */
|
||||
|
||||
#endif /* _DEV_I2C_DS1307REG_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue