Define a couple more framebuffer control bits.
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@ -1,4 +1,4 @@
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/* $NetBSD: btreg.h,v 1.2 1994/11/20 20:51:55 deraadt Exp $ */
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/* $NetBSD: btreg.h,v 1.3 1996/02/27 00:09:23 pk Exp $ */
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/*
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* Copyright (c) 1993
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@ -78,3 +78,60 @@ struct bt_regs {
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u_int bt_ctrl; /* control register */
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u_int bt_omap; /* overlay (cursor) map register */
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};
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#define BT_INIT(bt) do { /* whatever this means.. */ \
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(bt)->bt_addr = 0x06; /* command reg */ \
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(bt)->bt_ctrl = 0x73; /* overlay plane */ \
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(bt)->bt_addr = 0x04; /* read mask */ \
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(bt)->bt_ctrl = 0xff; /* color planes */ \
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} while(0)
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#define BT_UNBLANK(bt, x) do { \
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/* restore color 0 (and R of color 1) */ \
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(bt)->bt_addr = 0; \
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(bt)->bt_cmap = (x); \
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/* restore read mask */ \
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BT_INIT(bt); \
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} while(0)
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#define BT_BLANK(bt) do { \
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(bt)->bt_addr = 0x06; /* command reg */ \
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(bt)->bt_ctrl = 0x70; /* overlay plane */ \
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(bt)->bt_addr = 0x04; /* read mask */ \
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(bt)->bt_ctrl = 0x00; /* color planes */ \
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/* Set color 0 to black -- note that this overwrites R of color 1. */\
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(bt)->bt_addr = 0; \
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(bt)->bt_cmap = 0; \
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/* restore read mask */ \
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BT_INIT(bt); \
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} while(0)
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/*
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* Sbus framebuffer control look like this (usually at offset 0x400000).
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*/
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struct fbcontrol {
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struct bt_regs fbc_dac;
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u_char fbc_ctrl;
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u_char fbc_status;
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u_char fbc_cursor_start;
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u_char fbc_cursor_end;
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u_char fbc_vcontrol[12]; /* 12 bytes of video timing goo */
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};
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/* fbc_ctrl bits: */
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#define FBC_IENAB 0x80 /* Interrupt enable */
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#define FBC_VENAB 0x40 /* Video enable */
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#define FBC_TIMING 0x20 /* Master timing enable */
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#define FBC_CURSOR 0x10 /* Cursor compare enable */
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#define FBC_XTALMSK 0x0c /* Xtal select (0,1,2,test) */
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#define FBC_DIVMSK 0x03 /* Divisor (1,2,3,4) */
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/* fbc_status bits: */
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#define FBS_INTR 0x80 /* Interrupt pending */
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#define FBS_MSENSE 0x70 /* Monitor sense mask */
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#define FBS_1024X768 0x10
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#define FBS_1152X900 0x30
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#define FBS_1280X1024 0x40
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#define FBS_1600X1280 0x50
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#define FBS_ID_MASK 0x0f /* ID mask */
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#define FBS_ID_COLOR 0x01
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#define FBS_ID_MONO 0x02
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#define FBS_ID_MONO_ECL 0x03 /* ? */
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