update for new bus.h
This commit is contained in:
cgd
parent
8f5cf31b8a
commit
2f614ee518
@ -1,4 +1,4 @@
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/* $NetBSD: tc_bus_mem.c,v 1.7 1996/07/09 00:55:33 cgd Exp $ */
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/* $NetBSD: tc_bus_mem.c,v 1.8 1996/10/22 21:34:19 cgd Exp $ */
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/*
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* Copyright (c) 1996 Carnegie-Mellon University.
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@ -41,65 +41,159 @@
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#include <machine/bus.h>
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#include <dev/tc/tcvar.h>
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int tc_mem_map __P((void *, bus_mem_addr_t, bus_mem_size_t,
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int, bus_mem_handle_t *));
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void tc_mem_unmap __P((void *, bus_mem_handle_t,
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bus_mem_size_t));
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int tc_mem_subregion __P((void *, bus_mem_handle_t, bus_mem_size_t,
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bus_mem_size_t, bus_mem_handle_t *));
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u_int8_t tc_mem_read_1 __P((void *, bus_mem_handle_t,
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bus_mem_size_t));
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u_int16_t tc_mem_read_2 __P((void *, bus_mem_handle_t,
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bus_mem_size_t));
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u_int32_t tc_mem_read_4 __P((void *, bus_mem_handle_t,
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bus_mem_size_t));
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u_int64_t tc_mem_read_8 __P((void *, bus_mem_handle_t,
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bus_mem_size_t));
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void tc_mem_write_1 __P((void *, bus_mem_handle_t,
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bus_mem_size_t, u_int8_t));
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void tc_mem_write_2 __P((void *, bus_mem_handle_t,
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bus_mem_size_t, u_int16_t));
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void tc_mem_write_4 __P((void *, bus_mem_handle_t,
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bus_mem_size_t, u_int32_t));
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void tc_mem_write_8 __P((void *, bus_mem_handle_t,
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bus_mem_size_t, u_int64_t));
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/* mapping/unmapping */
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int tc_mem_map __P((void *, bus_addr_t, bus_size_t, int,
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bus_space_handle_t *));
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void tc_mem_unmap __P((void *, bus_space_handle_t, bus_size_t));
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int tc_mem_subregion __P((void *, bus_space_handle_t, bus_size_t,
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bus_size_t, bus_space_handle_t *));
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/* XXX DOES NOT BELONG */
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vm_offset_t tc_XXX_dmamap __P((void *));
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/* allocation/deallocation */
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int tc_mem_alloc __P((void *, bus_addr_t, bus_addr_t, bus_size_t,
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bus_size_t, bus_addr_t, int, bus_addr_t *,
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bus_space_handle_t *));
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void tc_mem_free __P((void *, bus_space_handle_t, bus_size_t));
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void
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tc_bus_mem_init(bc, memv)
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bus_chipset_tag_t bc;
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/* read (single) */
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u_int8_t tc_mem_read_1 __P((void *, bus_space_handle_t, bus_size_t));
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u_int16_t tc_mem_read_2 __P((void *, bus_space_handle_t, bus_size_t));
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u_int32_t tc_mem_read_4 __P((void *, bus_space_handle_t, bus_size_t));
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u_int64_t tc_mem_read_8 __P((void *, bus_space_handle_t, bus_size_t));
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/* read multiple */
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void tc_mem_read_multi_1 __P((void *, bus_space_handle_t,
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bus_size_t, u_int8_t *, bus_size_t));
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void tc_mem_read_multi_2 __P((void *, bus_space_handle_t,
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bus_size_t, u_int16_t *, bus_size_t));
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void tc_mem_read_multi_4 __P((void *, bus_space_handle_t,
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bus_size_t, u_int32_t *, bus_size_t));
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void tc_mem_read_multi_8 __P((void *, bus_space_handle_t,
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bus_size_t, u_int64_t *, bus_size_t));
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/* read region */
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void tc_mem_read_region_1 __P((void *, bus_space_handle_t,
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bus_size_t, u_int8_t *, bus_size_t));
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void tc_mem_read_region_2 __P((void *, bus_space_handle_t,
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bus_size_t, u_int16_t *, bus_size_t));
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void tc_mem_read_region_4 __P((void *, bus_space_handle_t,
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bus_size_t, u_int32_t *, bus_size_t));
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void tc_mem_read_region_8 __P((void *, bus_space_handle_t,
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bus_size_t, u_int64_t *, bus_size_t));
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/* write (single) */
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void tc_mem_write_1 __P((void *, bus_space_handle_t, bus_size_t,
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u_int8_t));
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void tc_mem_write_2 __P((void *, bus_space_handle_t, bus_size_t,
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u_int16_t));
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void tc_mem_write_4 __P((void *, bus_space_handle_t, bus_size_t,
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u_int32_t));
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void tc_mem_write_8 __P((void *, bus_space_handle_t, bus_size_t,
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u_int64_t));
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/* write multiple */
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void tc_mem_write_multi_1 __P((void *, bus_space_handle_t,
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bus_size_t, const u_int8_t *, bus_size_t));
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void tc_mem_write_multi_2 __P((void *, bus_space_handle_t,
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bus_size_t, const u_int16_t *, bus_size_t));
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void tc_mem_write_multi_4 __P((void *, bus_space_handle_t,
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bus_size_t, const u_int32_t *, bus_size_t));
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void tc_mem_write_multi_8 __P((void *, bus_space_handle_t,
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bus_size_t, const u_int64_t *, bus_size_t));
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/* write region */
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void tc_mem_write_region_1 __P((void *, bus_space_handle_t,
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bus_size_t, const u_int8_t *, bus_size_t));
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void tc_mem_write_region_2 __P((void *, bus_space_handle_t,
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bus_size_t, const u_int16_t *, bus_size_t));
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void tc_mem_write_region_4 __P((void *, bus_space_handle_t,
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bus_size_t, const u_int32_t *, bus_size_t));
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void tc_mem_write_region_8 __P((void *, bus_space_handle_t,
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bus_size_t, const u_int64_t *, bus_size_t));
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/* barrier */
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void tc_mem_barrier __P((void *, bus_space_handle_t,
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bus_size_t, bus_size_t, int));
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static struct alpha_bus_space tc_mem_space = {
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/* cookie */
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NULL,
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/* mapping/unmapping */
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tc_mem_map,
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tc_mem_unmap,
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tc_mem_subregion,
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/* allocation/deallocation */
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tc_mem_alloc,
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tc_mem_free,
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/* read (single) */
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tc_mem_read_1,
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tc_mem_read_2,
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tc_mem_read_4,
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tc_mem_read_8,
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/* read multi */
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tc_mem_read_multi_1,
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tc_mem_read_multi_2,
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tc_mem_read_multi_4,
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tc_mem_read_multi_8,
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/* read region */
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tc_mem_read_region_1,
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tc_mem_read_region_2,
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tc_mem_read_region_4,
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tc_mem_read_region_8,
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/* write (single) */
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tc_mem_write_1,
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tc_mem_write_2,
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tc_mem_write_4,
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tc_mem_write_8,
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/* write multi */
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tc_mem_write_multi_1,
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tc_mem_write_multi_2,
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tc_mem_write_multi_4,
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tc_mem_write_multi_8,
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/* write region */
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tc_mem_write_region_1,
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tc_mem_write_region_2,
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tc_mem_write_region_4,
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tc_mem_write_region_8,
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/* set multi */
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/* XXX IMPLEMENT */
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/* set region */
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/* XXX IMPLEMENT */
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/* copy */
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/* XXX IMPLEMENT */
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/* barrier */
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tc_mem_barrier,
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};
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bus_space_tag_t
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tc_bus_mem_init(memv)
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void *memv;
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{
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bus_space_tag_t h = &tc_mem_space;
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bc->bc_m_v = memv;
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bc->bc_m_map = tc_mem_map;
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bc->bc_m_unmap = tc_mem_unmap;
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bc->bc_m_subregion = tc_mem_subregion;
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bc->bc_mr1 = tc_mem_read_1;
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bc->bc_mr2 = tc_mem_read_2;
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bc->bc_mr4 = tc_mem_read_4;
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bc->bc_mr8 = tc_mem_read_8;
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bc->bc_mw1 = tc_mem_write_1;
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bc->bc_mw2 = tc_mem_write_2;
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bc->bc_mw4 = tc_mem_write_4;
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bc->bc_mw8 = tc_mem_write_8;
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/* XXX DOES NOT BELONG */
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bc->bc_XXX_dmamap = tc_XXX_dmamap;
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h->abs_cookie = memv;
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return (h);
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}
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int
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tc_mem_map(v, memaddr, memsize, cacheable, memhp)
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void *v;
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bus_mem_addr_t memaddr;
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bus_mem_size_t memsize;
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bus_addr_t memaddr;
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bus_size_t memsize;
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int cacheable;
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bus_mem_handle_t *memhp;
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bus_space_handle_t *memhp;
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{
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if (memaddr & 0x7)
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@ -114,18 +208,18 @@ tc_mem_map(v, memaddr, memsize, cacheable, memhp)
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void
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tc_mem_unmap(v, memh, memsize)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t memsize;
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bus_space_handle_t memh;
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bus_size_t memsize;
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{
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/* XXX nothing to do. */
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/* XXX XX XXX nothing to do. */
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}
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int
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tc_mem_subregion(v, memh, offset, size, nmemh)
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void *v;
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bus_mem_handle_t memh, *nmemh;
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bus_mem_size_t offset, size;
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bus_space_handle_t memh, *nmemh;
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bus_size_t offset, size;
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{
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/* Disallow subregioning that would make the handle unaligned. */
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@ -140,15 +234,39 @@ tc_mem_subregion(v, memh, offset, size, nmemh)
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return (0);
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}
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int
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tc_mem_alloc(v, rstart, rend, size, align, boundary, cacheable, addrp, bshp)
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void *v;
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bus_addr_t rstart, rend, *addrp;
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bus_size_t size, align, boundary;
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int cacheable;
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bus_space_handle_t *bshp;
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{
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/* XXX XXX XXX XXX XXX XXX */
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panic("tc_mem_alloc unimplemented");
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}
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void
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tc_mem_free(v, bsh, size)
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void *v;
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bus_space_handle_t bsh;
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bus_size_t size;
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{
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/* XXX XXX XXX XXX XXX XXX */
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panic("tc_mem_free unimplemented");
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}
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u_int8_t
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tc_mem_read_1(v, memh, off)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t off;
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bus_space_handle_t memh;
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bus_size_t off;
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{
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volatile u_int8_t *p;
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alpha_mb();
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alpha_mb(); /* XXX XXX XXX */
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if ((memh & TC_SPACE_SPARSE) != 0)
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panic("tc_mem_read_1 not implemented for sparse space");
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@ -160,12 +278,12 @@ tc_mem_read_1(v, memh, off)
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u_int16_t
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tc_mem_read_2(v, memh, off)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t off;
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bus_space_handle_t memh;
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bus_size_t off;
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{
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volatile u_int16_t *p;
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alpha_mb();
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alpha_mb(); /* XXX XXX XXX */
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if ((memh & TC_SPACE_SPARSE) != 0)
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panic("tc_mem_read_2 not implemented for sparse space");
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@ -177,12 +295,12 @@ tc_mem_read_2(v, memh, off)
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u_int32_t
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tc_mem_read_4(v, memh, off)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t off;
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bus_space_handle_t memh;
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bus_size_t off;
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{
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volatile u_int32_t *p;
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alpha_mb();
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alpha_mb(); /* XXX XXX XXX */
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if ((memh & TC_SPACE_SPARSE) != 0)
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/* Nothing special to do for 4-byte sparse space accesses */
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@ -195,12 +313,12 @@ tc_mem_read_4(v, memh, off)
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u_int64_t
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tc_mem_read_8(v, memh, off)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t off;
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bus_space_handle_t memh;
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bus_size_t off;
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{
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volatile u_int64_t *p;
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alpha_mb();
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alpha_mb(); /* XXX XXX XXX */
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if ((memh & TC_SPACE_SPARSE) != 0)
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panic("tc_mem_read_8 not implemented for sparse space");
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@ -209,11 +327,50 @@ tc_mem_read_8(v, memh, off)
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return (*p);
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}
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#define tc_mem_read_multi_N(BYTES,TYPE) \
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void \
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__abs_c(tc_mem_read_multi_,BYTES)(v, h, o, a, c) \
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void *v; \
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bus_space_handle_t h; \
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bus_size_t o, c; \
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TYPE *a; \
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{ \
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\
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while (c-- > 0) { \
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tc_mem_barrier(v, h, o, sizeof(*a), BUS_BARRIER_READ); \
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*a++ = __abs_c(tc_mem_read_,BYTES)(v, h, o); \
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} \
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}
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tc_mem_read_multi_N(1,u_int8_t)
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tc_mem_read_multi_N(2,u_int16_t)
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tc_mem_read_multi_N(4,u_int32_t)
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tc_mem_read_multi_N(8,u_int64_t)
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#define tc_mem_read_region_N(BYTES,TYPE) \
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void \
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__abs_c(tc_mem_read_region_,BYTES)(v, h, o, a, c) \
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void *v; \
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bus_space_handle_t h; \
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bus_size_t o, c; \
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TYPE *a; \
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{ \
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\
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while (c-- > 0) { \
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*a++ = __abs_c(tc_mem_read_,BYTES)(v, h, o); \
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o += sizeof(*a); \
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} \
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}
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tc_mem_read_region_N(1,u_int8_t)
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tc_mem_read_region_N(2,u_int16_t)
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tc_mem_read_region_N(4,u_int32_t)
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tc_mem_read_region_N(8,u_int64_t)
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void
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tc_mem_write_1(v, memh, off, val)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t off;
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bus_space_handle_t memh;
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bus_size_t off;
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u_int8_t val;
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{
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@ -236,14 +393,14 @@ tc_mem_write_1(v, memh, off, val)
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p = (u_int8_t *)(memh + off);
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*p = val;
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}
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alpha_mb();
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alpha_mb(); /* XXX XXX XXX */
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}
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void
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tc_mem_write_2(v, memh, off, val)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t off;
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bus_space_handle_t memh;
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bus_size_t off;
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u_int16_t val;
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{
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@ -266,14 +423,14 @@ tc_mem_write_2(v, memh, off, val)
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p = (u_int16_t *)(memh + off);
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*p = val;
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}
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alpha_mb();
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alpha_mb(); /* XXX XXX XXX */
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}
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void
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tc_mem_write_4(v, memh, off, val)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t off;
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bus_space_handle_t memh;
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bus_size_t off;
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u_int32_t val;
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{
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volatile u_int32_t *p;
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@ -284,14 +441,14 @@ tc_mem_write_4(v, memh, off, val)
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else
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p = (u_int32_t *)(memh + off);
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*p = val;
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alpha_mb();
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alpha_mb(); /* XXX XXX XXX */
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}
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void
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tc_mem_write_8(v, memh, off, val)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t off;
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bus_space_handle_t memh;
|
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bus_size_t off;
|
||||
u_int64_t val;
|
||||
{
|
||||
volatile u_int64_t *p;
|
||||
@ -301,14 +458,57 @@ tc_mem_write_8(v, memh, off, val)
|
||||
|
||||
p = (u_int64_t *)(memh + off);
|
||||
*p = val;
|
||||
alpha_mb();
|
||||
alpha_mb(); /* XXX XXX XXX */
|
||||
}
|
||||
#define tc_mem_write_multi_N(BYTES,TYPE) \
|
||||
void \
|
||||
__abs_c(tc_mem_write_multi_,BYTES)(v, h, o, a, c) \
|
||||
void *v; \
|
||||
bus_space_handle_t h; \
|
||||
bus_size_t o, c; \
|
||||
const TYPE *a; \
|
||||
{ \
|
||||
\
|
||||
while (c-- > 0) { \
|
||||
__abs_c(tc_mem_write_,BYTES)(v, h, o, *a++); \
|
||||
tc_mem_barrier(v, h, o, sizeof(*a), BUS_BARRIER_WRITE); \
|
||||
} \
|
||||
}
|
||||
tc_mem_write_multi_N(1,u_int8_t)
|
||||
tc_mem_write_multi_N(2,u_int16_t)
|
||||
tc_mem_write_multi_N(4,u_int32_t)
|
||||
tc_mem_write_multi_N(8,u_int64_t)
|
||||
|
||||
/* XXX DOES NOT BELONG */
|
||||
vm_offset_t
|
||||
tc_XXX_dmamap(addr)
|
||||
void *addr;
|
||||
#define tc_mem_write_region_N(BYTES,TYPE) \
|
||||
void \
|
||||
__abs_c(tc_mem_write_region_,BYTES)(v, h, o, a, c) \
|
||||
void *v; \
|
||||
bus_space_handle_t h; \
|
||||
bus_size_t o, c; \
|
||||
const TYPE *a; \
|
||||
{ \
|
||||
\
|
||||
while (c-- > 0) { \
|
||||
__abs_c(tc_mem_write_,BYTES)(v, h, o, *a); \
|
||||
o += sizeof(*a); \
|
||||
a++; \
|
||||
} \
|
||||
}
|
||||
tc_mem_write_region_N(1,u_int8_t)
|
||||
tc_mem_write_region_N(2,u_int16_t)
|
||||
tc_mem_write_region_N(4,u_int32_t)
|
||||
tc_mem_write_region_N(8,u_int64_t)
|
||||
|
||||
void
|
||||
tc_mem_barrier(v, h, o, l, f)
|
||||
void *v;
|
||||
bus_space_handle_t h;
|
||||
bus_size_t o, l;
|
||||
int f;
|
||||
{
|
||||
|
||||
return (vtophys((vm_offset_t)addr));
|
||||
if ((f & BUS_BARRIER_READ) != 0)
|
||||
alpha_mb();
|
||||
else if ((f & BUS_BARRIER_WRITE) != 0)
|
||||
alpha_wmb();
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: tc_machdep.h,v 1.2 1996/07/09 00:55:35 cgd Exp $ */
|
||||
/* $NetBSD: tc_machdep.h,v 1.3 1996/10/22 21:34:22 cgd Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
|
||||
@ -91,5 +91,4 @@ typedef int32_t tc_offset_t;
|
||||
#define TC_PHYS_TO_UNCACHED(addr) \
|
||||
(addr)
|
||||
|
||||
void tc_bus_io_init __P((bus_chipset_tag_t bc, void *iov));;
|
||||
void tc_bus_mem_init __P((bus_chipset_tag_t bc, void *memv));;
|
||||
bus_space_tag_t tc_bus_mem_init __P((void *memv));;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: tcasic.c,v 1.10 1996/10/13 03:00:39 christos Exp $ */
|
||||
/* $NetBSD: tcasic.c,v 1.11 1996/10/22 21:34:24 cgd Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
|
||||
@ -87,7 +87,6 @@ tcasicattach(parent, self, aux)
|
||||
struct tcbus_attach_args tba;
|
||||
void (*intr_setup) __P((void));
|
||||
void (*iointr) __P((void *, unsigned long));
|
||||
struct alpha_bus_chipset bc;
|
||||
|
||||
printf("\n");
|
||||
tcasicfound = 1;
|
||||
@ -131,9 +130,7 @@ tcasicattach(parent, self, aux)
|
||||
panic("tcasicattach: bad cputype");
|
||||
}
|
||||
|
||||
tc_bus_io_init(&bc, NULL);
|
||||
tc_bus_mem_init(&bc, NULL);
|
||||
tba.tba_bc = &bc;
|
||||
tba.tba_memt = tc_bus_mem_init(NULL);
|
||||
|
||||
(*intr_setup)();
|
||||
set_iointr(iointr);
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: if_fta.c,v 1.6 1996/10/13 01:38:38 christos Exp $ */
|
||||
/* $NetBSD: if_fta.c,v 1.7 1996/10/22 21:37:26 cgd Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1996 Matt Thomas <matt@3am-software.com>
|
||||
@ -86,18 +86,22 @@ pdq_tc_attach(
|
||||
pdq_softc_t * const sc = (pdq_softc_t *) self;
|
||||
struct tc_attach_args * const ta = (struct tc_attach_args *) aux;
|
||||
|
||||
sc->sc_bc = ta->ta_bc;
|
||||
/*
|
||||
* NOTE: sc_bc is an alias for sc_csrtag and sc_membase is an
|
||||
* alias for sc_csrhandle. sc_iobase is not used in this front-end.
|
||||
*/
|
||||
sc->sc_csrtag = ta->ta_memt;
|
||||
bcopy(sc->sc_dev.dv_xname, sc->sc_if.if_xname, IFNAMSIZ);
|
||||
sc->sc_if.if_flags = 0;
|
||||
sc->sc_if.if_softc = sc;
|
||||
|
||||
if (bus_mem_map(sc->sc_bc, ta->ta_addr + PDQ_TC_CSR_OFFSET,
|
||||
PDQ_TC_CSR_SPACE, 0, &sc->sc_membase)) {
|
||||
if (bus_space_map(sc->sc_csrtag, ta->ta_addr + PDQ_TC_CSR_OFFSET,
|
||||
PDQ_TC_CSR_SPACE, 0, &sc->sc_csrhandle)) {
|
||||
printf("\n%s: can't map card memory!\n", sc->sc_dev.dv_xname);
|
||||
return;
|
||||
}
|
||||
|
||||
sc->sc_pdq = pdq_initialize(sc->sc_bc, sc->sc_membase,
|
||||
sc->sc_pdq = pdq_initialize(sc->sc_csrtag, sc->sc_csrhandle,
|
||||
sc->sc_if.if_xname, 0,
|
||||
(void *) sc, PDQ_DEFTA);
|
||||
if (sc->sc_pdq == NULL) {
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: tc.c,v 1.19 1996/10/13 01:38:39 christos Exp $ */
|
||||
/* $NetBSD: tc.c,v 1.20 1996/10/22 21:37:29 cgd Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
|
||||
@ -129,7 +129,7 @@ tcattach(parent, self, aux)
|
||||
*/
|
||||
strncpy(ta.ta_modname, builtin->tcb_modname, TC_ROM_LLEN);
|
||||
#ifdef __alpha__ /* XXX */
|
||||
ta.ta_bc = tba->tba_bc;
|
||||
ta.ta_memt = tba->tba_memt;
|
||||
#endif
|
||||
ta.ta_modname[TC_ROM_LLEN] = '\0';
|
||||
ta.ta_slot = builtin->tcb_slot;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: tcvar.h,v 1.6 1996/09/09 16:39:44 cgd Exp $ */
|
||||
/* $NetBSD: tcvar.h,v 1.7 1996/10/22 21:37:31 cgd Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1995 Carnegie-Mellon University.
|
||||
@ -92,7 +92,7 @@ typedef enum {
|
||||
struct tcbus_attach_args {
|
||||
char *tba_busname; /* XXX should be common */
|
||||
#ifdef __alpha__ /* XXX */
|
||||
bus_chipset_tag_t tba_bc; /* XXX should be common */
|
||||
bus_space_tag_t tba_memt;
|
||||
#endif
|
||||
|
||||
/* Bus information */
|
||||
@ -114,7 +114,7 @@ struct tcbus_attach_args {
|
||||
*/
|
||||
struct tc_attach_args {
|
||||
#ifdef __alpha__ /* XXX */
|
||||
bus_chipset_tag_t ta_bc;
|
||||
bus_space_tag_t ta_memt;
|
||||
#endif
|
||||
|
||||
char ta_modname[TC_ROM_LLEN+1];
|
||||
|
||||
Loading…
Reference in New Issue
Block a user