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Add Amlogic SD/MMC driver.

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This commit is contained in:
jmcneill 2015-03-08 12:44:55 +00:00
parent af9a28ef89
commit 2eb101f7a5
7 changed files with 796 additions and 38 deletions
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58
sys/arch/arm/amlogic/amlogic_board.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: amlogic_board.c,v 1.8 2015/03/07 21:32:47 jmcneill Exp $ */
/* $NetBSD: amlogic_board.c,v 1.9 2015/03/08 12:44:55 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@ -29,7 +29,7 @@
#include "opt_amlogic.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: amlogic_board.c,v 1.8 2015/03/07 21:32:47 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: amlogic_board.c,v 1.9 2015/03/08 12:44:55 jmcneill Exp $");
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/param.h>
@ -191,47 +191,47 @@ amlogic_eth_init(void)
void
amlogic_rng_init(void)
{
printf("%s: GATING0 = %#x, GATING3 = %#x\n", __func__,
CBUS_READ(EE_CLK_GATING0_REG), CBUS_READ(EE_CLK_GATING3_REG));
CBUS_WRITE(EE_CLK_GATING0_REG,
CBUS_READ(EE_CLK_GATING0_REG) | EE_CLK_GATING0_RNG);
CBUS_WRITE(EE_CLK_GATING3_REG,
CBUS_READ(EE_CLK_GATING3_REG) | EE_CLK_GATING3_RNG);
printf("%s: GATING0 = %#x, GATING3 = %#x\n", __func__,
CBUS_READ(EE_CLK_GATING0_REG), CBUS_READ(EE_CLK_GATING3_REG));
}
void
amlogic_sdhc_init(void)
{
/* CARD -> SDHC pin mux settings */
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_5_REG, 0, 0x00007c00);
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_4_REG, 0, 0x7c000000);
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_2_REG, 0, 0x0000fc00);
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_8_REG, 0, 0x00000600);
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_2_REG, 0x000000f0, 0);
const uint32_t pupd_mask = __BITS(25,20); /* CARD_0-CARD_5 */
CBUS_SET_CLEAR(CBUS_REG(0x203c), pupd_mask, 0); /* PU/PD */
CBUS_SET_CLEAR(CBUS_REG(0x204a), pupd_mask, 0); /* PU/PD-EN */
const uint32_t io_mask = __BITS(27,22); /* CARD_0-CARD_5 */
CBUS_SET_CLEAR(CBUS_REG(0x200c), io_mask, 0); /* OEN */
/* XXX ODROID-C1 specific */
const uint32_t pwr_mask = __BIT(31); /* CARD_8 */
CBUS_SET_CLEAR(CBUS_REG(0x201c), 0, pwr_mask); /* O */
CBUS_SET_CLEAR(CBUS_REG(0x201b), 0, pwr_mask); /* OEN */
const uint32_t cd_mask = __BIT(29);
CBUS_SET_CLEAR(CBUS_REG(0x201b), cd_mask, 0); /* OEN */
/* enable SDHC clk */
CBUS_WRITE(EE_CLK_GATING0_REG,
CBUS_READ(EE_CLK_GATING0_REG) | EE_CLK_GATING0_SDHC);
}
int
amlogic_sdhc_select_port(int port)
{
switch (port) {
case AMLOGIC_SDHC_PORT_B:
/* CARD -> SDHC pin mux settings */
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_5_REG, 0, 0x00007c00);
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_4_REG, 0, 0x7c000000);
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_2_REG, 0, 0x0000fc00);
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_8_REG, 0, 0x00000600);
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_2_REG, 0x000000f0, 0);
break;
case AMLOGIC_SDHC_PORT_C:
/* BOOT -> SDHC pin mux settings */
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_2_REG, 0, 0x04c000f0);
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_5_REG, 0, 0x00007c00);
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_6_REG, 0, 0xff000000);
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_4_REG, 0x70000000, 0);
CBUS_SET_CLEAR(PERIPHS_PIN_MUX_7_REG, 0x000c0000, 0);
break;
default:
return EINVAL;
}
return 0;
}
static void
amlogic_usbphy_clkgate_enable(int port)
{

20
sys/arch/arm/amlogic/amlogic_crureg.h
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@ -1,4 +1,4 @@
/* $NetBSD: amlogic_crureg.h,v 1.6 2015/03/07 21:32:47 jmcneill Exp $ */
/* $NetBSD: amlogic_crureg.h,v 1.7 2015/03/08 12:44:55 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@ -75,6 +75,8 @@
#define PREG_CTLREG0_ADDR_REG CBUS_REG(0x2000)
#define PREG_CTLREG0_ADDR_CLKRATE __BITS(9,4)
#define PREG_PAD_GPIO0_EN_N_REG CBUS_REG(0x200c)
#define PERIPHS_PIN_MUX_0_REG CBUS_REG(0x202c)
#define PERIPHS_PIN_MUX_1_REG CBUS_REG(0x202d)
#define PERIPHS_PIN_MUX_2_REG CBUS_REG(0x202e)
@ -86,9 +88,25 @@
#define PERIPHS_PIN_MUX_8_REG CBUS_REG(0x2034)
#define PERIPHS_PIN_MUX_9_REG CBUS_REG(0x2035)
#define PAD_PULL_UP_6_REG CBUS_REG(0x2039)
#define PAD_PULL_UP_0_REG CBUS_REG(0x203a)
#define PAD_PULL_UP_1_REG CBUS_REG(0x203b)
#define PAD_PULL_UP_2_REG CBUS_REG(0x203c)
#define PAD_PULL_UP_3_REG CBUS_REG(0x203d)
#define PAD_PULL_UP_4_REG CBUS_REG(0x203e)
#define PAD_PULL_UP_5_REG CBUS_REG(0x203f)
#define RAND64_ADDR0_REG CBUS_REG(0x2040)
#define RAND64_ADDR1_REG CBUS_REG(0x2041)
#define PAD_PULL_UP_EN_0_REG CBUS_REG(0x2048)
#define PAD_PULL_UP_EN_1_REG CBUS_REG(0x2049)
#define PAD_PULL_UP_EN_2_REG CBUS_REG(0x204a)
#define PAD_PULL_UP_EN_3_REG CBUS_REG(0x204b)
#define PAD_PULL_UP_EN_4_REG CBUS_REG(0x204c)
#define PAD_PULL_UP_EN_5_REG CBUS_REG(0x204d)
#define PAD_PULL_UP_EN_6_REG CBUS_REG(0x204e)
#define PREI_USB_PHY_A_CFG_REG CBUS_REG(0x2200)
#define PREI_USB_PHY_A_CTRL_REG CBUS_REG(0x2201)
#define PREI_USB_PHY_A_ADP_BC_REG CBUS_REG(0x2203)

10
sys/arch/arm/amlogic/amlogic_io.c
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@ -1,4 +1,4 @@
/* $NetBSD: amlogic_io.c,v 1.5 2015/03/07 21:34:25 jmcneill Exp $ */
/* $NetBSD: amlogic_io.c,v 1.6 2015/03/08 12:44:55 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@ -29,7 +29,7 @@
#include "opt_amlogic.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: amlogic_io.c,v 1.5 2015/03/07 21:34:25 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: amlogic_io.c,v 1.6 2015/03/08 12:44:55 jmcneill Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -75,10 +75,10 @@ static const struct amlogic_locators amlogic_locators[] = {
AMLOGIC_USB1_OFFSET, AMLOGIC_USB_SIZE, 1, AMLOGIC_INTR_USB1 },
{ "awge",
AMLOGIC_GMAC_OFFSET, AMLOGIC_GMAC_SIZE, NOPORT, AMLOGIC_INTR_GMAC },
#if notyet
{ "amlogicsdhc",
AMLOGIC_SDHC_OFFSET, AMLOGIC_SDHC_SIZE, 0, AMLOGIC_INTR_SDHC },
#endif
AMLOGIC_SDHC_OFFSET, AMLOGIC_SDHC_SIZE, 1, AMLOGIC_INTR_SDHC },
{ "amlogicsdhc",
AMLOGIC_SDHC_OFFSET, AMLOGIC_SDHC_SIZE, 2, AMLOGIC_INTR_SDHC },
};
int

3
sys/arch/arm/amlogic/amlogic_reg.h
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@ -1,4 +1,4 @@
/* $NetBSD: amlogic_reg.h,v 1.7 2015/03/07 21:32:47 jmcneill Exp $ */
/* $NetBSD: amlogic_reg.h,v 1.8 2015/03/08 12:44:55 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@ -55,6 +55,7 @@
#define AMLOGIC_AOBUS_OFFSET 0x08100000
#define AMLOGIC_AO_RTI_PIN_MUX_OFFSET 0x08100014
#define AMLOGIC_GPIOAO_OFFSET 0x08100024
#define AMLOGIC_UART0AO_OFFSET 0x081004c0

585
sys/arch/arm/amlogic/amlogic_sdhc.c Normal file
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@ -0,0 +1,585 @@
/* $NetBSD: amlogic_sdhc.c,v 1.1 2015/03/08 12:44:55 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include "locators.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: amlogic_sdhc.c,v 1.1 2015/03/08 12:44:55 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/device.h>
#include <sys/intr.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <dev/sdmmc/sdmmcvar.h>
#include <dev/sdmmc/sdmmcchip.h>
#include <dev/sdmmc/sdmmc_ioreg.h>
#include <arm/amlogic/amlogic_reg.h>
#include <arm/amlogic/amlogic_sdhcreg.h>
#include <arm/amlogic/amlogic_var.h>
static int amlogic_sdhc_match(device_t, cfdata_t, void *);
static void amlogic_sdhc_attach(device_t, device_t, void *);
static void amlogic_sdhc_attach_i(device_t);
static int amlogic_sdhc_intr(void *);
struct amlogic_sdhc_softc {
device_t sc_dev;
bus_space_tag_t sc_bst;
bus_space_handle_t sc_bsh;
bus_dma_tag_t sc_dmat;
void *sc_ih;
device_t sc_sdmmc_dev;
kmutex_t sc_intr_lock;
kcondvar_t sc_intr_cv;
uint32_t sc_intr_ista;
};
CFATTACH_DECL_NEW(amlogic_sdhc, sizeof(struct amlogic_sdhc_softc),
amlogic_sdhc_match, amlogic_sdhc_attach, NULL, NULL);
static int amlogic_sdhc_host_reset(sdmmc_chipset_handle_t);
static uint32_t amlogic_sdhc_host_ocr(sdmmc_chipset_handle_t);
static int amlogic_sdhc_host_maxblklen(sdmmc_chipset_handle_t);
static int amlogic_sdhc_card_detect(sdmmc_chipset_handle_t);
static int amlogic_sdhc_write_protect(sdmmc_chipset_handle_t);
static int amlogic_sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t);
static int amlogic_sdhc_bus_clock(sdmmc_chipset_handle_t, int);
static int amlogic_sdhc_bus_width(sdmmc_chipset_handle_t, int);
static int amlogic_sdhc_bus_rod(sdmmc_chipset_handle_t, int);
static void amlogic_sdhc_exec_command(sdmmc_chipset_handle_t,
struct sdmmc_command *);
static void amlogic_sdhc_card_enable_intr(sdmmc_chipset_handle_t, int);
static void amlogic_sdhc_card_intr_ack(sdmmc_chipset_handle_t);
static int amlogic_sdhc_set_clock(struct amlogic_sdhc_softc *, u_int);
static int amlogic_sdhc_wait_idle(struct amlogic_sdhc_softc *);
static int amlogic_sdhc_wait_ista(struct amlogic_sdhc_softc *, uint32_t, int);
static struct sdmmc_chip_functions amlogic_sdhc_chip_functions = {
.host_reset = amlogic_sdhc_host_reset,
.host_ocr = amlogic_sdhc_host_ocr,
.host_maxblklen = amlogic_sdhc_host_maxblklen,
.card_detect = amlogic_sdhc_card_detect,
.write_protect = amlogic_sdhc_write_protect,
.bus_power = amlogic_sdhc_bus_power,
.bus_clock = amlogic_sdhc_bus_clock,
.bus_width = amlogic_sdhc_bus_width,
.bus_rod = amlogic_sdhc_bus_rod,
.exec_command = amlogic_sdhc_exec_command,
.card_enable_intr = amlogic_sdhc_card_enable_intr,
.card_intr_ack = amlogic_sdhc_card_intr_ack,
};
#define SDHC_WRITE(sc, reg, val) \
bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
#define SDHC_READ(sc, reg) \
bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
static int
amlogic_sdhc_match(device_t parent, cfdata_t cf, void *aux)
{
return 1;
}
static void
amlogic_sdhc_attach(device_t parent, device_t self, void *aux)
{
struct amlogic_sdhc_softc * const sc = device_private(self);
struct amlogicio_attach_args * const aio = aux;
const struct amlogic_locators * const loc = &aio->aio_loc;
sc->sc_dev = self;
sc->sc_bst = aio->aio_core_bst;
sc->sc_dmat = aio->aio_dmat;
bus_space_subregion(aio->aio_core_bst, aio->aio_bsh,
loc->loc_offset, loc->loc_size, &sc->sc_bsh);
mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO);
cv_init(&sc->sc_intr_cv, "sdhcintr");
amlogic_sdhc_init();
if (amlogic_sdhc_select_port(loc->loc_port) != 0) {
aprint_error(": couldn't select port %d\n", loc->loc_port);
return;
}
aprint_naive("\n");
aprint_normal(": SDHC controller\n");
sc->sc_ih = intr_establish(loc->loc_intr, IPL_BIO, IST_EDGE,
amlogic_sdhc_intr, sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(self, "couldn't establish interrupt %d\n",
loc->loc_intr);
return;
}
aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
config_interrupts(self, amlogic_sdhc_attach_i);
}
static void
amlogic_sdhc_attach_i(device_t self)
{
struct amlogic_sdhc_softc *sc = device_private(self);
struct sdmmcbus_attach_args saa;
amlogic_sdhc_host_reset(sc);
amlogic_sdhc_bus_width(sc, 1);
memset(&saa, 0, sizeof(saa));
saa.saa_busname = "sdmmc";
saa.saa_sct = &amlogic_sdhc_chip_functions;
saa.saa_dmat = sc->sc_dmat;
saa.saa_sch = sc;
saa.saa_clkmin = 400;
saa.saa_clkmax = 50000;
saa.saa_caps = SMC_CAPS_4BIT_MODE|
SMC_CAPS_8BIT_MODE|
SMC_CAPS_SD_HIGHSPEED|
SMC_CAPS_MMC_HIGHSPEED|
SMC_CAPS_AUTO_STOP|
SMC_CAPS_DMA;
sc->sc_sdmmc_dev = config_found(self, &saa, NULL);
}
static int
amlogic_sdhc_intr(void *priv)
{
struct amlogic_sdhc_softc *sc = priv;
uint32_t ista;
mutex_enter(&sc->sc_intr_lock);
ista = SDHC_READ(sc, SD_ISTA_REG);
if (!ista) {
mutex_exit(&sc->sc_intr_lock);
return 0;
}
SDHC_WRITE(sc, SD_ISTA_REG, ista);
sc->sc_intr_ista |= ista;
cv_broadcast(&sc->sc_intr_cv);
mutex_exit(&sc->sc_intr_lock);
return 1;
}
static int
amlogic_sdhc_set_clock(struct amlogic_sdhc_softc *sc, u_int freq)
{
uint32_t clkc;
uint32_t clk2;
u_int pll_freq, clk_div;
clkc = SDHC_READ(sc, SD_CLKC_REG);
clkc &= ~SD_CLKC_TX_CLK_ENABLE;
clkc &= ~SD_CLKC_RX_CLK_ENABLE;
clkc &= ~SD_CLKC_SD_CLK_ENABLE;
SDHC_WRITE(sc, SD_CLKC_REG, clkc);
clkc &= ~SD_CLKC_MOD_CLK_ENABLE;
SDHC_WRITE(sc, SD_CLKC_REG, clkc);
if (freq == 0)
return 0;
clkc &= ~SD_CLKC_CLK_DIV;
clkc &= ~SD_CLKC_CLK_IN_SEL;
clkc |= __SHIFTIN(SD_CLKC_CLK_IN_SEL_FCLK_DIV3,
SD_CLKC_CLK_IN_SEL);
pll_freq = amlogic_get_rate_fixed() / 1000; /* 2.55GHz */
pll_freq /= 3; /* for SD_CLKC_CLK_IN_SEL_FCLK_DIV3 */
clk_div = howmany(pll_freq, freq);
clkc |= __SHIFTIN(clk_div - 1, SD_CLKC_CLK_DIV);
SDHC_WRITE(sc, SD_CLKC_REG, clkc);
clkc |= SD_CLKC_MOD_CLK_ENABLE;
SDHC_WRITE(sc, SD_CLKC_REG, clkc);
clkc |= SD_CLKC_TX_CLK_ENABLE;
clkc |= SD_CLKC_RX_CLK_ENABLE;
clkc |= SD_CLKC_SD_CLK_ENABLE;
SDHC_WRITE(sc, SD_CLKC_REG, clkc);
clk2 = SDHC_READ(sc, SD_CLK2_REG);
clk2 &= ~SD_CLK2_SD_CLK_PHASE;
clk2 |= __SHIFTIN(1, SD_CLK2_SD_CLK_PHASE);
clk2 &= ~SD_CLK2_RX_CLK_PHASE;
const u_int act_freq = pll_freq / clk_div;
if (act_freq > 45000) {
clk2 |= __SHIFTIN(15, SD_CLK2_RX_CLK_PHASE);
/* XXX 11 for 1.8V */
} else if (act_freq > 5000) {
clk2 |= __SHIFTIN(23, SD_CLK2_RX_CLK_PHASE);
} else if (act_freq > 1000) {
clk2 |= __SHIFTIN(55, SD_CLK2_RX_CLK_PHASE);
} else {
clk2 |= __SHIFTIN(1061, SD_CLK2_RX_CLK_PHASE);
}
SDHC_WRITE(sc, SD_CLK2_REG, clk2);
return 0;
}
static int
amlogic_sdhc_wait_idle(struct amlogic_sdhc_softc *sc)
{
int i;
for (i = 0; i < 1000000; i++) {
const uint32_t stat = SDHC_READ(sc, SD_STAT_REG);
const uint32_t esta = SDHC_READ(sc, SD_ESTA_REG);
if ((stat & SD_STAT_BUSY) == 0 &&
(esta & SD_ESTA_BUSY) == 0)
return 0;
delay(1);
}
return EBUSY;
}
static int
amlogic_sdhc_wait_ista(struct amlogic_sdhc_softc *sc, uint32_t mask, int timeout)
{
int retry, error;
KASSERT(mutex_owned(&sc->sc_intr_lock));
if (sc->sc_intr_ista & mask)
return 0;
retry = timeout / hz;
while (retry > 0) {
error = cv_timedwait(&sc->sc_intr_cv, &sc->sc_intr_lock, hz);
if (error && error != EWOULDBLOCK)
return error;
if (sc->sc_intr_ista & mask)
return 0;
--retry;
}
return ETIMEDOUT;
}
static int
amlogic_sdhc_host_reset(sdmmc_chipset_handle_t sch)
{
struct amlogic_sdhc_softc *sc = sch;
uint32_t enhc;
SDHC_WRITE(sc, SD_SRST_REG,
SD_SRST_MAIN_CTRL | SD_SRST_TX_FIFO | SD_SRST_RX_FIFO |
SD_SRST_DPHY_TX | SD_SRST_DPHY_RX | SD_SRST_DMA_IF);
delay(50);
SDHC_WRITE(sc, SD_SRST_REG, 0);
delay(10);
SDHC_WRITE(sc, SD_CNTL_REG,
__SHIFTIN(0x7, SD_CNTL_TX_ENDIAN_CTRL) |
__SHIFTIN(0x7, SD_CNTL_RX_ENDIAN_CTRL) |
__SHIFTIN(0xf, SD_CNTL_RX_PERIOD) |
__SHIFTIN(0x7f, SD_CNTL_RX_TIMEOUT));
SDHC_WRITE(sc, SD_CLKC_REG,
SDHC_READ(sc, SD_CLKC_REG) & ~SD_CLKC_MEM_PWR);
SDHC_WRITE(sc, SD_PDMA_REG,
__SHIFTIN(7, SD_PDMA_TX_BURST_LEN) |
__SHIFTIN(49, SD_PDMA_TXFIFO_THRESHOLD) |
__SHIFTIN(15, SD_PDMA_RX_BURST_LEN) |
__SHIFTIN(7, SD_PDMA_RXFIFO_THRESHOLD) |
SD_PDMA_DMA_URGENT);
SDHC_WRITE(sc, SD_MISC_REG,
__SHIFTIN(7, SD_MISC_TXSTART_THRESHOLD) |
__SHIFTIN(5, SD_MISC_WCRC_ERR_PATTERN) |
__SHIFTIN(2, SD_MISC_WCRC_OK_PATTERN));
enhc = SDHC_READ(sc, SD_ENHC_REG);
enhc &= ~SD_ENHC_RXFIFO_THRESHOLD;
enhc |= __SHIFTIN(63, SD_ENHC_RXFIFO_THRESHOLD);
enhc &= ~SD_ENHC_DMA_RX_RESP;
enhc |= SD_ENHC_DMA_TX_RESP;
enhc &= ~SD_ENHC_SDIO_IRQ_PERIOD;
enhc |= __SHIFTIN(12, SD_ENHC_SDIO_IRQ_PERIOD);
enhc &= ~SD_ENHC_RX_TIMEOUT;
enhc |= __SHIFTIN(0xff, SD_ENHC_RX_TIMEOUT);
SDHC_WRITE(sc, SD_ENHC_REG, enhc);
SDHC_WRITE(sc, SD_ICTL_REG, 0);
SDHC_WRITE(sc, SD_ISTA_REG, SD_INT_CLEAR);
return 0;
}
static uint32_t
amlogic_sdhc_host_ocr(sdmmc_chipset_handle_t sch)
{
return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V;
}
static int
amlogic_sdhc_host_maxblklen(sdmmc_chipset_handle_t sch)
{
return 512;
}
static int
amlogic_sdhc_card_detect(sdmmc_chipset_handle_t sch)
{
return 1;
}
static int
amlogic_sdhc_write_protect(sdmmc_chipset_handle_t sch)
{
return 0;
}
static int
amlogic_sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)
{
return 0;
}
static int
amlogic_sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
{
struct amlogic_sdhc_softc *sc = sch;
return amlogic_sdhc_set_clock(sc, freq);
}
static int
amlogic_sdhc_bus_width(sdmmc_chipset_handle_t sch, int width)
{
struct amlogic_sdhc_softc *sc = sch;
uint32_t cntl;
cntl = SDHC_READ(sc, SD_CNTL_REG);
cntl &= ~SD_CNTL_DAT_TYPE;
switch (width) {
case 1:
cntl |= __SHIFTIN(0, SD_CNTL_DAT_TYPE);
break;
case 4:
cntl |= __SHIFTIN(1, SD_CNTL_DAT_TYPE);
break;
case 8:
cntl |= __SHIFTIN(2, SD_CNTL_DAT_TYPE);
break;
default:
return EINVAL;
}
SDHC_WRITE(sc, SD_CNTL_REG, cntl);
return 0;
}
static int
amlogic_sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on)
{
return ENOTSUP;
}
static void
amlogic_sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
{
struct amlogic_sdhc_softc *sc = sch;
uint32_t cmdval = 0, cntl, srst, pdma;
int i;
KASSERT(cmd->c_blklen <= 512);
mutex_enter(&sc->sc_intr_lock);
/* Filter SDIO commands */
switch (cmd->c_opcode) {
case SD_IO_SEND_OP_COND:
case SD_IO_RW_DIRECT:
case SD_IO_RW_EXTENDED:
cmd->c_error = EINVAL;
goto done;
}
while (SDHC_READ(sc, SD_STAT_REG) & __BIT(24))
delay(10);
if (cmd->c_opcode == MMC_STOP_TRANSMISSION)
cmdval |= SD_SEND_DATA_STOP;
if (cmd->c_flags & SCF_RSP_PRESENT)
cmdval |= SD_SEND_COMMAND_HAS_RESP;
if (cmd->c_flags & SCF_RSP_136) {
cmdval |= SD_SEND_RESPONSE_LENGTH;
cmdval |= SD_SEND_RESPONSE_NO_CRC;
}
if ((cmd->c_flags & SCF_RSP_CRC) == 0)
cmdval |= SD_SEND_RESPONSE_NO_CRC;
cntl = SDHC_READ(sc, SD_CNTL_REG);
cntl &= ~SD_CNTL_PACK_LEN;
if (cmd->c_datalen > 0) {
unsigned int nblks;
cmdval |= SD_SEND_COMMAND_HAS_DATA;
if (!ISSET(cmd->c_flags, SCF_CMD_READ)) {
cmdval |= SD_SEND_DATA_DIRECTION;
}
nblks = cmd->c_datalen / cmd->c_blklen;
if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0)
++nblks;
cntl |= __SHIFTIN(cmd->c_blklen & 0x1ff, SD_CNTL_PACK_LEN);
cmdval |= __SHIFTIN(nblks - 1, SD_SEND_TOTAL_PACK);
}
SDHC_WRITE(sc, SD_CNTL_REG, cntl);
SDHC_WRITE(sc, SD_ISTA_REG, SD_INT_CLEAR);
sc->sc_intr_ista = 0;
SDHC_WRITE(sc, SD_ICTL_REG,
SD_INT_ERROR | SD_INT_DATA_COMPLETE | SD_INT_RESP_COMPLETE |
SD_INT_DMA_DONE);
pdma = SDHC_READ(sc, SD_PDMA_REG);
pdma |= SD_PDMA_DMA_MODE;
SDHC_WRITE(sc, SD_PDMA_REG, pdma);
SDHC_WRITE(sc, SD_ARGU_REG, cmd->c_arg);
cmd->c_error = amlogic_sdhc_wait_idle(sc);
if (cmd->c_error) {
goto done;
}
if (cmd->c_datalen > 0) {
KASSERT(cmd->c_dmamap->dm_nsegs == 1);
KASSERT(cmd->c_dmamap->dm_segs[0].ds_len == cmd->c_datalen);
SDHC_WRITE(sc, SD_ADDR_REG, cmd->c_dmamap->dm_segs[0].ds_addr);
}
cmd->c_resid = cmd->c_datalen;
SDHC_WRITE(sc, SD_SEND_REG, cmdval | cmd->c_opcode);
if (cmd->c_flags & SCF_RSP_PRESENT) {
cmd->c_error = amlogic_sdhc_wait_ista(sc,
SD_INT_ERROR | SD_INT_RESP_COMPLETE, hz * 10);
if (cmd->c_error == 0 && (sc->sc_intr_ista & SD_INT_ERROR)) {
if (sc->sc_intr_ista & SD_INT_TIMEOUT) {
cmd->c_error = ETIMEDOUT;
} else {
cmd->c_error = EIO;
}
}
if (cmd->c_error) {
goto done;
}
}
if (cmd->c_datalen > 0) {
cmd->c_error = amlogic_sdhc_wait_ista(sc,
SD_INT_ERROR | SD_INT_DMA_DONE, hz * 10);
if (cmd->c_error == 0 &&
(sc->sc_intr_ista & SD_INT_ERROR)) {
cmd->c_error = ETIMEDOUT;
}
if (cmd->c_error) {
goto done;
}
}
if (cmd->c_flags & SCF_RSP_PRESENT) {
pdma = SDHC_READ(sc, SD_PDMA_REG);
pdma &= ~SD_PDMA_DMA_MODE;
if (cmd->c_flags & SCF_RSP_136) {
for (i = 4; i >= 1; i--) {
pdma &= ~SD_PDMA_PIO_RDRESP;
pdma |= __SHIFTIN(i, SD_PDMA_PIO_RDRESP);
SDHC_WRITE(sc, SD_PDMA_REG, pdma);
cmd->c_resp[i - 1] = SDHC_READ(sc, SD_ARGU_REG);
}
if (cmd->c_flags & SCF_RSP_CRC) {
cmd->c_resp[0] = (cmd->c_resp[0] >> 8) |
(cmd->c_resp[1] << 24);
cmd->c_resp[1] = (cmd->c_resp[1] >> 8) |
(cmd->c_resp[2] << 24);
cmd->c_resp[2] = (cmd->c_resp[2] >> 8) |
(cmd->c_resp[3] << 24);
cmd->c_resp[3] = (cmd->c_resp[3] >> 8);
}
} else {
pdma &= ~SD_PDMA_PIO_RDRESP;
pdma |= __SHIFTIN(0, SD_PDMA_PIO_RDRESP);
SDHC_WRITE(sc, SD_PDMA_REG, pdma);
cmd->c_resp[0] = SDHC_READ(sc, SD_ARGU_REG);
}
}
done:
cmd->c_flags |= SCF_ITSDONE;
SDHC_WRITE(sc, SD_ISTA_REG, SD_INT_CLEAR);
SDHC_WRITE(sc, SD_ICTL_REG, 0);
srst = SDHC_READ(sc, SD_SRST_REG);
srst |= (SD_SRST_TX_FIFO | SD_SRST_RX_FIFO);
SDHC_WRITE(sc, SD_SRST_REG, srst);
mutex_exit(&sc->sc_intr_lock);
}
static void
amlogic_sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable)
{
}
static void
amlogic_sdhc_card_intr_ack(sdmmc_chipset_handle_t sch)
{
}

150
sys/arch/arm/amlogic/amlogic_sdhcreg.h Normal file
View File

@ -0,0 +1,150 @@
/* $NetBSD: amlogic_sdhcreg.h,v 1.1 2015/03/08 12:44:55 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _ARM_AMLOGIC_SDHCREG_H
#define _ARM_AMLOGIC_SDHCREG_H
#define SD_ARGU_REG 0x00
#define SD_SEND_REG 0x04
#define SD_CNTL_REG 0x08
#define SD_STAT_REG 0x0c
#define SD_CLKC_REG 0x10
#define SD_ADDR_REG 0x14
#define SD_PDMA_REG 0x18
#define SD_MISC_REG 0x1c
#define SD_DATA_REG 0x20
#define SD_ICTL_REG 0x24
#define SD_ISTA_REG 0x28
#define SD_SRST_REG 0x2c
#define SD_ESTA_REG 0x30
#define SD_ENHC_REG 0x34
#define SD_CLK2_REG 0x38
#define SD_SEND_TOTAL_PACK __BITS(31,16)
#define SD_SEND_R1B __BIT(12)
#define SD_SEND_DATA_STOP __BIT(11)
#define SD_SEND_DATA_DIRECTION __BIT(10)
#define SD_SEND_RESPONSE_NO_CRC __BIT(9)
#define SD_SEND_RESPONSE_LENGTH __BIT(8)
#define SD_SEND_COMMAND_HAS_DATA __BIT(7)
#define SD_SEND_COMMAND_HAS_RESP __BIT(6)
#define SD_SEND_COMMAND_INDEX __BITS(5,0)
#define SD_CNTL_TX_ENDIAN_CTRL __BITS(31,29)
#define SD_CNTL_DAT0_INT_SEL __BIT(28)
#define SD_CNTL_SDIO_IRQ_MODE __BIT(27)
#define SD_CNTL_RX_ENDIAN_CTRL __BITS(26,24)
#define SD_CNTL_RX_PERIOD __BITS(23,20)
#define SD_CNTL_RX_TIMEOUT __BITS(19,13)
#define SD_CNTL_PACK_LEN __BITS(12,4)
#define SD_CNTL_TX_CRC_CHECK __BIT(3)
#define SD_CNTL_DDR_MODE __BIT(2)
#define SD_CNTL_DAT_TYPE __BITS(1,0)
#define SD_STAT_DAT_HI __BITS(23,20)
#define SD_STAT_TXFIFO_COUNT __BITS(19,13)
#define SD_STAT_RXFIFO_COUNT __BITS(12,6)
#define SD_STAT_CMD __BIT(5)
#define SD_STAT_DAT_LO __BITS(4,1)
#define SD_STAT_BUSY __BIT(0)
#define SD_CLKC_MEM_PWR __BITS(26,25)
#define SD_CLKC_MEM_PWR_ON 0
#define SD_CLKC_MEM_PWR_OFF 3
#define SD_CLKC_CLK_JIC __BIT(24)
#define SD_CLKC_CLK_IN_SEL __BITS(17,16)
#define SD_CLKC_CLK_IN_SEL_OSC 0
#define SD_CLKC_CLK_IN_SEL_FCLK_DIV4 1
#define SD_CLKC_CLK_IN_SEL_FCLK_DIV3 2
#define SD_CLKC_CLK_IN_SEL_FCLK_DIV5 3
#define SD_CLKC_MOD_CLK_ENABLE __BIT(15)
#define SD_CLKC_SD_CLK_ENABLE __BIT(14)
#define SD_CLKC_RX_CLK_ENABLE __BIT(13)
#define SD_CLKC_TX_CLK_ENABLE __BIT(12)
#define SD_CLKC_CLK_DIV __BITS(11,0)
#define SD_PDMA_TXFIFO_FILL __BIT(31)
#define SD_PDMA_RXFIFO_MANUAL_FLUSH __BITS(30,29)
#define SD_PDMA_TXFIFO_THRESHOLD __BITS(28,22)
#define SD_PDMA_RXFIFO_THRESHOLD __BITS(21,15)
#define SD_PDMA_RX_BURST_LEN __BITS(14,10)
#define SD_PDMA_TX_BURST_LEN __BITS(9,5)
#define SD_PDMA_DMA_URGENT __BIT(4)
#define SD_PDMA_PIO_RDRESP __BITS(3,1)
#define SD_PDMA_DMA_MODE __BIT(0)
#define SD_MISC_TXSTART_THRESHOLD __BITS(31,29)
#define SD_MISC_STOP_MODE __BIT(28)
#define SD_MISC_THREAD_ID __BITS(27,22)
#define SD_MISC_BURST_NUMBER __BITS(21,16)
#define SD_MISC_WCRC_OK_PATTERN __BITS(9,7)
#define SD_MISC_WCRC_ERR_PATTERN __BITS(6,4)
#define SD_ICTL_SDIO_DAT1 __BITS(17,16)
#define SD_INT_ADDL_SDIO_DAT1 __BIT(14)
#define SD_INT_TXFIFO __BIT(13)
#define SD_INT_RXFIFO __BIT(12)
#define SD_INT_DMA_DONE __BIT(11)
#define SD_INT_SDIO_DAT1 __BIT(10)
#define SD_INT_TXFIFO_THRES __BIT(9)
#define SD_INT_RXFIFO_THRES __BIT(8)
#define SD_INT_DATA_COMPLETE __BIT(7)
#define SD_INT_PACK_CRC_ERROR __BIT(6)
#define SD_INT_PACK_TIMEOUT __BIT(5)
#define SD_INT_PACK_COMPLETE __BIT(4)
#define SD_INT_DATA_BIT0_CHG __BIT(3)
#define SD_INT_RESP_CRC_ERROR __BIT(2)
#define SD_INT_RESP_TIMEOUT __BIT(1)
#define SD_INT_RESP_COMPLETE __BIT(0)
#define SD_INT_TIMEOUT (SD_INT_PACK_TIMEOUT | SD_INT_RESP_TIMEOUT)
#define SD_INT_CRC_ERROR (SD_INT_PACK_CRC_ERROR | SD_INT_RESP_CRC_ERROR)
#define SD_INT_ERROR (SD_INT_TIMEOUT | SD_INT_CRC_ERROR)
#define SD_INT_CLEAR 0x7fff
#define SD_SRST_DMA_IF __BIT(5)
#define SD_SRST_DPHY_TX __BIT(4)
#define SD_SRST_DPHY_RX __BIT(3)
#define SD_SRST_TX_FIFO __BIT(2)
#define SD_SRST_RX_FIFO __BIT(1)
#define SD_SRST_MAIN_CTRL __BIT(0)
#define SD_ENHC_RX_TIMEOUT __BITS(7,0)
#define SD_ENHC_SDIO_IRQ_PERIOD __BITS(15,8)
#define SD_ENHC_DMA_RX_RESP __BIT(16)
#define SD_ENHC_DMA_TX_RESP __BIT(17)
#define SD_ENHC_RXFIFO_THRESHOLD __BITS(24,18)
#define SD_ENHC_TXFIFO_THRESHOLD __BITS(31,25)
#define SD_ESTA_BUSY __BITS(13,11) /* XXX ??? */
#define SD_CLK2_RX_CLK_PHASE __BITS(11,0)
#define SD_CLK2_SD_CLK_PHASE __BITS(23,12)
#endif /* _ARM_AMLOGIC_SDHCREG_H */

8
sys/arch/arm/amlogic/amlogic_var.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: amlogic_var.h,v 1.5 2015/03/07 21:32:47 jmcneill Exp $ */
/* $NetBSD: amlogic_var.h,v 1.6 2015/03/08 12:44:55 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@ -60,8 +60,12 @@ void amlogic_cpufreq_init(void);
void amlogic_usbphy_init(int);
void amlogic_eth_init(void);
void amlogic_sdhc_init(void);
void amlogic_rng_init(void);
void amlogic_sdhc_init(void);
int amlogic_sdhc_select_port(int);
#define AMLOGIC_SDHC_PORT_B 1
#define AMLOGIC_SDHC_PORT_C 2
uint32_t amlogic_get_rate_xtal(void);
uint32_t amlogic_get_rate_sys(void);