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Move the hpcmips L1 cache disable hack up 

where another machine-specific hacks exists.

Note that no existing kernel seems to enable this option.
This commit is contained in:
maya 2018-03-07 15:52:43 +00:00
parent 1fa5c16d04
commit 2e66644133
1 changed files with 11 additions and 10 deletions
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21
sys/arch/mips/mips/locore.S
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@ -1,4 +1,4 @@
/* $NetBSD: locore.S,v 1.212 2018/03/07 15:49:45 maya Exp $ */
/* $NetBSD: locore.S,v 1.213 2018/03/07 15:52:43 maya Exp $ */
/*
* Copyright (c) 1992, 1993
@ -63,7 +63,7 @@
#include <mips/trap.h>
#include <mips/locore.h>
RCSID("$NetBSD: locore.S,v 1.212 2018/03/07 15:49:45 maya Exp $")
RCSID("$NetBSD: locore.S,v 1.213 2018/03/07 15:52:43 maya Exp $")
#include "assym.h"
@ -93,6 +93,15 @@ _C_LABEL(kernel_text):
mtc0 k0, MIPS_COP_0_STATUS
#endif
#ifdef HPCMIPS_L1CACHE_DISABLE
mfc0 t0, MIPS_COP_0_CONFIG
li t1, 0xfffffff8
and t0, t0, t1
or t0, 0x00000002 # XXX, KSEG0 is uncached
mtc0 t0, MIPS_COP_0_CONFIG
COP0_SYNC
#endif /* HPCMIPS_L1CACHE_DISABLE */
#ifdef MIPS64_OCTEON
//
// U-boot on the erlite starts all cpus at the kernel entry point.
@ -145,14 +154,6 @@ _C_LABEL(kernel_text):
mtc0 t0, MIPS_COP_0_STATUS # the fp coprocessor
COP0_SYNC
#endif /* !emips */
#ifdef HPCMIPS_L1CACHE_DISABLE
mfc0 t0, MIPS_COP_0_CONFIG
li t1, 0xfffffff8
and t0, t0, t1
or t0, 0x00000002 # XXX, KSEG0 is uncached
mtc0 t0, MIPS_COP_0_CONFIG
COP0_SYNC
#endif /* HPCMIPS_L1CACHE_DISABLE */
#else /* NOFPU */
mfc0 t0, MIPS_COP_0_STATUS
MFC0_HAZARD