Pull fixes from FreeBSD's rgephy.c:
Revision 1.9: > Make the rgephy driver advertise both 1000_FD and 1000_HD bits in > autoneg mode. A couple of the devices don't autoneg correctly unless > configured this way. Revision 1.11: > Due to the poor PHY documentation from RealTek I can't sure but I > think the RealTek PHY needs driver to set RGEPHY_BMCR_AUTOEN bit of > RGEPHY_MII_BMCR register and proper ANAR register setting for manual > media type selection. > This fixes long standing manual media type selection bug in rgephy(4).
This commit is contained in:
tsutsui
parent
898c6532b4
commit
2e0739074e
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@ -1,4 +1,4 @@
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/* $NetBSD: rgephy.c,v 1.12 2006/11/16 21:24:07 christos Exp $ */
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/* $NetBSD: rgephy.c,v 1.13 2006/11/28 13:36:29 tsutsui Exp $ */
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/*
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* Copyright (c) 2003
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@ -33,7 +33,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.12 2006/11/16 21:24:07 christos Exp $");
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__KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.13 2006/11/28 13:36:29 tsutsui Exp $");
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/*
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@ -140,7 +140,6 @@ rgephy_attach(struct device *parent, struct device *self, void *aux)
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#endif
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rgephy_mii_model = MII_MODEL(ma->mii_id2);
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PHY_RESET(sc);
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sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
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sc->mii_capabilities &= ~BMSR_ANEG;
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@ -171,6 +170,7 @@ rgephy_attach(struct device *parent, struct device *self, void *aux)
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#undef ADD
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#undef PRINT
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PHY_RESET(sc);
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aprint_normal("\n");
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}
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@ -181,7 +181,7 @@ rgephy_service(sc, mii, cmd)
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int cmd;
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int reg, speed, gig;
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int reg, speed, gig, anar;
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switch (cmd) {
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case MII_POLLSTAT:
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@ -211,6 +211,10 @@ rgephy_service(sc, mii, cmd)
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PHY_RESET(sc); /* XXX hardware bug work-around */
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anar = PHY_READ(sc, RGEPHY_MII_ANAR);
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anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
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RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10);
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_AUTO:
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#ifdef foo
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@ -227,28 +231,30 @@ rgephy_service(sc, mii, cmd)
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goto setit;
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case IFM_100_TX:
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speed = RGEPHY_S100;
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anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX;
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goto setit;
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case IFM_10_T:
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speed = RGEPHY_S10;
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anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10;
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setit:
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rgephy_loop(sc);
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if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
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speed |= RGEPHY_BMCR_FDX;
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gig = RGEPHY_1000CTL_AFD;
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anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10);
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} else {
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gig = RGEPHY_1000CTL_AHD;
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anar &=
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~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD);
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}
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PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
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PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
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PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE);
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) {
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PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
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PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
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PHY_WRITE(sc, RGEPHY_MII_BMCR, speed |
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RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
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break;
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PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
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PHY_WRITE(sc, RGEPHY_MII_BMCR,
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speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG);
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}
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/*
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* When settning the link manually, one side must
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@ -265,6 +271,8 @@ setit:
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PHY_WRITE(sc, RGEPHY_MII_1000CTL,
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gig|RGEPHY_1000CTL_MSE);
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}
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PHY_WRITE(sc, RGEPHY_MII_BMCR, speed |
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RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
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break;
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#ifdef foo
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case IFM_NONE:
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@ -371,12 +379,14 @@ rgephy_status(sc)
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}
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bmsr = PHY_READ(sc, RTK_GMEDIASTAT);
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if (bmsr & RTK_GMEDIASTAT_10MBPS)
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mii->mii_media_active |= IFM_10_T;
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if (bmsr & RTK_GMEDIASTAT_100MBPS)
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mii->mii_media_active |= IFM_100_TX;
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if (bmsr & RTK_GMEDIASTAT_1000MBPS)
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mii->mii_media_active |= IFM_1000_T;
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else if (bmsr & RTK_GMEDIASTAT_100MBPS)
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mii->mii_media_active |= IFM_100_TX;
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else if (bmsr & RTK_GMEDIASTAT_10MBPS)
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mii->mii_media_active |= IFM_10_T;
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else
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mii->mii_media_active |= IFM_NONE;
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if (bmsr & RTK_GMEDIASTAT_FDX)
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mii->mii_media_active |= IFM_FDX;
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@ -394,7 +404,8 @@ rgephy_mii_phy_auto(mii)
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PHY_WRITE(mii, RGEPHY_MII_ANAR,
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BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
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DELAY(1000);
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PHY_WRITE(mii, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AFD);
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PHY_WRITE(mii, RGEPHY_MII_1000CTL,
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RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD);
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DELAY(1000);
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PHY_WRITE(mii, RGEPHY_MII_BMCR,
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RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
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@ -432,8 +443,9 @@ rgephy_loop(struct mii_softc *sc)
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/*
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* Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
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* existing revisions of the 8169S/8110S chips need to be tuned in
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* order to reliably negotiate a 1000Mbps link. Later revs of the
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* chips may not require this software tuning.
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* order to reliably negotiate a 1000Mbps link. This is only needed
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* for rev 0 and rev 1 of the PHY. Later versions work without
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* any fixups.
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*/
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static void
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rgephy_load_dspcode(struct mii_softc *sc)
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