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Enable "shareable" access to the page table for armv7. PTE_SYNC only does

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a DSB now on an armv7 cpu and no longer needs to flush the cache line to ram.
This commit is contained in:
matt 2012-09-06 02:07:25 +00:00
parent 85489630e0
commit 2e04e0ecda
2 changed files with 6 additions and 2 deletions
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4
sys/arch/arm/arm/cpufunc_asm_armv7.S
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@ -71,6 +71,10 @@ END(armv7_tlb_flushID_SE)
ENTRY(armv7_setttb)
mrc p15, 0, r1, c0, c0, 5 @ get MPIDR
cmp r1, #0
orrlt r0, #0x5b @ MP, cachable (Normal in/out WB)
orrge r0, #0x1b @ Non-MP, cacheable, normal WB
mcr p15, 0, r0, c2, c0, 0 @ load new TTB
#ifdef MULTIPROCESSOR
mcr p15, 0, r0, c8, c3, 0 @ invalidate all I+D TLBs

4
sys/arch/arm/include/arm32/pmap.h
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@ -1,4 +1,4 @@
/* $NetBSD: pmap.h,v 1.107 2012/09/02 14:43:21 matt Exp $ */
/* $NetBSD: pmap.h,v 1.108 2012/09/06 02:07:25 matt Exp $ */
/*
* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@ -405,7 +405,7 @@ extern int pmap_needs_pte_sync;
#if (ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7 != 0) && (ARM_NMMUS == 1)
#define PMAP_INCLUDE_PTE_SYNC
#if (ARM_MMU_V7 > 0)
#define PMAP_NEEDS_PTE_SYNC 1
#define PMAP_NEEDS_PTE_SYNC 0
#else
#define PMAP_NEEDS_PTE_SYNC 1
#endif