A31 SMP support
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jmcneill
parent
36be35bfb0
commit
2ddb0e42ba
@ -41,7 +41,7 @@
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#include <arm/allwinner/awin_reg.h>
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#include <evbarm/awin/platform.h>
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RCSID("$NetBSD: awin_start.S,v 1.2 2014/09/25 07:59:29 matt Exp $")
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RCSID("$NetBSD: awin_start.S,v 1.3 2014/10/10 23:51:28 jmcneill Exp $")
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#if defined(VERBOSE_INIT_ARM)
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#define XPUTC(n) mov r0, n; bl xputc
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@ -150,7 +150,29 @@ _C_LABEL(awin_start):
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XPUTC2(#60)
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// Make sure the cache is flushed out to RAM for the other CPUs
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bl _C_LABEL(armv7_dcache_wbinv_all)
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bl a20_mpinit
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// Read SoC ID
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movw r5, #:lower16:(AWIN_CORE_PBASE+AWIN_SRAM_OFFSET)
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movt r5, #:upper16:(AWIN_CORE_PBASE+AWIN_SRAM_OFFSET)
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ldr r1, [r5, #AWIN_SRAM_VER_REG]
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orr r1, r1, AWIN_SRAM_VER_R_EN
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str r1, [r5, #AWIN_SRAM_VER_REG]
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dsb
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ldr r1, [r5, #AWIN_SRAM_VER_REG]
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lsr r1, r1, #16
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// MP init based on SoC ID
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#if defined(ALLWINNER_A20)
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movw r0, #AWIN_SRAM_VER_KEY_A20
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cmp r1, r0
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bleq a20_mpinit
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#endif
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#if defined(ALLWINNER_A31)
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movw r0, #AWIN_SRAM_VER_KEY_A31
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cmp r1, r0
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bleq a31_mpinit
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#endif
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XPUTC2(#62)
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#endif /* MULTIPROCESSOR */
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XPUTC2(#13)
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@ -178,6 +200,10 @@ a20_mpinit:
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movw r5, #:lower16:(AWIN_CORE_PBASE+AWIN_CPUCFG_OFFSET)
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movt r5, #:upper16:(AWIN_CORE_PBASE+AWIN_CPUCFG_OFFSET)
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XPUTC2(#65)
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XPUTC2(#50)
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XPUTC2(#48)
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#ifdef __ARMEB__
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setend le // everything here is little-endian
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#endif
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@ -258,6 +284,144 @@ ASEND(a20_mpinit)
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#ifndef KERNEL_BASES_EQUAL
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.popsection
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#endif
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#ifndef KERNEL_BASES_EQUAL
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.pushsection .text,"ax",%progbits
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#endif
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a31_mpinit:
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mov r4, lr // because we call gtmr_bootdelay
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movw r5, #:lower16:(AWIN_CORE_PBASE+AWIN_A31_CPUCFG_OFFSET)
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movt r5, #:upper16:(AWIN_CORE_PBASE+AWIN_A31_CPUCFG_OFFSET)
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movw r6, #:lower16:(AWIN_CORE_PBASE+AWIN_A31_PRCM_OFFSET)
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movt r6, #:upper16:(AWIN_CORE_PBASE+AWIN_A31_PRCM_OFFSET)
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XPUTC2(#65)
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XPUTC2(#51)
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XPUTC2(#49)
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#ifdef __ARMEB__
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setend le // everything here is little-endian
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#endif
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mov r12, #1 // CPU number
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a31_mpinit_cpu:
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XPUTC2(r12)
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/* Set where the other CPU(s) are going to execute */
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movw r1, #:lower16:cortex_mpstart
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movt r1, #:upper16:cortex_mpstart
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str r1, [r5, #AWIN_CPUCFG_PRIVATE_REG]
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dsb
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/* Assert CPU core reset */
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mov r1, #0
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mov r2, #0x40
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mul r7, r12, r2
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add r7, r7, #AWIN_A31_CPUCFG_CPU0_RST_CTRL_REG
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str r1, [r5, r7]
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dsb
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/* Ensure CPUX reset also invalidates its L1 caches */
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ldr r1, [r5, #AWIN_CPUCFG_GENCTRL_REG]
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mov r0, #1
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lsl r0, r0, r12
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bic r1, r1, r0
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str r1, [r5, #AWIN_CPUCFG_GENCTRL_REG]
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dsb
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/* Release power clamp */
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mov r1, #0xe7
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mov r2, #0x4
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mul r7, r12, r2
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add r7, r7, #AWIN_A31_PRCM_CPUX_PWR_CLAMP_REG
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str r1, [r6, r7]
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dsb
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mov r2, #0x40
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mul r7, r12, r2
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add r7, r7, #AWIN_A31_CPUCFG_CPU0_PWR_CLAMP_STATUS_REG
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1:
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ldr r1, [r5, r7]
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cmp r1, #0xe7
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bne 1b
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/* We need to wait (at least) 10ms */
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mov r0, #0x3b000 // 10.06ms
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bl _C_LABEL(gtmr_bootdelay) // endian-neutral
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/* Restore power clamp */
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mov r1, #0
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mov r2, #0x4
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mul r7, r12, r2
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add r7, r7, #AWIN_A31_PRCM_CPUX_PWR_CLAMP_REG
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str r1, [r6, r7]
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dsb
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mov r2, #0x40
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mul r7, r12, r2
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add r7, r7, #AWIN_A31_CPUCFG_CPU0_PWR_CLAMP_STATUS_REG
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1:
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ldr r1, [r5, r7]
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cmp r1, #0
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bne 1b
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/* We need to wait (at least) 10ms */
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mov r0, #0x3b000 // 10.06ms
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bl _C_LABEL(gtmr_bootdelay) // endian-neutral
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/* Clear power-off gating */
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ldr r1, [r6, #AWIN_A31_PRCM_PWROFF_GATING_REG]
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mov r0, #1
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lsl r0, r0, r12
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bic r1, r1, r0
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str r1, [r6, #AWIN_A31_PRCM_PWROFF_GATING_REG]
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dsb
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/* We need to wait (at least) 10ms */
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mov r0, #0x3b000 // 10.06ms
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bl _C_LABEL(gtmr_bootdelay) // endian-neutral
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/* Bring CPUX out of reset */
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mov r1, #(AWIN_A31_CPUCFG_RST_CTRL_CPU_RESET|AWIN_A31_CPUCFG_RST_CTRL_CORE_RESET)
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mov r2, #0x40
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mul r7, r12, r2
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add r7, r7, #AWIN_A31_CPUCFG_CPU0_RST_CTRL_REG
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str r1, [r5, r7]
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dsb
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/* If there is another CPU, start it */
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add r12, r12, #1
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cmp r12, #3
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ble a31_mpinit_cpu
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#ifdef __ARMEB__
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setend be // we're done with little endian
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#endif
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//
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// Wait up a second for CPU1-3 to hatch.
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//
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movw r6, #:lower16:arm_cpu_hatched
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movt r6, #:upper16:arm_cpu_hatched
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mov r5, #200 // 200 x 5ms
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1: dmb // memory barrier
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ldr r0, [r6] // load hatched
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tst r0, #0xe // our bits set yet?
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bxne r4 // yes, return
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subs r5, r5, #1 // decrement count
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bxeq r4 // 0? return
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mov r0, #0x1d800 // 5.03ms
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bl _C_LABEL(gtmr_bootdelay)
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b 1b
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ASEND(a31_mpinit)
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#ifndef KERNEL_BASES_EQUAL
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.popsection
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#endif
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#endif /* MULTIPROCESSOR */
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.Lmmu_init_table:
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