Define some extra configuration block bits used on the i82550 (a.k.a.
PRO 100/S), including the extended RFA format. Don't hard-code the RFA size to allow us to use the extended format in the future.
This commit is contained in:
thorpej
parent
876e40a10a
commit
2da55b9a39
@ -1,4 +1,4 @@
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/* $NetBSD: i82557.c,v 1.52 2001/05/22 15:29:30 thorpej Exp $ */
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/* $NetBSD: i82557.c,v 1.53 2001/06/02 01:04:01 thorpej Exp $ */
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/*-
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* Copyright (c) 1997, 1998, 1999, 2001 The NetBSD Foundation, Inc.
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@ -167,7 +167,17 @@ const u_int8_t fxp_cb_config_template[] = {
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0xf0, /* 18 */
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0x0, /* 19 */
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0x3f, /* 20 */
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0x5 /* 21 */
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0x5, /* 21 */
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0x0, /* 22 */
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0x0, /* 23 */
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0x0, /* 24 */
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0x0, /* 25 */
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0x0, /* 26 */
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0x0, /* 27 */
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0x0, /* 28 */
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0x0, /* 29 */
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0x0, /* 30 */
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0x0, /* 31 */
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};
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void fxp_mii_initmedia(struct fxp_softc *);
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@ -259,6 +269,9 @@ fxp_attach(struct fxp_softc *sc)
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callout_init(&sc->sc_callout);
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/* Start out using the standard RFA. */
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sc->sc_rfa_size = RFA_SIZE;
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/*
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* Enable some good stuff on i82558 and later.
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*/
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@ -1376,7 +1389,8 @@ fxp_init(struct ifnet *ifp)
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FXP_CB_COMMAND_EL);
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/* BIG_ENDIAN: no need to swap to store 0xffffffff */
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cbp->link_addr = 0xffffffff; /* (no) next command */
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cbp->byte_count = 22; /* (22) bytes to config */
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/* bytes in config block */
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cbp->byte_count = FXP_CONFIG_LEN;
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cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
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cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
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cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
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@ -1,4 +1,4 @@
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/* $NetBSD: i82557reg.h,v 1.9 2001/05/25 08:54:40 hannken Exp $ */
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/* $NetBSD: i82557reg.h,v 1.10 2001/06/02 01:04:01 thorpej Exp $ */
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/*-
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* Copyright (c) 1998, 1999, 2001 The NetBSD Foundation, Inc.
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@ -191,21 +191,23 @@ struct fxp_cb_config {
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volatile u_int16_t cb_status;
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volatile u_int16_t cb_command;
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volatile u_int32_t link_addr;
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volatile u_int8_t __FXP_BITFIELD2(byte_count:6, :2);
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volatile u_int8_t __FXP_BITFIELD3(rx_fifo_limit:4,
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/* Bytes 0 - 21 -- common to all i8255x */
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/*0*/ volatile u_int8_t __FXP_BITFIELD2(byte_count:6, :2);
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/*1*/ volatile u_int8_t __FXP_BITFIELD3(rx_fifo_limit:4,
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tx_fifo_limit:3,
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:1);
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volatile u_int8_t adaptive_ifs;
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volatile u_int8_t __FXP_BITFIELD5(mwi_enable:1, /* 8,9 */
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/*2*/ volatile u_int8_t adaptive_ifs;
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/*3*/ volatile u_int8_t __FXP_BITFIELD5(mwi_enable:1, /* 8,9 */
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type_enable:1, /* 8,9 */
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read_align_en:1, /* 8,9 */
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end_wr_on_cl:1, /* 8,9 */
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:4);
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volatile u_int8_t __FXP_BITFIELD2(rx_dma_bytecount:7,
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/*4*/ volatile u_int8_t __FXP_BITFIELD2(rx_dma_bytecount:7,
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:1);
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volatile u_int8_t __FXP_BITFIELD2(tx_dma_bytecount:7,
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/*5*/ volatile u_int8_t __FXP_BITFIELD2(tx_dma_bytecount:7,
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dma_mbce:1);
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volatile u_int8_t __FXP_BITFIELD8(late_scb:1, /* 7 */
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/*6*/ volatile u_int8_t __FXP_BITFIELD8(late_scb:1, /* 7 */
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direct_dma_dis:1, /* 8,9 */
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tno_int_or_tco_en:1, /* 7,9 */
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ci_int:1,
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@ -213,32 +215,33 @@ struct fxp_cb_config {
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ext_stats_dis:1, /* 8,9 */
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keep_overrun_rx:1,
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save_bf:1);
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volatile u_int8_t __FXP_BITFIELD5(disc_short_rx:1,
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/*7*/ volatile u_int8_t __FXP_BITFIELD6(disc_short_rx:1,
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underrun_retry:2,
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:3,
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:2,
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extended_rfd_en:1, /* 0 */
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two_frames:1, /* 8,9 */
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dyn_tbd:1); /* 8,9 */
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volatile u_int8_t __FXP_BITFIELD3(mediatype:1, /* 7 */
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/*8*/ volatile u_int8_t __FXP_BITFIELD3(mediatype:1, /* 7 */
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:6,
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csma_dis:1); /* 8,9 */
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volatile u_int8_t __FXP_BITFIELD6(tcp_udp_cksum:1,/* 9 */
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/*9*/ volatile u_int8_t __FXP_BITFIELD6(tcp_udp_cksum:1,/* 9 */
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:3,
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vlan_tco:1, /* 8,9 */
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link_wake_en:1, /* 8,9 */
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arp_wake_en:1, /* 8 */
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mc_wake_en:1); /* 8 */
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volatile u_int8_t __FXP_BITFIELD4(:3,
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/*10*/ volatile u_int8_t __FXP_BITFIELD4(:3,
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nsai:1,
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preamble_length:2,
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loopback:2);
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volatile u_int8_t __FXP_BITFIELD2(linear_priority:3,/* 7 */
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/*11*/ volatile u_int8_t __FXP_BITFIELD2(linear_priority:3,/* 7 */
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:5);
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volatile u_int8_t __FXP_BITFIELD3(linear_pri_mode:1,/* 7 */
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/*12*/ volatile u_int8_t __FXP_BITFIELD3(linear_pri_mode:1,/* 7 */
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:3,
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interfrm_spacing:4);
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volatile u_int8_t :8;
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volatile u_int8_t :8;
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volatile u_int8_t __FXP_BITFIELD8(promiscuous:1,
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/*13*/ volatile u_int8_t :8;
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/*14*/ volatile u_int8_t :8;
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/*15*/ volatile u_int8_t __FXP_BITFIELD8(promiscuous:1,
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bcast_disable:1,
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wait_after_win:1, /* 8,9 */
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:1,
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@ -246,15 +249,15 @@ struct fxp_cb_config {
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crc16_en:1, /* 9 */
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:1,
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crscdt:1);
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volatile u_int8_t fc_delay_lsb:8; /* 8,9 */
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volatile u_int8_t fc_delay_msb:8; /* 8,9 */
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volatile u_int8_t __FXP_BITFIELD6(stripping:1,
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/*16*/ volatile u_int8_t fc_delay_lsb:8; /* 8,9 */
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/*17*/ volatile u_int8_t fc_delay_msb:8; /* 8,9 */
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/*18*/ volatile u_int8_t __FXP_BITFIELD6(stripping:1,
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padding:1,
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rcv_crc_xfer:1,
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long_rx_en:1, /* 8,9 */
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pri_fc_thresh:3, /* 8,9 */
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:1);
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volatile u_int8_t __FXP_BITFIELD8(ia_wake_en:1, /* 8 */
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/*19*/ volatile u_int8_t __FXP_BITFIELD8(ia_wake_en:1, /* 8 */
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magic_pkt_dis:1, /* 8,9,!9ER */
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tx_fc_dis:1, /* 8,9 */
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rx_fc_restop:1, /* 8,9 */
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@ -262,13 +265,22 @@ struct fxp_cb_config {
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fc_filter:1, /* 8,9 */
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force_fdx:1,
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fdx_pin_en:1);
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volatile u_int8_t __FXP_BITFIELD4(:5,
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/*20*/ volatile u_int8_t __FXP_BITFIELD4(:5,
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pri_fc_loc:1 /* 8,9 */,
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multi_ia:1,
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:1);
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volatile u_int8_t __FXP_BITFIELD3(:3, mc_all:1, :4);
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/*21*/ volatile u_int8_t __FXP_BITFIELD3(:3, mc_all:1, :4);
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/* Bytes 22 - 31 -- i82550 only */
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/*22*/ volatile u_int8_t __FXP_BITFIELD3(ext_rx_mode:1,
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vlan_drop_en:1,
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:6);
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volatile u_int8_t reserved[9];
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};
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#define FXP_CONFIG_LEN 22 /* i8255x */
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#define FXP_EXT_CONFIG_LEN 32 /* i82550 */
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/*
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* Multicast setup command.
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*/
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@ -340,14 +352,27 @@ struct fxp_tbd {
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* we must make them an array of bytes!
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*/
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struct fxp_rfa {
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/* Fields common to all i8255x chips. */
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volatile u_int16_t rfa_status;
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volatile u_int16_t rfa_control;
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volatile u_int8_t link_addr[4];
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volatile u_int8_t rbd_addr[4];
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volatile u_int16_t actual_size;
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volatile u_int16_t size;
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/* Fields available only on the i82550 in extended RFD mode. */
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volatile u_int16_t vlan_id;
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volatile u_int8_t rx_parse_stat;
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volatile u_int8_t reserved;
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volatile u_int16_t security_stat;
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volatile u_int8_t cksum_stat;
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volatile u_int8_t zerocopy_stat;
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volatile u_int8_t unused[8];
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};
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#define RFA_SIZE 16
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#define RFA_EXT_SIZE 32
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#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */
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#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */
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#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */
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@ -1,4 +1,4 @@
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/* $NetBSD: i82557var.h,v 1.23 2001/05/22 15:29:30 thorpej Exp $ */
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/* $NetBSD: i82557var.h,v 1.24 2001/06/02 01:04:01 thorpej Exp $ */
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/*-
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* Copyright (c) 1997, 1998, 1999, 2001 The NetBSD Foundation, Inc.
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@ -177,6 +177,7 @@ struct fxp_softc {
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*/
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struct fxp_txsoft sc_txsoft[FXP_NTXCB];
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int sc_rfa_size; /* size of the RFA structure */
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struct ifqueue sc_rxq; /* receive buffer queue */
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bus_dmamap_t sc_rxmaps[FXP_NRFABUFS]; /* free receive buffer DMA maps */
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int sc_rxfree; /* free map index */
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@ -251,18 +252,18 @@ struct fxp_softc {
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \
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FXP_CDSTATSOFF, sizeof(struct fxp_stats), (ops))
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#define FXP_RXBUFSIZE(m) ((m)->m_ext.ext_size - \
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(sizeof(struct fxp_rfa) + \
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#define FXP_RXBUFSIZE(sc, m) ((m)->m_ext.ext_size - \
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(sc->sc_rfa_size + \
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RFA_ALIGNMENT_FUDGE))
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#define FXP_RFASYNC(sc, m, ops) \
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bus_dmamap_sync((sc)->sc_dmat, M_GETCTX((m), bus_dmamap_t), \
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RFA_ALIGNMENT_FUDGE, sizeof(struct fxp_rfa), (ops))
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RFA_ALIGNMENT_FUDGE, (sc)->sc_rfa_size, (ops))
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#define FXP_RXBUFSYNC(sc, m, ops) \
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bus_dmamap_sync((sc)->sc_dmat, M_GETCTX((m), bus_dmamap_t), \
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RFA_ALIGNMENT_FUDGE + sizeof(struct fxp_rfa), \
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FXP_RXBUFSIZE((m)), (ops))
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RFA_ALIGNMENT_FUDGE + (sc)->sc_rfa_size, \
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FXP_RXBUFSIZE((sc), (m)), (ops))
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#define FXP_MTORFA(m) (struct fxp_rfa *)((m)->m_ext.ext_buf + \
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RFA_ALIGNMENT_FUDGE)
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@ -274,11 +275,11 @@ do { \
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struct fxp_rfa *__rfa, *__p_rfa; \
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u_int32_t __v; \
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\
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(m)->m_data = (m)->m_ext.ext_buf + sizeof(struct fxp_rfa) + \
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(m)->m_data = (m)->m_ext.ext_buf + (sc)->sc_rfa_size + \
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RFA_ALIGNMENT_FUDGE; \
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\
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__rfa = FXP_MTORFA((m)); \
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__rfa->size = htole16(FXP_RXBUFSIZE((m))); \
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__rfa->size = htole16(FXP_RXBUFSIZE((sc), (m))); \
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/* BIG_ENDIAN: no need to swap to store 0 */ \
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__rfa->rfa_status = 0; \
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__rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); \
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