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GPI2 in the CIR register indicates our clock speed: 1 = 25MHz, 0 = 40MHz.

This commit is contained in:
thorpej 1998-05-26 22:48:01 +00:00
parent 4631dca956
commit 2d384ae1a1
1 changed files with 2 additions and 2 deletions
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4
sys/arch/alpha/tc/tcdsreg.h
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@ -1,4 +1,4 @@
/* $NetBSD: tcdsreg.h,v 1.4 1998/05/25 01:14:38 thorpej Exp $ */
/* $NetBSD: tcdsreg.h,v 1.5 1998/05/26 22:48:01 thorpej Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
@ -50,7 +50,7 @@
#define TCDS_CIR_STD 0x00000008 /* Serial transmit disable */
#define TCDS_CIR_GPI_0 0x00000010 /* Not used */
#define TCDS_CIR_GPI_1 0x00000020 /* Not used */
#define TCDS_CIR_GPI_2 0x00000040 /* Not used */
#define TCDS_CIR_GPI_2 0x00000040 /* 1 = 25MHz, 0 = 40MHz */
#define TCDS_CIR_GPI_3 0x00000080 /* Not used */
#define TCDS_CIR_SCSI0_DMAENA 0x00000100 /* SCSI 0 DMA enable */
#define TCDS_CIR_SCSI1_DMAENA 0x00000200 /* SCSI 1 DMA enable */