For those CPUs which don't have a cache-type register, keep the details
of the cache in a static table. Note that the table isn't complete -- contributions of cache details for CPUs whose data sheets I haven't got are welcome.
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bjh21
parent
1351389550
commit
2d05b7a7b6
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.c,v 1.31 2002/03/16 03:38:28 reinoud Exp $ */
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/* $NetBSD: cpufunc.c,v 1.32 2002/03/16 18:02:19 bjh21 Exp $ */
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/*
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* arm7tdmi support code Copyright (c) 2001 John Fremlin
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@ -553,11 +553,11 @@ u_int cputype;
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u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */
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#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
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defined(CPU_SA110) || defined(CPU_XSCALE)
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static void get_cachetype __P((void));
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defined(CPU_XSCALE)
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static void get_cachetype_cp15 __P((void));
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static void
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get_cachetype()
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get_cachetype_cp15()
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{
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u_int ctype, isize, dsize;
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u_int multiplier;
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@ -619,7 +619,67 @@ get_cachetype()
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out:
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arm_dcache_align_mask = arm_dcache_align - 1;
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}
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#endif /* ARM7TDMI || ARM8 || ARM9 || SA110 || XSCALE */
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#endif /* ARM7TDMI || ARM8 || ARM9 || XSCALE */
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#if defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3) || \
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defined(CPU_ARM7) || defined(CPU_SA110)
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/* Cache information for CPUs without cache type registers. */
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struct cachetab {
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u_int32_t ct_cpuid;
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int ct_pcache_type;
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int ct_pcache_unified;
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int ct_pdcache_size;
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int ct_pdcache_line_size;
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int ct_pdcache_ways;
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int ct_picache_size;
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int ct_picache_line_size;
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int ct_picache_ways;
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};
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struct cachetab cachetab[] = {
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/* cpuid, cache type, u, dsiz, ls, wy, isiz, ls, wy */
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{ CPU_ID_ARM2, 0, 1, 0, 0, 0, 0, 0, 0 },
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{ CPU_ID_ARM250, 0, 1, 0, 0, 0, 0, 0, 0 },
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{ CPU_ID_ARM3, CPU_CT_CTYPE_WT, 1, 4096, 16, 64, 0, 0, 0 },
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{ CPU_ID_ARM710, CPU_CT_CTYPE_WT, 1, 8192, 32, 4, 0, 0, 0 },
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{ CPU_ID_ARM7500, CPU_CT_CTYPE_WT, 1, 4096, 16, 4, 0, 0, 0 },
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{ CPU_ID_ARM710A, CPU_CT_CTYPE_WT, 1, 8192, 16, 4, 0, 0, 0 },
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{ CPU_ID_ARM7500FE, CPU_CT_CTYPE_WT, 1, 4096, 16, 4, 0, 0, 0 },
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/* XXX is this type right for SA-1? */
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{ CPU_ID_SA110, CPU_CT_CTYPE_WB1, 0, 16384, 32, 32, 16384, 32, 32 },
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{ CPU_ID_SA1100, CPU_CT_CTYPE_WB1, 0, 8192, 32, 32, 16384, 32, 32 },
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{ CPU_ID_SA1110, CPU_CT_CTYPE_WB1, 0, 8192, 32, 32, 16384, 32, 32 },
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{ 0, 0, 0, 0, 0, 0, 0, 0}
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};
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static void get_cachetype_table __P((void));
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static void
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get_cachetype_table()
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{
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int i;
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u_int32_t cpuid = cpufunc_id();
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for (i = 0; cachetab[i].ct_cpuid != 0; i++) {
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if (cachetab[i].ct_cpuid == (cpuid & CPU_ID_CPU_MASK)) {
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arm_pcache_type = cachetab[i].ct_pcache_type;
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arm_pcache_unified = cachetab[i].ct_pcache_unified;
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arm_pdcache_size = cachetab[i].ct_pdcache_size;
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arm_pdcache_line_size =
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cachetab[i].ct_pdcache_line_size;
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arm_pdcache_ways = cachetab[i].ct_pdcache_ways;
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arm_picache_size = cachetab[i].ct_picache_size;
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arm_picache_line_size =
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cachetab[i].ct_picache_line_size;
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arm_picache_ways = cachetab[i].ct_picache_ways;
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}
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}
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arm_dcache_align = arm_pdcache_line_size;
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arm_dcache_align_mask = arm_dcache_align - 1;
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}
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#endif /* ARM2 || ARM250 || ARM3 || ARM7 || SA110 */
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/*
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* Cannot panic here as we may not have a console yet ...
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@ -637,7 +697,7 @@ set_cpufuncs()
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(cputype & 0x00000f00) == 0x00000300) {
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cpufuncs = arm3_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 0;
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/* XXX Cache info? */
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get_cachetype_table();
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arm_dcache_align_mask = -1;
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return 0;
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}
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@ -658,7 +718,7 @@ set_cpufuncs()
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(cputype & CPU_ID_7ARCH_MASK) == CPU_ID_7ARCH_V3) {
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cpufuncs = arm7_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 0;
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/* XXX Cache info? */
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get_cachetype_table();
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arm_dcache_align_mask = -1;
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return 0;
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}
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@ -669,7 +729,7 @@ set_cpufuncs()
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(cputype & CPU_ID_7ARCH_MASK) == CPU_ID_7ARCH_V4T) {
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cpufuncs = arm7tdmi_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 0;
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get_cachetype();
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get_cachetype_cp15();
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return 0;
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}
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#endif
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@ -678,7 +738,7 @@ set_cpufuncs()
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(cputype & 0x0000f000) == 0x00008000) {
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cpufuncs = arm8_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 0; /* XXX correct? */
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get_cachetype();
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get_cachetype_cp15();
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return 0;
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}
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#endif /* CPU_ARM8 */
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@ -687,7 +747,7 @@ set_cpufuncs()
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pte_cache_mode = PT_C; /* Select write-through cacheing. */
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cpufuncs = arm9_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
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get_cachetype();
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get_cachetype_cp15();
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return 0;
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}
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#endif /* CPU_ARM9 */
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@ -696,7 +756,7 @@ set_cpufuncs()
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cputype == CPU_ID_SA1110) {
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cpufuncs = sa110_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
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get_cachetype();
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get_cachetype_table();
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/*
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* Enable the right variant of sleeping.
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*/
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@ -756,7 +816,7 @@ set_cpufuncs()
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cpufuncs.cf_dcache_inv_range = xscale_cache_purgeD_rng;
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cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
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get_cachetype();
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get_cachetype_cp15();
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return 0;
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}
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#endif /* CPU_XSCALE */
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