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Support single-stepping in DDB for sh3 too, it has different format of

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UBC registers.
This commit is contained in:
uwe 2008-06-06 04:16:22 +00:00
parent db245f3eb5
commit 2cef892cf9
2 changed files with 48 additions and 18 deletions
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36
sys/arch/sh3/sh3/db_interface.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: db_interface.c,v 1.52 2008/06/01 01:43:20 uwe Exp $ */
/* $NetBSD: db_interface.c,v 1.53 2008/06/06 04:16:22 uwe Exp $ */
/*-
* Copyright (C) 2002 UCHIYAMA Yasushi. All rights reserved.
@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.52 2008/06/01 01:43:20 uwe Exp $");
__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.53 2008/06/06 04:16:22 uwe Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@ -227,12 +227,34 @@ db_set_single_step(db_regs_t *regs)
{
_reg_write_2(SH_(BBRA), 0); /* disable break */
_reg_write_4(SH_(BARA), 0); /* break address */
_reg_write_1(SH_(BASRA), 0); /* break ASID */
_reg_write_1(SH_(BAMRA), 0x07); /* break always */
_reg_write_2(SH_(BRCR), 0x400); /* break after each execution */
regs->tf_ubc = 0x0014; /* will be written to BBRA */
#ifdef SH3
if (CPU_IS_SH3) {
/* A: ignore address */
_reg_write_4(SH_(BAMRA), 0xffffffff);
/* A: break after execution, ignore ASID */
_reg_write_4(SH_(BRCR), (UBC_CTL_A_AFTER_INSN
| SH3_UBC_CTL_A_MASK_ASID));
/* will be written to BBRA before RTE */
regs->tf_ubc = UBC_CYCLE_INSN | UBC_CYCLE_READ
| SH3_UBC_CYCLE_CPU;
}
#endif /* SH3 */
#ifdef SH4
if (CPU_IS_SH4) {
/* A: ignore address, ignore ASID */
_reg_write_1(SH_(BAMRA), SH4_UBC_MASK_ALL | SH4_UBC_MASK_ASID);
/* A: break after execution */
_reg_write_2(SH_(BRCR), UBC_CTL_A_AFTER_INSN);
/* will be written to BBRA before RTE */
regs->tf_ubc = UBC_CYCLE_INSN | UBC_CYCLE_READ;
}
#endif /* SH4 */
}
void

30
sys/arch/sh3/sh3/exception_vector.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: exception_vector.S,v 1.38 2008/04/28 20:23:35 martin Exp $ */
/* $NetBSD: exception_vector.S,v 1.39 2008/06/06 04:16:22 uwe Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@ -46,7 +46,7 @@
#define _ALIGN_TEXT .align 5
#include <sh3/asm.h>
__KERNEL_RCSID(0, "$NetBSD: exception_vector.S,v 1.38 2008/04/28 20:23:35 martin Exp $")
__KERNEL_RCSID(0, "$NetBSD: exception_vector.S,v 1.39 2008/06/06 04:16:22 uwe Exp $")
/*
@ -92,16 +92,15 @@ NENTRY(sh_vector_generic)
mov.l .Lg_tlb_exception, r0
jsr @r0
mov r14, r5 /* 2nd arg */
bra 2f
bra .Lg_return_from_exception
nop
/* general_exception(curlwp, tf, TEA); */
1: mov r4, r8
#ifdef DDB
mov #0, r2
MOV (BBRA, r1)
mov #0, r2
mov.w r2, @r1 /* disable UBC */
mov.l r2, @(TF_UBC, r14) /* clear tf->tf_ubc */
#endif /* DDB */
__EXCEPTION_UNBLOCK(r0, r1)
mov.l .Lg_general_exception, r0
@ -113,13 +112,22 @@ NENTRY(sh_vector_generic)
mov.l .Lg_ast, r0
jsr @r0
mov r14, r5
#ifdef DDB /* BBRA = tf->tf_ubc */
__EXCEPTION_BLOCK(r0, r1)
mov.l @(TF_UBC, r14), r0
MOV (BBRA, r1)
mov.w r0, @r1
#ifdef DDB
mov.l @(TF_UBC, r14), r2
tst r2, r2 ! ddb single-step == 0?
bt .Lg_return_from_exception
!! We are returning from DDB to do single step. Channel A in
!! UBC is already rigged, we just need to enable it.
mov #0, r0
MOV (BBRA, r3)
mov.l r0, @(TF_UBC, r14)
__EXCEPTION_BLOCK(r0, r1) ! because we ignore insn address
mov.w r2, @r3 ! now safe to set BBRA = tf->tf_ubc
#endif /* DDB */
2: __EXCEPTION_RETURN
.Lg_return_from_exception:
__EXCEPTION_RETURN
.align 5
.Lg_curlwp: .long _C_LABEL(curlwp)