- option MIPS_DDB_WATCH is dedprecated, removed; now using
(MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 for conditional compile of db_mach_watch stuff - MIPS CPU (COP0) watchpoint support moved from db_interface.c to cpu_subr.c, cpu.h; ddb_mach_watch &etc now use those cpu functions. - ddb_cpu now volatile - 'struct db_mach_watch' definition &etc moved to mips/include/db_machdep.h - db_mach_watch_tab is replaced by curcpu()->ci_watch_tab to allow per-cpu watchpoint control - improve MP function in kdb_trap() - fix conditions for printing cp0 regs
This commit is contained in:
cliff
parent
061e9aafc0
commit
2cbfee21ba
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@ -1,4 +1,4 @@
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/* $NetBSD: db_interface.c,v 1.70 2011/04/06 05:53:27 matt Exp $ */
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/* $NetBSD: db_interface.c,v 1.71 2011/04/14 05:09:34 cliff Exp $ */
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/*
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* Mach Operating System
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@ -27,7 +27,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.70 2011/04/06 05:53:27 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.71 2011/04/14 05:09:34 cliff Exp $");
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#include "opt_multiprocessor.h"
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#include "opt_cputype.h" /* which mips CPUs do we support? */
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@ -67,34 +67,15 @@ __KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.70 2011/04/06 05:53:27 matt Exp $
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#endif
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#define NOCPU ~0
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u_int ddb_cpu = NOCPU;
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volatile u_int ddb_cpu = NOCPU;
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int db_active = 0;
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db_regs_t ddb_regs;
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#ifdef MIPS_DDB_WATCH
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struct db_mach_watch {
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register_t addr;
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register_t mask;
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uint32_t asid;
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uint32_t mode;
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};
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/* mode bits */
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#define DB_WATCH_WRITE __BIT(0)
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#define DB_WATCH_READ __BIT(1)
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#define DB_WATCH_EXEC __BIT(2)
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#define DB_WATCH_MASK __BIT(3)
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#define DB_WATCH_ASID __BIT(4)
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#define DB_WATCH_RWX (DB_WATCH_EXEC|DB_WATCH_READ|DB_WATCH_WRITE)
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#define DBNWATCH 1
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static volatile struct db_mach_watch db_mach_watch_tab[DBNWATCH];
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static void db_mach_watch_set(int, register_t, register_t, uint32_t, uint32_t,
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bool);
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#if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
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static void db_watch_cmd(db_expr_t, bool, db_expr_t, const char *);
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static void db_unwatch_cmd(db_expr_t, bool, db_expr_t, const char *);
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#endif /* MIPS_DDB_WATCH */
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#endif /* (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 */
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#ifdef MULTIPROCESSOR
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static void db_mach_cpu(db_expr_t, bool, db_expr_t, const char *);
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@ -146,6 +127,8 @@ kdb_trap(int type, struct reg *regs)
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break;
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}
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s = splhigh();
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#ifdef MULTIPROCESSOR
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bool first_in_ddb = false;
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const u_int cpu_me = cpu_number();
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@ -155,26 +138,25 @@ kdb_trap(int type, struct reg *regs)
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cpu_pause_others();
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} else {
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if (old_ddb_cpu != cpu_me) {
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KASSERT(cpu_is_paused(cpu_me));
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cpu_pause(regs);
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splx(s);
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return 1;
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}
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}
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KASSERT(! cpu_is_paused(cpu_me));
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#endif
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/* Should switch to kdb`s own stack here. */
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ddb_regs = *regs;
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s = splhigh();
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db_active++;
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cnpollc(1);
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db_trap(type & ~T_USER, 0 /*code*/);
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cnpollc(0);
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db_active--;
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splx(s);
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*regs = ddb_regs;
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#ifdef MULTIPROCESSOR
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if (ddb_cpu == cpu_me) {
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ddb_cpu = NOCPU;
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if (atomic_cas_uint(&ddb_cpu, cpu_me, NOCPU) == cpu_me) {
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cpu_resume_others();
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} else {
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cpu_resume(ddb_cpu);
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@ -183,9 +165,8 @@ kdb_trap(int type, struct reg *regs)
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}
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#endif
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*regs = ddb_regs;
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return (1);
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splx(s);
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return 1;
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}
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void
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@ -411,10 +392,12 @@ db_cp0dump_cmd(db_expr_t addr, bool have_addr, db_expr_t count,
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SHOW32(MIPS_COP_0_COUNT, "count");
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}
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if ((cp0flags & MIPS_CP0FL_EIRR) != 0)
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SHOW64SEL(9, 6, "eirr");
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if ((cp0flags & MIPS_CP0FL_EIMR) != 0)
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SHOW64SEL(9, 7, "eimr");
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if ((cp0flags & MIPS_CP0FL_USE) != 0) {
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if ((cp0flags & MIPS_CP0FL_EIRR) != 0)
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SHOW64SEL(9, 6, "eirr");
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if ((cp0flags & MIPS_CP0FL_EIMR) != 0)
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SHOW64SEL(9, 7, "eimr");
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}
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if (CPUIS64BITS) {
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SHOW64(MIPS_COP_0_TLB_HI, "entryhi");
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@ -479,146 +462,98 @@ db_cp0dump_cmd(db_expr_t addr, bool have_addr, db_expr_t count,
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else
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SHOW32(MIPS_COP_0_LLADDR, "lladdr");
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}
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}
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SHOW32(MIPS_COP_0_WATCH_HI, "watchhi");
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if (CPUIS64BITS)
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SHOW64(MIPS_COP_0_WATCH_LO, "watchlo");
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else
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SHOW32(MIPS_COP_0_WATCH_LO, "watchlo");
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#if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
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for (int i=0; i < curcpu()->ci_cpuwatch_count; i++) {
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uint32_t r = mipsNN_cp0_watchlo_read(i);
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printf(" %s%d:%*s %#x\n", "watchlo", i, FLDWIDTH - 8, "", r);
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}
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for (int i=0; i < curcpu()->ci_cpuwatch_count; i++) {
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if (CPUIS64BITS) {
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SHOW64(MIPS_COP_0_TLB_XCONTEXT, "xcontext");
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}
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if (CPUISMIPSNN) {
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if (CPUIS64BITS) {
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SHOW64(MIPS_COP_0_PERFCNT, "perfcnt");
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} else {
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SHOW32(MIPS_COP_0_PERFCNT, "perfcnt");
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}
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}
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if (((cp0flags & MIPS_CP0FL_USE) == 0) ||
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((cp0flags & MIPS_CP0FL_ECC) != 0))
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SHOW32(MIPS_COP_0_ECC, "ecc");
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if (((cp0flags & MIPS_CP0FL_USE) == 0) ||
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((cp0flags & MIPS_CP0FL_CACHE_ERR) != 0))
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SHOW32(MIPS_COP_0_CACHE_ERR, "cacherr");
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SHOW32(MIPS_COP_0_TAG_LO, "cachelo");
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SHOW32(MIPS_COP_0_TAG_HI, "cachehi");
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if (CPUIS64BITS) {
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SHOW64(MIPS_COP_0_ERROR_PC, "errorpc");
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uint32_t r = mipsNN_cp0_watchhi_read(i);
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printf(" %s%d:%*s %#x\n",
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"watchhi", i, FLDWIDTH - 8, "", r);
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} else {
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SHOW32(MIPS_COP_0_ERROR_PC, "errorpc");
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uint64_t r = mipsNN_cp0_watchhi_read(i);
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printf(" %s%d:%*s %#" PRIx64 "\n",
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"watchhi", i, FLDWIDTH - 8, "", r);
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}
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}
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}
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#ifdef MIPS_DDB_WATCH
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void
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db_mach_watch_set_all(void)
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{
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volatile struct db_mach_watch *wp;
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int i;
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for (i=0; i < DBNWATCH; i++) {
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wp = &db_mach_watch_tab[i];
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db_mach_watch_set(i, wp->addr, wp->mask, wp->asid, wp->mode,
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true);
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}
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}
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/*
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* db_mach_watch_set - write the COP0 registers
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*/
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static void
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db_mach_watch_set(int wnum, register_t addr, register_t mask, uint32_t asid,
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uint32_t mode, bool quiet)
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{
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uint32_t watchhi;
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register_t watchlo;
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const char *strhi = (quiet) ? NULL : "watchhi";
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const char *strlo = (quiet) ? NULL : "watchlo";
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KASSERT(wnum == 0); /* TBD */
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watchlo = addr;
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if (mode & DB_WATCH_WRITE)
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watchlo |= __BIT(0);
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if (mode & DB_WATCH_READ)
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watchlo |= __BIT(1);
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if (mode & DB_WATCH_EXEC)
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watchlo |= __BIT(2);
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if (mode & DB_WATCH_ASID)
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watchhi = asid << 16; /* addr qualified by asid */
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else
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watchhi = __BIT(30); /* addr not qualified by asid (Global)*/
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if (mode & DB_WATCH_MASK)
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watchhi |= mask; /* set "dont care" addr match bits */
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SET32(MIPS_COP_0_WATCH_HI, strhi, watchhi);
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#endif
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if (CPUIS64BITS) {
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MIPS64_SET64(MIPS_COP_0_WATCH_LO, 0, strlo, watchlo);
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SHOW64(MIPS_COP_0_TLB_XCONTEXT, "xcontext");
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}
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if (CPUISMIPSNN) {
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if (CPUIS64BITS) {
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SHOW64(MIPS_COP_0_PERFCNT, "perfcnt");
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} else {
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SHOW32(MIPS_COP_0_PERFCNT, "perfcnt");
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}
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}
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if (((cp0flags & MIPS_CP0FL_USE) == 0) ||
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((cp0flags & MIPS_CP0FL_ECC) != 0))
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SHOW32(MIPS_COP_0_ECC, "ecc");
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if (((cp0flags & MIPS_CP0FL_USE) == 0) ||
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((cp0flags & MIPS_CP0FL_CACHE_ERR) != 0))
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SHOW32(MIPS_COP_0_CACHE_ERR, "cacherr");
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SHOW32(MIPS_COP_0_TAG_LO, "cachelo");
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SHOW32(MIPS_COP_0_TAG_HI, "cachehi");
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if (CPUIS64BITS) {
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SHOW64(MIPS_COP_0_ERROR_PC, "errorpc");
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} else {
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SET32(MIPS_COP_0_WATCH_LO, strlo, (uint32_t)watchlo);
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SHOW32(MIPS_COP_0_ERROR_PC, "errorpc");
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}
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}
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#if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
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static void
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db_watch_cmd(db_expr_t address, bool have_addr, db_expr_t count,
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const char *modif)
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{
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volatile struct db_mach_watch *wp;
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struct cpu_info * const ci = curcpu();
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cpu_watchpoint_t *cwp;
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register_t mask=0;
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uint32_t asid;
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uint32_t mode;
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db_expr_t value;
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int wnum;
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char str[6];
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if (!have_addr) {
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db_printf("%-3s %-5s %-16s %4s %4s\n",
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"#", "MODE", "ADDR", "MASK", "ASID");
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for (int i=0; i < DBNWATCH; i++) {
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wp = &db_mach_watch_tab[i];
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mode = wp->mode;
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if ((mode & DB_WATCH_RWX) == 0)
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for (int i=0; i < ci->ci_cpuwatch_count; i++) {
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cwp = &ci->ci_cpuwatch_tab[i];
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mode = cwp->cw_mode;
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if ((mode & CPUWATCH_RWX) == 0)
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continue; /* empty/disabled/invalid */
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str[0] = (mode & DB_WATCH_READ) ? 'r' : '-';
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str[1] = (mode & DB_WATCH_WRITE) ? 'w' : '-';
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str[2] = (mode & DB_WATCH_EXEC) ? 'x' : '-';
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str[3] = (mode & DB_WATCH_MASK) ? 'm' : '-';
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str[4] = (mode & DB_WATCH_ASID) ? 'a' : 'g';
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str[0] = (mode & CPUWATCH_READ) ? 'r' : '-';
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str[1] = (mode & CPUWATCH_WRITE) ? 'w' : '-';
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str[2] = (mode & CPUWATCH_EXEC) ? 'x' : '-';
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str[3] = (mode & CPUWATCH_MASK) ? 'm' : '-';
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str[4] = (mode & CPUWATCH_ASID) ? 'a' : 'g';
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str[5] = '\0';
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db_printf("%2d: %s %16" PRIxREGISTER
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" %4" PRIxREGISTER " %4x\n",
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i, str, wp->addr, wp->mask, wp->asid);
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i, str, cwp->cw_addr, cwp->cw_mask, cwp->cw_asid);
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}
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db_flush_lex();
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return;
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}
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/*
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* find an empty slot
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* no lock for the table since only 1 CPU active in ddb at a time
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* (other CPUs are paused)
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*/
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for (int i=0; i < DBNWATCH; i++) {
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wp = &db_mach_watch_tab[i]; /* empty/disabled/invalid */
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if ((wp->mode & DB_WATCH_RWX) == 0) {
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wnum = i;
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goto found;
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}
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cwp = cpuwatch_alloc();
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if (cwp == NULL) {
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db_printf("no watchpoint available\n");
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db_flush_lex();
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return;
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}
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db_printf("no watchpoint available\n");
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db_flush_lex();
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return;
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found:
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/*
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* parse modif to define mode
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*/
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@ -627,19 +562,19 @@ db_watch_cmd(db_expr_t address, bool have_addr, db_expr_t count,
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for (int i=0; modif[i] != '\0'; i++) {
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switch(modif[i]) {
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case 'w':
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mode |= DB_WATCH_WRITE;
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mode |= CPUWATCH_WRITE;
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break;
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case 'm':
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mode |= DB_WATCH_MASK;
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mode |= CPUWATCH_MASK;
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break;
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case 'r':
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mode |= DB_WATCH_READ;
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mode |= CPUWATCH_READ;
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break;
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case 'x':
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mode |= DB_WATCH_EXEC;
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mode |= CPUWATCH_EXEC;
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break;
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case 'a':
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mode |= DB_WATCH_ASID;
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mode |= CPUWATCH_ASID;
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break;
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}
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}
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@ -652,7 +587,7 @@ db_watch_cmd(db_expr_t address, bool have_addr, db_expr_t count,
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/*
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* if mask mode is requested get the mask,
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*/
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if (mode & DB_WATCH_MASK) {
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if (mode & CPUWATCH_MASK) {
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if (! db_expression(&value)) {
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db_printf("mask missing\n");
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db_flush_lex();
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@ -665,7 +600,7 @@ db_watch_cmd(db_expr_t address, bool have_addr, db_expr_t count,
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* if asid mode is requested, get the asid;
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* otherwise use global mode (and set asid=0)
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*/
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if (mode & DB_WATCH_ASID) {
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if (mode & CPUWATCH_ASID) {
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if (! db_expression(&value)) {
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db_printf("asid missing\n");
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db_flush_lex();
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@ -676,7 +611,7 @@ db_watch_cmd(db_expr_t address, bool have_addr, db_expr_t count,
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asid = 0;
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}
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if (mode & (DB_WATCH_MASK|DB_WATCH_ASID))
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if (mode & (CPUWATCH_MASK|CPUWATCH_ASID))
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db_skip_to_eol();
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else
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db_flush_lex();
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@ -685,31 +620,32 @@ db_watch_cmd(db_expr_t address, bool have_addr, db_expr_t count,
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* store to the (volatile) table entry
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* other CPUs can see this and load when resuming from pause
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*/
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wp->addr = (register_t)address;
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wp->mask = (register_t)mask;
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wp->asid = asid;
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wp->mode = mode;
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cwp->cw_addr = (register_t)address;
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cwp->cw_mask = (register_t)mask;
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cwp->cw_asid = asid;
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cwp->cw_mode = mode;
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db_mach_watch_set(wnum, (register_t)address, mask, asid, mode, false);
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/*
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* program the CPU watchpoint regs
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*/
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cpuwatch_set(cwp);
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}
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static void
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db_unwatch_cmd(db_expr_t address, bool have_addr, db_expr_t count,
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const char *modif)
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{
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volatile struct db_mach_watch *wp;
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struct cpu_info * const ci = curcpu();
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cpu_watchpoint_t *cwp;
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int i, n;
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bool unwatch_all = !have_addr;
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n = 0;
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for (i=0; i < DBNWATCH; i++) {
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wp = &db_mach_watch_tab[i];
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if (unwatch_all || (wp->addr == (register_t)address)) {
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for (i=0; i < ci->ci_cpuwatch_count; i++) {
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cwp = &ci->ci_cpuwatch_tab[i];
|
||||
if (unwatch_all || (cwp->cw_addr == (register_t)address)) {
|
||||
cpuwatch_free(cwp);
|
||||
n++;
|
||||
wp->mode = 0;
|
||||
wp->asid = 0;
|
||||
wp->addr = 0;
|
||||
db_mach_watch_set(i, 0, 0, 0, 0, false);
|
||||
}
|
||||
}
|
||||
if (n == 0)
|
||||
|
|
@ -717,7 +653,7 @@ db_unwatch_cmd(db_expr_t address, bool have_addr, db_expr_t count,
|
|||
(register_t)address);
|
||||
|
||||
}
|
||||
#endif /* MIPS_DDB_WATCH */
|
||||
#endif /* (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 */
|
||||
|
||||
#ifdef MIPS64_XLS
|
||||
void
|
||||
|
|
@ -787,14 +723,14 @@ const struct db_command db_machine_command_table[] = {
|
|||
{ DDB_ADD_CMD("cp0", db_cp0dump_cmd, 0,
|
||||
"Dump CP0 registers.",
|
||||
NULL, NULL) },
|
||||
#ifdef MIPS_DDB_WATCH
|
||||
#if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
|
||||
{ DDB_ADD_CMD("watch", db_watch_cmd, CS_MORE,
|
||||
"set cp0 watchpoint",
|
||||
"address <mask> <asid> </rwxma>", NULL) },
|
||||
{ DDB_ADD_CMD("unwatch",db_unwatch_cmd, 0,
|
||||
"delete cp0 watchpoint",
|
||||
"address", NULL) },
|
||||
#endif /* MIPS_DDB_WATCH */
|
||||
#endif /* (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 */
|
||||
{ DDB_ADD_CMD("kvtop", db_kvtophys_cmd, 0,
|
||||
"Print the physical address for a given kernel virtual address",
|
||||
"address",
|
||||
|
|
@ -1029,8 +965,7 @@ db_mach_cpu(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
|
|||
db_printf("CPU %ld not paused\n", (long)addr);
|
||||
return;
|
||||
}
|
||||
/* no locking needed - all other cpus are paused */
|
||||
ddb_cpu = cpu_index(ci);
|
||||
(void)atomic_cas_uint(&ddb_cpu, cpu_number(), cpu_index(ci));
|
||||
db_continue_cmd(0, false, 0, "");
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue