Patches from Ken Wellsch/Ken Lalonde to support some Dilog MSCP cards
(DQ256 SMD card, SQ706A and SU726A SCSI card).
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@ -1,4 +1,4 @@
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/* $NetBSD: uda.c,v 1.7 1995/07/05 08:24:48 ragge Exp $ */
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/* $NetBSD: uda.c,v 1.8 1995/08/31 22:24:39 ragge Exp $ */
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/*
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* Copyright (c) 1988 Regents of the University of California.
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@ -109,6 +109,27 @@
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extern int cold;
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/*
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* This macro is for delay during init. Some MSCP clone card (Dilog)
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* can't handle fast read from its registers, and therefore need
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* a delay between them.
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*/
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#define DELAYTEN 1000
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#define Wait_step( mask, result, status ) { \
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status = 1; \
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if ((udaddr->udasa & mask) != result) { \
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int count = 0; \
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while ((udaddr->udasa & mask) != result) { \
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DELAY(100); \
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count += 1; \
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if (count > DELAYTEN) \
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break; \
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} \
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if (count > DELAYTEN) \
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status = 0; \
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} \
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}
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/*
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* UDA communications area and MSCP packet pools, per controller.
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*/
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@ -278,7 +299,7 @@ udaprobe(reg, ctlr, um)
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volatile struct udadevice *udaddr;
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struct mscp_info *mi;
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extern int cpu_type;
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int timeout, tries;
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int timeout, tries, count;
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#ifdef notyet
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int s;
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#endif
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@ -350,15 +371,36 @@ udaprobe(reg, ctlr, um)
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tries = 0;
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again:
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udaddr->udaip = 0; /* start initialisation */
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timeout = todr() + 1000; /* timeout in 10 seconds */
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while ((udaddr->udasa & UDA_STEP1) == 0)
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if (todr() > timeout)
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goto bad;
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count = 0;
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while ( count < DELAYTEN ) {
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if ( (udaddr->udasa & UDA_STEP1) != 0 )
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break;
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DELAY(10000);
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count += 1;
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}
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/* nothing there */
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if ( count == DELAYTEN )
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return(0);
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udaddr->udasa = UDA_ERR | (NCMDL2 << 11) | (NRSPL2 << 8) | UDA_IE |
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(sc->sc_ivec >> 2);
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while ((udaddr->udasa & UDA_STEP2) == 0)
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if (todr() > timeout)
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goto bad;
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count = 0;
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while (count < DELAYTEN) {
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if ((udaddr->udasa & UDA_STEP2 ) != 0)
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break;
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DELAY(10000);
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count += 1;
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}
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if (count == DELAYTEN) {
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printf("udaprobe: uda%d: init step2 no change.\n",
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um->um_ctlr);
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goto bad;
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}
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/* should have interrupted by now */
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#ifdef notyet
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sc->sc_ipl = br = qbgetpri();
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@ -600,7 +642,7 @@ udainit(ctlr)
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register struct uda_softc *sc;
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register struct udadevice *udaddr;
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struct uba_ctlr *um;
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int timo, ubinfo;
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int timo, ubinfo, count;
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/* printf("udainit\n"); */
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sc = &uda_softc[ctlr];
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um = udaminfo[ctlr];
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@ -635,13 +677,18 @@ udainit(ctlr)
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sc->sc_state = ST_IDLE; /* in case init fails */
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udaddr = (struct udadevice *)um->um_addr;
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udaddr->udaip = 0;
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timo = todr() + 1000;
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while ((udaddr->udasa & STEP0MASK) == 0) {
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if (todr() > timo) {
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printf("uda%d: timeout during init\n", ctlr);
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return (-1);
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}
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count = 0;
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while (count < DELAYTEN) {
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if ((udaddr->udasa & UDA_STEP1) != 0)
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break;
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DELAY(10000);
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count += 1;
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}
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if (count == DELAYTEN) {
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printf("uda%d: timeout during init\n", ctlr);
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return (-1);
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}
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if ((udaddr->udasa & STEP0MASK) != UDA_STEP1) {
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printf("uda%d: init failed, sa=%b\n", ctlr,
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udaddr->udasa, udasr_bits);
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@ -1345,7 +1392,7 @@ udaintr(vektor,level,uba,ctlr)
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volatile struct udadevice *udaddr = (struct udadevice *)um->um_addr;
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struct uda *ud;
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struct mscp *mp;
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volatile int i;
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volatile int i, wait_status;
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extern int cpu_type;
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#ifdef QBA
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@ -1385,8 +1432,9 @@ udaintr(vektor,level,uba,ctlr)
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/*
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* Begin step two initialisation.
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*/
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if ((udaddr->udasa & STEP1MASK) != STEP1GOOD) {
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i = 1;
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i = 0;
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Wait_step(STEP1MASK, STEP1GOOD, wait_status);
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if (!wait_status) {
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initfailed:
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printf("uda%d: init step %d failed, sa=%b\n",
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ctlr, i, udaddr->udasa, udasr_bits);
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@ -1408,10 +1456,11 @@ initfailed:
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/*
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* Begin step 3 initialisation.
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*/
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if ((udaddr->udasa & STEP2MASK) != STEP2GOOD) {
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i = 2;
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i = 2;
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Wait_step(STEP2MASK, STEP2GOOD, wait_status);
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if (!wait_status)
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goto initfailed;
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}
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udaddr->udasa = ((int)&sc->sc_uda->uda_ca.ca_rspdsc[0]) >> 16;
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sc->sc_state = ST_STEP3;
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return;
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@ -1420,10 +1469,11 @@ initfailed:
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/*
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* Set controller characteristics (finish initialisation).
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*/
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if ((udaddr->udasa & STEP3MASK) != STEP3GOOD) {
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i = 3;
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i = 3;
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Wait_step(STEP3MASK, STEP3GOOD, wait_status);
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if (!wait_status)
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goto initfailed;
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}
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i = udaddr->udasa & 0xff;
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if (i != sc->sc_micro) {
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sc->sc_micro = i;
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