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Clear the upper word explicitly before combining two 32-bit values to 64-bit

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on 32-bit kernels.
This commit is contained in:
nakayama 2010-07-10 10:10:36 +00:00
parent 180e77d6e9
commit 2c360db4bf
3 changed files with 19 additions and 10 deletions
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14
sys/arch/sparc64/include/ctlreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: ctlreg.h,v 1.52 2010/02/23 05:24:50 mrg Exp $ */
/* $NetBSD: ctlreg.h,v 1.53 2010/07/10 10:10:36 nakayama Exp $ */
/*
* Copyright (c) 1996-2002 Eduardo Horvath
@ -533,6 +533,7 @@ static __inline type ld(paddr_t loc, int asi) \
/* 32-bit kernel, MMU bypass, non-constant */
#define SPARC64_LD_PHYS_NONCONST(ld) \
__asm volatile( \
"clruw %2; " \
"rdpr %%pstate,%1; " \
"sllx %3,32,%0; " \
"wrpr %1,8,%%pstate; " \
@ -552,6 +553,7 @@ static __inline type ld(paddr_t loc, int asi) \
/* 32-bit kernel, MMU bypass, non-constant, 64-bit value */
#define SPARC64_LD_PHYS_NONCONST64(ld) \
__asm volatile( \
"clruw %2; " \
"rdpr %%pstate,%1; " \
"sllx %3,32,%0; " \
"wrpr %1,8,%%pstate; " \
@ -583,6 +585,7 @@ static __inline type ld(paddr_t loc, int asi) \
_hi = (uint64_t)(loc) >> 32; \
if (__builtin_constant_p(asi)) \
__asm volatile( \
"clruw %2; " \
"rdpr %%pstate,%1; " \
"sllx %3,32,%0; " \
"wrpr %1,8,%%pstate; " \
@ -613,6 +616,7 @@ static __inline type ld(paddr_t loc, int asi) \
_hi = (uint64_t)(loc) >> 32; \
if (__builtin_constant_p(asi)) \
__asm volatile( \
"clruw %2; " \
"rdpr %%pstate,%1; " \
"sllx %3,32,%0; " \
"wrpr %1,8,%%pstate; " \
@ -715,6 +719,7 @@ static __inline void st(paddr_t loc, int asi, type value) \
/* 32-bit kernel, MMU bypass, non-constant */
#define SPARC64_ST_PHYS_NONCONST(st) \
__asm volatile( \
"clruw %3; " \
"rdpr %%pstate,%1; " \
"sllx %4,32,%0; " \
"wrpr %1,8,%%pstate; " \
@ -734,6 +739,8 @@ static __inline void st(paddr_t loc, int asi, type value) \
/* 32-bit kernel, MMU bypass, non-constant, 64-bit value */
#define SPARC64_ST_PHYS_NONCONST64(st) \
__asm volatile( \
"clruw %3; " \
"clruw %5; " \
"sllx %4,32,%1; " \
"sllx %6,32,%0; " \
"rdpr %%pstate,%2; " \
@ -749,6 +756,7 @@ static __inline void st(paddr_t loc, int asi, type value) \
/* 32-bit kernel, non-constant, 64-bit value */
#define SPARC64_ST_NONCONST64(st) \
__asm volatile( \
"clruw %1; " \
"sllx %2,32,%0; " \
"or %0,%1,%0; " \
"wr %4,%%g0,%%asi; " \
@ -766,6 +774,7 @@ static __inline void st(paddr_t loc, int asi, type value) \
_hi = (uint64_t)(loc) >> 32; \
if (__builtin_constant_p(asi)) \
__asm volatile( \
"clruw %3; " \
"sllx %4,32,%0; " \
"rdpr %%pstate,%1; " \
"or %0,%3,%0; " \
@ -797,6 +806,8 @@ static __inline void st(paddr_t loc, int asi, type value) \
_hi = (uint64_t)(loc) >> 32; \
if (__builtin_constant_p(asi)) \
__asm volatile( \
"clruw %3; " \
"clruw %5; " \
"sllx %4,32,%1; " \
"sllx %6,32,%0; " \
"rdpr %%pstate,%2; " \
@ -814,6 +825,7 @@ static __inline void st(paddr_t loc, int asi, type value) \
} else { \
if (__builtin_constant_p(asi)) \
__asm volatile( \
"clruw %1; " \
"sllx %2,32,%0; " \
"or %0,%1,%0; " \
#st " %0,[%3]%4 " \

3
sys/arch/sparc64/include/locore.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.h,v 1.4 2010/05/23 18:49:14 martin Exp $ */
/* $NetBSD: locore.h,v 1.5 2010/07/10 10:10:36 nakayama Exp $ */
/*
* Copyright (c) 1996-2002 Eduardo Horvath
@ -129,6 +129,7 @@
* values to LP64.
*/
#define COMBINE(r1, r2, d) \
clruw r2; \
sllx r1, 32, d; \
or d, r2, d

12
sys/arch/sparc64/sparc64/locore.s
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.s,v 1.330 2010/05/23 18:49:14 martin Exp $ */
/* $NetBSD: locore.s,v 1.331 2010/07/10 10:10:36 nakayama Exp $ */
/*
* Copyright (c) 2006-2010 Matthew R. Green
@ -5483,13 +5483,9 @@ ENTRY(pseg_get_real)
*/
ENTRY(pseg_set_real)
#ifndef _LP64
sllx %o4, 32, %o4 ! Put args into 64-bit format
sllx %o2, 32, %o2 ! Shift to high 32-bits
clruw %o3 ! Zero extend
clruw %o5
clruw %o1
or %o2, %o3, %o2
or %o4, %o5, %o3
clruw %o1 ! Zero extend
COMBINE(%o2, %o3, %o2)
COMBINE(%o4, %o5, %o3)
#endif
!!
!! However we managed to get here we now have: