Clean up dbregs; remove useless comments, remove arguments from prototypes,
style, add KASSERT and move x86_dbregspl into dbregs.c. No real functional change.
This commit is contained in:
maxv
parent
1577172429
commit
2b85909210
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.307 2018/07/21 06:09:13 maxv Exp $ */
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/* $NetBSD: machdep.c,v 1.308 2018/07/22 15:02:51 maxv Exp $ */
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/*
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* Copyright (c) 1996, 1997, 1998, 2000, 2006, 2007, 2008, 2011
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@ -110,7 +110,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.307 2018/07/21 06:09:13 maxv Exp $");
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.308 2018/07/22 15:02:51 maxv Exp $");
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#include "opt_modular.h"
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#include "opt_user_ldt.h"
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@ -280,7 +280,7 @@ void (*delay_func)(unsigned int) = xen_delay;
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void (*initclock_func)(void) = xen_initclocks;
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#endif
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struct pool x86_dbregspl;
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extern struct pool x86_dbregspl;
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struct nmistore {
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uint64_t cr3;
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@ -1929,11 +1929,7 @@ init_x86_64(paddr_t first_avail)
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#endif
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pcb->pcb_dbregs = NULL;
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x86_dbregs_setup_initdbstate();
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pool_init(&x86_dbregspl, sizeof(struct dbreg), 16, 0, 0, "dbregs",
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NULL, IPL_NONE);
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x86_dbregs_init();
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}
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void
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.806 2018/04/05 08:43:07 maxv Exp $ */
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/* $NetBSD: machdep.c,v 1.807 2018/07/22 15:02:51 maxv Exp $ */
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/*
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* Copyright (c) 1996, 1997, 1998, 2000, 2004, 2006, 2008, 2009, 2017
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@ -67,7 +67,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.806 2018/04/05 08:43:07 maxv Exp $");
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.807 2018/07/22 15:02:51 maxv Exp $");
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#include "opt_beep.h"
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#include "opt_compat_freebsd.h"
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@ -213,7 +213,7 @@ int i386_use_fxsave;
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int i386_has_sse;
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int i386_has_sse2;
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struct pool x86_dbregspl;
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extern struct pool x86_dbregspl;
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vaddr_t idt_vaddr;
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paddr_t idt_paddr;
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@ -1443,11 +1443,7 @@ init386(paddr_t first_avail)
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}
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pcb->pcb_dbregs = NULL;
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x86_dbregs_setup_initdbstate();
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pool_init(&x86_dbregspl, sizeof(struct dbreg), 16, 0, 0, "dbregs",
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NULL, IPL_NONE);
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x86_dbregs_init();
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}
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#include <dev/ic/mc146818reg.h> /* for NVRAM POST */
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@ -1,6 +1,6 @@
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/* $NetBSD: dbregs.h,v 1.4 2017/02/23 03:34:22 kamil Exp $ */
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/* $NetBSD: dbregs.h,v 1.5 2018/07/22 15:02:51 maxv Exp $ */
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/*-
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/*
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* Copyright (c) 2016 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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@ -26,7 +26,6 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _X86_DBREGS_H_
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#define _X86_DBREGS_H_
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@ -50,11 +49,11 @@
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/*
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* CPU Debug Control Register (DR7)
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*
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* LOCAL_EXACT_BREAKPOINT and GLOBAL_EXACT_BREAKPOINT are no longer used since
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* the P6 processor family - portable code should set these bits
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* unconditionally in oder to get exact breakpoints
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* LOCAL_EXACT_BREAKPOINT and GLOBAL_EXACT_BREAKPOINT are no longer used
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* since the P6 processor family - portable code should set these bits
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* unconditionally in order to get exact breakpoints.
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*
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* Reserved bits: 10, 12, 14-15 and on x86_64 32-64
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* Reserved bits: 10, 12, 14-15 and on x86_64 32-64.
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*/
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#define X86_DR7_LOCAL_DR0_BREAKPOINT __BIT(0)
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#define X86_DR7_GLOBAL_DR0_BREAKPOINT __BIT(1)
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@ -79,9 +78,9 @@
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#define X86_DR7_DR3_LENGTH_MASK __BITS(30, 31)
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/*
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* X86_DR7_CONDITION_IO_READWRITE is currently unused
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* it requires DE (debug extension) flag in control register CR4 set
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* not all CPUs support it
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* X86_DR7_CONDITION_IO_READWRITE is currently unused. It requires DE
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* (debug extension) flag in control register CR4 set, and not all CPUs
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* support it.
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*/
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enum x86_dr7_condition {
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X86_DR7_CONDITION_EXECUTION = 0x0,
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@ -91,7 +90,7 @@ enum x86_dr7_condition {
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};
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/*
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* 0x2 is currently unimplemented - it reflects 8 bytes on modern CPUs
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* 0x2 is currently unimplemented - it reflects 8 bytes on modern CPUs.
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*/
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enum x86_dr7_length {
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X86_DR7_LENGTH_BYTE = 0x0,
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@ -107,46 +106,13 @@ enum x86_dr7_length {
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*/
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#define X86_DBREGS 4
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/*
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* Store the initial Debug Register state of CPU
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* This copy will be used to initialize new debug register state
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*/
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void x86_dbregs_setup_initdbstate(void);
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/*
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* Reset CPU Debug Registers - to be used after returning to user context
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*/
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void x86_dbregs_clear(struct lwp *l);
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/*
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* Retrieve Debug Registers from LWP's PCB and save in regs
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* In case of empty register set, initialize it
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*/
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void x86_dbregs_read(struct lwp *l, struct dbreg *regs);
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/*
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* Set CPU Debug Registers - to be used before entering user-land context
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*/
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void x86_dbregs_set(struct lwp *l);
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/*
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* Store DR6 in LWP - to be used in trap function
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*/
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void x86_dbregs_store_dr6(struct lwp *l);
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/*
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* Check if trap is triggered from user-land if so return nonzero value
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*/
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void x86_dbregs_init(void);
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void x86_dbregs_clear(struct lwp *);
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void x86_dbregs_read(struct lwp *, struct dbreg *);
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void x86_dbregs_set(struct lwp *);
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void x86_dbregs_store_dr6(struct lwp *);
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int x86_dbregs_user_trap(void);
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/*
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* Check if trap is triggered from user-land if so return nonzero value
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*/
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int x86_dbregs_validate(const struct dbreg *regs);
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/*
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* Write new Debug Registers from regs into LWP's PCB
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*/
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void x86_dbregs_write(struct lwp *l, const struct dbreg *regs);
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int x86_dbregs_validate(const struct dbreg *);
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void x86_dbregs_write(struct lwp *, const struct dbreg *);
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#endif /* !_X86_DBREGS_H_ */
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@ -1,6 +1,6 @@
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/* $NetBSD: dbregs.c,v 1.9 2018/04/08 14:21:23 kamil Exp $ */
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/* $NetBSD: dbregs.c,v 1.10 2018/07/22 15:02:51 maxv Exp $ */
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/*-
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/*
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* Copyright (c) 2016 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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@ -26,7 +26,6 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/types.h>
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#include <sys/lwp.h>
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@ -39,7 +38,7 @@
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#include <machine/pmap.h>
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extern struct pool x86_dbregspl;
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struct pool x86_dbregspl;
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static struct dbreg initdbstate;
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@ -56,7 +55,7 @@ static struct dbreg initdbstate;
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X86_DR7_GLOBAL_DR3_BREAKPOINT )
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void
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x86_dbregs_setup_initdbstate(void)
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x86_dbregs_init(void)
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{
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/* DR0-DR3 should always be 0 */
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initdbstate.dr[0] = rdr0();
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@ -70,14 +69,14 @@ x86_dbregs_setup_initdbstate(void)
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/* DR8-DR15 are reserved - skip */
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/*
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* Paranoid case.
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*
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* Explicitly reset some bits just in case they could be
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* set by brave software/hardware before the kernel boot.
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*/
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initdbstate.dr[6] &= ~X86_BREAKPOINT_CONDITION_DETECTED;
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initdbstate.dr[7] &= ~X86_DR7_GENERAL_DETECT_ENABLE;
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pool_init(&x86_dbregspl, sizeof(struct dbreg), 16, 0, 0, "dbregs",
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NULL, IPL_NONE);
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}
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void
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@ -88,16 +87,16 @@ x86_dbregs_clear(struct lwp *l)
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KASSERT(pcb->pcb_dbregs == NULL);
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/*
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* It's sufficient to just disable Debug Control Register (DR7)
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* it will deactivate hardware watchpoints
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* It's sufficient to just disable Debug Control Register (DR7).
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* It will deactivate hardware watchpoints.
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*/
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ldr7(0);
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/*
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* However at some point we need to clear Debug Status Registers (DR6)
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* CPU will never do it automatically
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* However at some point we need to clear Debug Status Registers
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* (DR6). The CPU will never do it automatically.
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*
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* Clear BREAKPOINT_CONDITION_DETECTED bits and ignore the rest
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* Clear BREAKPOINT_CONDITION_DETECTED bits and ignore the rest.
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*/
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ldr6(rdr6() & ~X86_BREAKPOINT_CONDITION_DETECTED);
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}
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@ -135,6 +134,7 @@ x86_dbregs_store_dr6(struct lwp *l)
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{
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struct pcb *pcb = lwp_getpcb(l);
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KASSERT(l == curlwp);
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KASSERT(pcb->pcb_dbregs != NULL);
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pcb->pcb_dbregs->dr[6] = rdr6();
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@ -143,15 +143,14 @@ x86_dbregs_store_dr6(struct lwp *l)
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int
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x86_dbregs_user_trap(void)
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{
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register_t dr7, dr6; /* debug registers dr6 and dr7 */
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register_t bp; /* breakpoint bits extracted from dr6 */
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register_t dr7, dr6;
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register_t bp;
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dr7 = rdr7();
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if ((dr7 & X86_GLOBAL_BREAKPOINT) == 0) {
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/*
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* all Global Breakpoint bits in the DR7 register are zero,
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* thus the trap couldn't have been caused by the
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* hardware debug registers
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* All Global Breakpoint bits are zero, thus the trap couldn't
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* have been caused by the hardware debug registers.
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*/
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return 0;
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}
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@ -161,15 +160,15 @@ x86_dbregs_user_trap(void)
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if (!bp) {
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/*
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* None of the breakpoint bits are set meaning this
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* trap was not caused by any of the debug registers
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* None of the breakpoint bits are set, meaning this
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* trap was not caused by any of the debug registers.
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*/
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return 0;
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}
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/*
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* at least one of the breakpoints were hit, check to see
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* which ones and if any of them are user space addresses
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* At least one of the breakpoints was hit, check to see
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* which ones and if any of them are user space addresses.
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*/
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if (bp & X86_DR6_DR0_BREAKPOINT_CONDITION_DETECTED)
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@ -197,12 +196,14 @@ x86_dbregs_validate(const struct dbreg *regs)
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size_t i;
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/* Check that DR0-DR3 contain user-space address */
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for (i = 0; i < X86_DBREGS; i++)
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for (i = 0; i < X86_DBREGS; i++) {
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if (regs->dr[i] >= (vaddr_t)VM_MAXUSER_ADDRESS)
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return EINVAL;
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}
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if (regs->dr[7] & X86_DR7_GENERAL_DETECT_ENABLE)
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if (regs->dr[7] & X86_DR7_GENERAL_DETECT_ENABLE) {
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return EINVAL;
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}
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/*
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* Skip checks for reserved registers (DR4-DR5, DR8-DR15).
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@ -216,8 +217,9 @@ x86_dbregs_write(struct lwp *l, const struct dbreg *regs)
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{
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struct pcb *pcb = lwp_getpcb(l);
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if (pcb->pcb_dbregs == NULL)
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if (pcb->pcb_dbregs == NULL) {
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pcb->pcb_dbregs = pool_get(&x86_dbregspl, PR_WAITOK);
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}
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memcpy(pcb->pcb_dbregs, regs, sizeof(*regs));
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}
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