Aren
/
NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

wm(4): Add RQDPC(Receive Queue Drop Packet Count) to iqdrops. 

The iqdrops counter should include not only MPC(Missed Packet Count)
but also RQDPC(Receive Queue Drop Packet Count). Same as ixgbe(4) and igc(4).

 Note that the RQDPC is not currently counted because SRRCTL_DROP_EN
is not set.
This commit is contained in:
msaitoh 2024-01-29 05:02:06 +00:00
parent c74656f40c
commit 2af43e2877
2 changed files with 30 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
sys/dev/pci/if_wm.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_wm.c,v 1.794 2024/01/26 03:23:36 msaitoh Exp $ */
/* $NetBSD: if_wm.c,v 1.795 2024/01/29 05:02:06 msaitoh Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@ -82,7 +82,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.794 2024/01/26 03:23:36 msaitoh Exp $");
__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.795 2024/01/29 05:02:06 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_if_wm.h"
@ -460,9 +460,9 @@ struct wm_rxqueue {
/* RX event counters */
WM_Q_EVCNT_DEFINE(rxq, intr); /* Interrupts */
WM_Q_EVCNT_DEFINE(rxq, defer); /* Rx deferred processing */
WM_Q_EVCNT_DEFINE(rxq, ipsum); /* IP checksums checked */
WM_Q_EVCNT_DEFINE(rxq, tusum); /* TCP/UDP cksums checked */
WM_Q_EVCNT_DEFINE(rxq, qdrop); /* Rx queue drop packet */
#endif
};
@ -6639,6 +6639,8 @@ wm_update_stats(struct wm_softc *sc)
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
uint64_t crcerrs, algnerrc, symerrc, mpc, colc, sec, rlec, rxerrc,
cexterr;
uint64_t total_qdrop = 0;
int i;
crcerrs = CSR_READ(sc, WMREG_CRCERRS);
symerrc = CSR_READ(sc, WMREG_SYMERRC);
@ -6787,6 +6789,20 @@ wm_update_stats(struct wm_softc *sc)
WM_EVCNT_ADD(&sc->sc_ev_lenerrs, CSR_READ(sc, WMREG_LENERRS));
WM_EVCNT_ADD(&sc->sc_ev_scvpc, CSR_READ(sc, WMREG_SCVPC));
WM_EVCNT_ADD(&sc->sc_ev_hrmpc, CSR_READ(sc, WMREG_HRMPC));
for (i = 0; i < sc->sc_nqueues; i++) {
struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
uint32_t rqdpc;
rqdpc = CSR_READ(sc, WMREG_RQDPC(i));
/*
* On I210 and newer device, the RQDPC register is not
* cleard on read.
*/
if ((rqdpc != 0) && (sc->sc_type >= WM_T_I210))
CSR_WRITE(sc, WMREG_RQDPC(i), 0);
WM_Q_EVCNT_ADD(rxq, qdrop, rqdpc);
total_qdrop += rqdpc;
}
}
if ((sc->sc_type >= WM_T_I350) && !WM_IS_ICHPCH(sc)) {
WM_EVCNT_ADD(&sc->sc_ev_tlpic, CSR_READ(sc, WMREG_TLPIC));
@ -6815,7 +6831,7 @@ wm_update_stats(struct wm_softc *sc)
* If you want to know the nubmer of WMREG_RMBC, you should use such as
* own EVCNT instead of if_iqdrops.
*/
if_statadd_ref(nsr, if_iqdrops, mpc);
if_statadd_ref(nsr, if_iqdrops, mpc + total_qdrop);
IF_STAT_PUTREF(ifp);
}
@ -6833,6 +6849,8 @@ wm_clear_evcnt(struct wm_softc *sc)
WM_Q_EVCNT_STORE(rxq, defer, 0);
WM_Q_EVCNT_STORE(rxq, ipsum, 0);
WM_Q_EVCNT_STORE(rxq, tusum, 0);
if ((sc->sc_type >= WM_T_82575) && !WM_IS_ICHPCH(sc))
WM_Q_EVCNT_STORE(rxq, qdrop, 0);
}
/* TX queues */
@ -8195,9 +8213,10 @@ wm_alloc_txrx_queues(struct wm_softc *sc)
WM_Q_INTR_EVCNT_ATTACH(rxq, intr, rxq, i, xname);
WM_Q_INTR_EVCNT_ATTACH(rxq, defer, rxq, i, xname);
WM_Q_MISC_EVCNT_ATTACH(rxq, ipsum, rxq, i, xname);
WM_Q_MISC_EVCNT_ATTACH(rxq, tusum, rxq, i, xname);
if ((sc->sc_type >= WM_T_82575) && !WM_IS_ICHPCH(sc))
WM_Q_MISC_EVCNT_ATTACH(rxq, qdrop, rxq, i, xname);
#endif /* WM_EVENT_COUNTERS */
rx_done++;
@ -8248,6 +8267,8 @@ wm_free_txrx_queues(struct wm_softc *sc)
WM_Q_EVCNT_DETACH(rxq, defer, rxq, i);
WM_Q_EVCNT_DETACH(rxq, ipsum, rxq, i);
WM_Q_EVCNT_DETACH(rxq, tusum, rxq, i);
if ((sc->sc_type >= WM_T_82575) && !WM_IS_ICHPCH(sc))
WM_Q_EVCNT_DETACH(rxq, qdrop, rxq, i);
#endif /* WM_EVENT_COUNTERS */
wm_free_rx_buffer(sc, rxq);

5
sys/dev/pci/if_wmreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_wmreg.h,v 1.130 2023/05/11 07:19:02 msaitoh Exp $ */
/* $NetBSD: if_wmreg.h,v 1.131 2024/01/29 05:02:06 msaitoh Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@ -857,6 +857,9 @@ struct livengood_tcpip_ctxdesc {
#define RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
#define RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */
#define WMREG_RQDPC(x) (((x) < 4) ? (0x2830 + (0x100 * (x))) : \
(0xc030 + (0x40 * (x)))) /* Receive Queue Drop Packet Count */
#define WMREG_OLD_RDTR1 0x0130 /* Receive Delay Timer (ring 1) */
#define WMREG_OLD_RDBA1_LO 0x0138 /* Receive Descriptor Base Low (ring 1) */
#define WMREG_OLD_RDBA1_HI 0x013c /* Receive Descriptor Base High (ring 1) */