using devmap for static mapping
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fc035bc8fd
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2a9dfe7684
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@ -1,4 +1,4 @@
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/* $NetBSD: ixp12x0.c,v 1.8 2003/06/15 23:08:56 fvdl Exp $ */
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/* $NetBSD: ixp12x0.c,v 1.9 2003/07/13 01:01:50 igy Exp $ */
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/*
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* Copyright (c) 2002, 2003
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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@ -33,7 +33,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ixp12x0.c,v 1.8 2003/06/15 23:08:56 fvdl Exp $");
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__KERNEL_RCSID(0, "$NetBSD: ixp12x0.c,v 1.9 2003/07/13 01:01:50 igy Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -206,75 +206,6 @@ ixp12x0_pcibus_print(void *aux, const char *pnp)
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return (UNCONF);
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}
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/*
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* IXP12x0 specific I/O registers mapping table
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*/
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static struct pmap_ent map_tbl_ixp12x0[] = {
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{ "StrongARM System and Peripheral Registers",
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IXP12X0_SYS_VBASE, IXP12X0_SYS_HWBASE,
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IXP12X0_SYS_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE, },
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{ "PCI Registers Accessible Through StrongARM Core",
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IXP12X0_PCI_VBASE, IXP12X0_PCI_HWBASE,
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IXP12X0_PCI_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE, },
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{ "PCI Registers Accessible Through I/O Cycle Access",
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IXP12X0_PCI_IO_VBASE, IXP12X0_PCI_IO_HWBASE,
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IXP12X0_PCI_IO_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE, },
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{ "PCI Registers Accessible Through Memory Cycle Access",
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IXP12X0_PCI_MEM_VBASE, IXP12X0_PCI_MEM_HWBASE,
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IXP12X0_PCI_MEM_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE, },
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{ "PCI Type0 Configuration Space",
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IXP12X0_PCI_TYPE0_VBASE, IXP12X0_PCI_TYPE0_HWBASE,
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IXP12X0_PCI_TYPE0_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE, },
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{ "PCI Type1 Configuration Space",
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IXP12X0_PCI_TYPE1_VBASE, IXP12X0_PCI_TYPE1_HWBASE,
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IXP12X0_PCI_TYPE1_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE, },
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{ NULL, 0, 0, 0, 0, 0 },
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};
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/*
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* mapping virtual memories
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*/
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void
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ixp12x0_pmap_chunk_table(vaddr_t l1pt, struct pmap_ent* m)
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{
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int loop;
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loop = 0;
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while (m[loop].msg) {
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printf("mapping %s...\n", m[loop].msg);
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pmap_map_chunk(l1pt, m[loop].va, m[loop].pa,
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m[loop].sz, m[loop].prot, m[loop].cache);
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++loop;
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}
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}
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/*
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* mapping I/O registers
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*/
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void
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ixp12x0_pmap_io_reg(vaddr_t l1pt)
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{
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ixp12x0_pmap_chunk_table(l1pt, map_tbl_ixp12x0);
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}
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void
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ixp12x0_reset(void)
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{
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@ -1,4 +1,4 @@
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/* $NetBSD: ixm1200_machdep.c,v 1.25 2003/05/22 05:47:10 thorpej Exp $ */
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/* $NetBSD: ixm1200_machdep.c,v 1.26 2003/07/13 01:01:51 igy Exp $ */
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/*
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* Copyright (c) 2002, 2003
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@ -67,7 +67,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ixm1200_machdep.c,v 1.25 2003/05/22 05:47:10 thorpej Exp $");
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__KERNEL_RCSID(0, "$NetBSD: ixm1200_machdep.c,v 1.26 2003/07/13 01:01:51 igy Exp $");
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#include "opt_ddb.h"
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#include "opt_pmap_debug.h"
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@ -300,6 +300,53 @@ cpu_reboot(howto, bootstr)
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for (;;);
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}
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/* Static device mappings. */
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static const struct pmap_devmap ixm1200_devmap[] = {
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/* StrongARM System and Peripheral Registers */
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{
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IXP12X0_SYS_VBASE,
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IXP12X0_SYS_HWBASE,
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IXP12X0_SYS_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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/* PCI Registers Accessible Through StrongARM Core */
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{
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IXP12X0_PCI_VBASE, IXP12X0_PCI_HWBASE,
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IXP12X0_PCI_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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/* PCI Registers Accessible Through I/O Cycle Access */
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{
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IXP12X0_PCI_IO_VBASE, IXP12X0_PCI_IO_HWBASE,
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IXP12X0_PCI_IO_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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/* PCI Type0 Configuration Space */
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{
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IXP12X0_PCI_TYPE0_VBASE, IXP12X0_PCI_TYPE0_HWBASE,
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IXP12X0_PCI_TYPE0_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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/* PCI Type1 Configuration Space */
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{
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IXP12X0_PCI_TYPE1_VBASE, IXP12X0_PCI_TYPE1_HWBASE,
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IXP12X0_PCI_TYPE1_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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{
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0,
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0,
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0,
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0,
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0
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},
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};
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/*
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* Initial entry point on startup. This gets called before main() is
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* entered.
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@ -562,11 +609,8 @@ initarm(void *arg)
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systempage.pv_pa, vector_page);
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#endif
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/*
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* Map the PCI I/O spaces and IXP12x0 registers
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*/
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ixp12x0_pmap_io_reg(l1pagetable);
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/* Map the statically mapped devices. */
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pmap_devmap_bootstrap(l1pagetable, ixm1200_devmap);
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#ifdef VERBOSE_INIT_ARM
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printf("done.\n");
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@ -744,6 +788,8 @@ consinit(void)
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consinit_called = 1;
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pmap_devmap_register(ixm1200_devmap);
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if (ixpcomcnattach(&ixpsip_bs_tag,
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IXPCOM_UART_HWBASE, IXPCOM_UART_VBASE,
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CONSPEED, CONMODE))
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