using devmap for static mapping

This commit is contained in:
igy 2003-07-13 01:01:50 +00:00
parent fc035bc8fd
commit 2a9dfe7684
2 changed files with 55 additions and 78 deletions

View File

@ -1,4 +1,4 @@
/* $NetBSD: ixp12x0.c,v 1.8 2003/06/15 23:08:56 fvdl Exp $ */
/* $NetBSD: ixp12x0.c,v 1.9 2003/07/13 01:01:50 igy Exp $ */
/*
* Copyright (c) 2002, 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ixp12x0.c,v 1.8 2003/06/15 23:08:56 fvdl Exp $");
__KERNEL_RCSID(0, "$NetBSD: ixp12x0.c,v 1.9 2003/07/13 01:01:50 igy Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -206,75 +206,6 @@ ixp12x0_pcibus_print(void *aux, const char *pnp)
return (UNCONF);
}
/*
* IXP12x0 specific I/O registers mapping table
*/
static struct pmap_ent map_tbl_ixp12x0[] = {
{ "StrongARM System and Peripheral Registers",
IXP12X0_SYS_VBASE, IXP12X0_SYS_HWBASE,
IXP12X0_SYS_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE, },
{ "PCI Registers Accessible Through StrongARM Core",
IXP12X0_PCI_VBASE, IXP12X0_PCI_HWBASE,
IXP12X0_PCI_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE, },
{ "PCI Registers Accessible Through I/O Cycle Access",
IXP12X0_PCI_IO_VBASE, IXP12X0_PCI_IO_HWBASE,
IXP12X0_PCI_IO_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE, },
{ "PCI Registers Accessible Through Memory Cycle Access",
IXP12X0_PCI_MEM_VBASE, IXP12X0_PCI_MEM_HWBASE,
IXP12X0_PCI_MEM_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE, },
{ "PCI Type0 Configuration Space",
IXP12X0_PCI_TYPE0_VBASE, IXP12X0_PCI_TYPE0_HWBASE,
IXP12X0_PCI_TYPE0_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE, },
{ "PCI Type1 Configuration Space",
IXP12X0_PCI_TYPE1_VBASE, IXP12X0_PCI_TYPE1_HWBASE,
IXP12X0_PCI_TYPE1_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE, },
{ NULL, 0, 0, 0, 0, 0 },
};
/*
* mapping virtual memories
*/
void
ixp12x0_pmap_chunk_table(vaddr_t l1pt, struct pmap_ent* m)
{
int loop;
loop = 0;
while (m[loop].msg) {
printf("mapping %s...\n", m[loop].msg);
pmap_map_chunk(l1pt, m[loop].va, m[loop].pa,
m[loop].sz, m[loop].prot, m[loop].cache);
++loop;
}
}
/*
* mapping I/O registers
*/
void
ixp12x0_pmap_io_reg(vaddr_t l1pt)
{
ixp12x0_pmap_chunk_table(l1pt, map_tbl_ixp12x0);
}
void
ixp12x0_reset(void)
{

View File

@ -1,4 +1,4 @@
/* $NetBSD: ixm1200_machdep.c,v 1.25 2003/05/22 05:47:10 thorpej Exp $ */
/* $NetBSD: ixm1200_machdep.c,v 1.26 2003/07/13 01:01:51 igy Exp $ */
/*
* Copyright (c) 2002, 2003
@ -67,7 +67,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ixm1200_machdep.c,v 1.25 2003/05/22 05:47:10 thorpej Exp $");
__KERNEL_RCSID(0, "$NetBSD: ixm1200_machdep.c,v 1.26 2003/07/13 01:01:51 igy Exp $");
#include "opt_ddb.h"
#include "opt_pmap_debug.h"
@ -300,6 +300,53 @@ cpu_reboot(howto, bootstr)
for (;;);
}
/* Static device mappings. */
static const struct pmap_devmap ixm1200_devmap[] = {
/* StrongARM System and Peripheral Registers */
{
IXP12X0_SYS_VBASE,
IXP12X0_SYS_HWBASE,
IXP12X0_SYS_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
/* PCI Registers Accessible Through StrongARM Core */
{
IXP12X0_PCI_VBASE, IXP12X0_PCI_HWBASE,
IXP12X0_PCI_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
/* PCI Registers Accessible Through I/O Cycle Access */
{
IXP12X0_PCI_IO_VBASE, IXP12X0_PCI_IO_HWBASE,
IXP12X0_PCI_IO_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
/* PCI Type0 Configuration Space */
{
IXP12X0_PCI_TYPE0_VBASE, IXP12X0_PCI_TYPE0_HWBASE,
IXP12X0_PCI_TYPE0_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
/* PCI Type1 Configuration Space */
{
IXP12X0_PCI_TYPE1_VBASE, IXP12X0_PCI_TYPE1_HWBASE,
IXP12X0_PCI_TYPE1_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
{
0,
0,
0,
0,
0
},
};
/*
* Initial entry point on startup. This gets called before main() is
* entered.
@ -562,11 +609,8 @@ initarm(void *arg)
systempage.pv_pa, vector_page);
#endif
/*
* Map the PCI I/O spaces and IXP12x0 registers
*/
ixp12x0_pmap_io_reg(l1pagetable);
/* Map the statically mapped devices. */
pmap_devmap_bootstrap(l1pagetable, ixm1200_devmap);
#ifdef VERBOSE_INIT_ARM
printf("done.\n");
@ -744,6 +788,8 @@ consinit(void)
consinit_called = 1;
pmap_devmap_register(ixm1200_devmap);
if (ixpcomcnattach(&ixpsip_bs_tag,
IXPCOM_UART_HWBASE, IXPCOM_UART_VBASE,
CONSPEED, CONMODE))