Misc minor cleanup for arc interrupt handlers:
- always enable options MIPS3_ENABLE_CLOCK_INTR and just clear the compare register in cpu_intr() to make CLKF_BASE() works properly - prepare only possible number of cpu_inttab - use macro for interrupt priority number passed to arc_set_intr() to avoid confusion - merge arc_hardware_intr() into cpu_intr() - check independent timer interrupt first in cpu_intr() - tweak MIPS_SR_INT_IE before calling hardclock timer handlers so that spllowersoftclock(9) will be invoked properly in hardclock(9) - reenable interrupt for timer in cpu_intr() rather than each timer handlers okay'ed by soda. Note the real fix is to make CLKF_BASE() check all independent interrupt sources including jazz and isa devices.
This commit is contained in:
tsutsui
parent
648df6ea96
commit
2a8a21a021
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@ -1,4 +1,4 @@
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/* $NetBSD: arc_trap.c,v 1.32 2006/06/17 14:11:16 tsutsui Exp $ */
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/* $NetBSD: arc_trap.c,v 1.33 2006/06/24 03:50:38 tsutsui Exp $ */
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/* $OpenBSD: trap.c,v 1.22 1999/05/24 23:08:59 jason Exp $ */
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/*
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@ -78,7 +78,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: arc_trap.c,v 1.32 2006/06/17 14:11:16 tsutsui Exp $");
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__KERNEL_RCSID(0, "$NetBSD: arc_trap.c,v 1.33 2006/06/24 03:50:38 tsutsui Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -95,43 +95,14 @@ __KERNEL_RCSID(0, "$NetBSD: arc_trap.c,v 1.32 2006/06/17 14:11:16 tsutsui Exp $"
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#include <arc/jazz/pica.h>
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#include <arc/jazz/rd94.h>
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uint32_t arc_hardware_intr(uint32_t, uint32_t, uint32_t, uint32_t);
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#define MIPS_INT_LEVELS 8
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struct {
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struct cpu_inttab {
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uint32_t int_mask;
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uint32_t (*int_hand)(uint32_t, struct clockframe *);
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} cpu_int_tab[MIPS_INT_LEVELS];
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};
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static struct cpu_inttab cpu_int_tab[ARC_NINTPRI];
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uint32_t cpu_int_mask; /* External cpu interrupt mask */
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uint32_t
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arc_hardware_intr(uint32_t status, uint32_t cause, uint32_t pc,
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uint32_t ipending)
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{
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int i;
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struct clockframe cf;
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cf.pc = pc;
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cf.sr = status;
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/*
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* Check off all enabled interrupts. Called interrupt routine
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* returns mask of interrupts to reenable.
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*/
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for (i = 0; i < MIPS_INT_LEVELS; i++) {
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if (cpu_int_tab[i].int_mask & ipending) {
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cause &= (*cpu_int_tab[i].int_hand)(ipending, &cf);
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}
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}
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/*
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* Reenable all non served hardware levels.
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*/
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return cause;
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}
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/*
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* Set up handler for external interrupt events.
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* Events are checked in priority order.
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@ -141,7 +112,7 @@ arc_set_intr(uint32_t mask, uint32_t (*int_hand)(uint32_t, struct clockframe *),
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int prio)
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{
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if (prio > MIPS_INT_LEVELS)
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if (prio >= ARC_NINTPRI)
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panic("arc_set_intr: too high priority");
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if (cpu_int_tab[prio].int_mask != 0 &&
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@ -162,23 +133,66 @@ arc_set_intr(uint32_t mask, uint32_t (*int_hand)(uint32_t, struct clockframe *),
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void
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cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
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{
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uint32_t handled;
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struct clockframe cf;
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struct cpu_inttab *inttab;
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u_int i;
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uvmexp.intrs++;
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cf.pc = pc;
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cf.sr = status;
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/* check MIPS3 internal clock interrupt */
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if (ipending & MIPS_INT_MASK_5) {
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/*
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* Writing a value to the Compare register,
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* as a side effect, clears the timer interrupt request.
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*/
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mips3_cp0_compare_write(mips3_cp0_count_read());
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mips3_cp0_compare_write(0);
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cause &= ~MIPS_INT_MASK_5;
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}
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_splset((status & MIPS_INT_MASK_5) | MIPS_SR_INT_IE);
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uvmexp.intrs++;
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handled = cause;
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/* real device interrupt */
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if (ipending & MIPS3_HARD_INT_MASK) {
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handled = arc_hardware_intr(status, cause, pc, ipending);
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/*
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* If there is an independent timer interrupt handler, call it first.
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* Called interrupt routine returns mask of interrupts to be reenabled.
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*/
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inttab = &cpu_int_tab[ARC_INTPRI_TIMER_INT];
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if (inttab->int_mask & ipending) {
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if ((ipending & MIPS_INT_MASK & ~inttab->int_mask) == 0) {
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/*
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* If all interrupts were enabled and there is no
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* pending interrupts, set MIPS_SR_INT_IE so that
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* spllowerclock() in hardclock() works properly.
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*/
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#if 0 /* MIPS_SR_INT_IE is enabled above */
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_splset(MIPS_SR_INT_IE);
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#endif
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} else {
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/*
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* If there are any pending interrputs, clear
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* MIPS_SR_INT_IE in cf.sr so that spllowerclock()
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* in hardclock() will not happen.
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*/
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cf.sr &= ~MIPS_SR_INT_IE;
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}
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cause &= (*inttab->int_hand)(ipending, &cf);
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}
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_splset((status & ~handled & MIPS3_HARD_INT_MASK) | MIPS_SR_INT_IE);
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_splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
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inttab++;
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/*
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* Check off all other enabled interrupts.
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* Called handlers return mask of interrupts to be reenabled.
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*/
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for (i = ARC_INTPRI_TIMER_INT + 1; i < ARC_NINTPRI; i++) {
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if (inttab->int_mask & ipending) {
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cause &= (*inttab->int_hand)(ipending, &cf);
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}
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inttab++;
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}
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_splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
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/* software interrupts */
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ipending &= (MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0);
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@ -1,4 +1,4 @@
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/* $NetBSD: c_magnum.c,v 1.13 2005/12/11 12:16:37 christos Exp $ */
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/* $NetBSD: c_magnum.c,v 1.14 2006/06/24 03:50:38 tsutsui Exp $ */
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/* $OpenBSD: machdep.c,v 1.36 1999/05/22 21:22:19 weingart Exp $ */
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/*
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: c_magnum.c,v 1.13 2005/12/11 12:16:37 christos Exp $");
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__KERNEL_RCSID(0, "$NetBSD: c_magnum.c,v 1.14 2006/06/24 03:50:38 tsutsui Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -174,9 +174,6 @@ timer_magnum_intr(uint32_t mask, struct clockframe *cf)
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hardclock(cf);
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timer_jazzio_ev.ev_count++;
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/* Re-enable clock interrupts */
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splx(MIPS_INT_MASK_4 | MIPS_SR_INT_IE);
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return ~MIPS_INT_MASK_4; /* Keep clock interrupts enabled */
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: c_nec_jazz.c,v 1.11 2005/12/11 12:16:37 christos Exp $ */
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/* $NetBSD: c_nec_jazz.c,v 1.12 2006/06/24 03:50:38 tsutsui Exp $ */
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/*-
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* Copyright (C) 2000 Shuichiro URATA. All rights reserved.
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@ -31,7 +31,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: c_nec_jazz.c,v 1.11 2005/12/11 12:16:37 christos Exp $");
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__KERNEL_RCSID(0, "$NetBSD: c_nec_jazz.c,v 1.12 2006/06/24 03:50:38 tsutsui Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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hardclock(cf);
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timer_jazzio_ev.ev_count++;
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/* Re-enable clock interrupts */
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splx(MIPS_INT_MASK_3 | MIPS_SR_INT_IE);
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return ~MIPS_INT_MASK_3; /* Keep clock interrupts enabled */
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}
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# $NetBSD: std.arc,v 1.20 2005/12/11 12:16:38 christos Exp $
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# $NetBSD: std.arc,v 1.21 2006/06/24 03:50:38 tsutsui Exp $
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# standard arc info
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machine arc mips
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# set CPU architecture level for kernel target
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#options MIPS1 # R2000/R3000 support
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options MIPS3 # R4000/R4400 support
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options MIPS3_ENABLE_CLOCK_INTR
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# arc port use wired map for device space
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options ENABLE_MIPS3_WIRED_MAP
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@ -1,4 +1,4 @@
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/* $NetBSD: arcsisabr.c,v 1.2 2006/06/12 15:06:32 tsutsui Exp $ */
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/* $NetBSD: arcsisabr.c,v 1.3 2006/06/24 03:50:38 tsutsui Exp $ */
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/* $OpenBSD: isabus.c,v 1.15 1998/03/16 09:38:46 pefo Exp $ */
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/* NetBSD: isa.c,v 1.33 1995/06/28 04:30:51 cgd Exp */
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: arcsisabr.c,v 1.2 2006/06/12 15:06:32 tsutsui Exp $");
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__KERNEL_RCSID(0, "$NetBSD: arcsisabr.c,v 1.3 2006/06/24 03:50:38 tsutsui Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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struct isabr_softc *sc = (struct isabr_softc *)self;
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isadma_bounce_tag_init(&sc->sc_dmat);
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(*platform->set_intr)(MIPS_INT_MASK_2, isabr_iointr, 2);
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(*platform->set_intr)(MIPS_INT_MASK_2, isabr_iointr, ARC_INTPRI_PCIISA);
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isabrattach(sc);
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}
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/* $NetBSD: tyneisabr.c,v 1.9 2006/04/15 08:49:47 tsutsui Exp $ */
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/* $NetBSD: tyneisabr.c,v 1.10 2006/06/24 03:50:38 tsutsui Exp $ */
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/* $OpenBSD: isabus.c,v 1.15 1998/03/16 09:38:46 pefo Exp $ */
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/* NetBSD: isa.c,v 1.33 1995/06/28 04:30:51 cgd Exp */
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: tyneisabr.c,v 1.9 2006/04/15 08:49:47 tsutsui Exp $");
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__KERNEL_RCSID(0, "$NetBSD: tyneisabr.c,v 1.10 2006/06/24 03:50:38 tsutsui Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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struct isabr_softc *sc = (struct isabr_softc *)self;
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_bus_dma_tag_init(&sc->sc_dmat); /* XXX dedicated bounce mem */
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(*platform->set_intr)(MIPS_INT_MASK_2, isabr_iointr, 2);
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(*platform->set_intr)(MIPS_INT_MASK_2, isabr_iointr, ARC_INTPRI_PCIISA);
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isabrattach(sc);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.h,v 1.15 2006/06/17 14:10:28 tsutsui Exp $ */
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/* $NetBSD: intr.h,v 1.16 2006/06/24 03:50:38 tsutsui Exp $ */
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/*-
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* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
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@ -117,6 +117,12 @@ struct clockframe;
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void arc_set_intr(uint32_t, uint32_t (*)(uint32_t, struct clockframe *), int);
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extern uint32_t cpu_int_mask;
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/* priority order to handle each CPU INT line specified via set_intr() */
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#define ARC_INTPRI_TIMER_INT 0 /* independent CPU INT for timer */
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#define ARC_INTPRI_JAZZ 1 /* CPU INT for JAZZ local bus */
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#define ARC_INTPRI_PCIISA 2 /* CPU INT for PCI/EISA/ISA */
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#define ARC_NINTPRI 3 /* number of total used CPU INTs */
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#endif /* !_LOCORE */
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#endif /* _KERNEL */
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@ -1,4 +1,4 @@
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/* $NetBSD: jazzio.c,v 1.16 2006/04/15 08:49:47 tsutsui Exp $ */
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/* $NetBSD: jazzio.c,v 1.17 2006/06/24 03:50:38 tsutsui Exp $ */
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/* $OpenBSD: picabus.c,v 1.11 1999/01/11 05:11:10 millert Exp $ */
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/* NetBSD: tc.c,v 1.2 1995/03/08 00:39:05 cgd Exp */
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@ -31,7 +31,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: jazzio.c,v 1.16 2006/04/15 08:49:47 tsutsui Exp $");
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__KERNEL_RCSID(0, "$NetBSD: jazzio.c,v 1.17 2006/06/24 03:50:38 tsutsui Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -131,7 +131,7 @@ jazzioattach(struct device *parent, struct device *self, void *aux)
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}
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/* set up interrupt handlers */
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(*platform->set_intr)(MIPS_INT_MASK_1, jazzio_intr, 2);
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(*platform->set_intr)(MIPS_INT_MASK_1, jazzio_intr, ARC_INTPRI_JAZZ);
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sc->sc_bus.ab_dv = (struct device *)sc;
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@ -1,4 +1,4 @@
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/* $NetBSD: jazzisabr.c,v 1.10 2006/04/15 08:49:47 tsutsui Exp $ */
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/* $NetBSD: jazzisabr.c,v 1.11 2006/06/24 03:50:38 tsutsui Exp $ */
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/* $OpenBSD: isabus.c,v 1.15 1998/03/16 09:38:46 pefo Exp $ */
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/* NetBSD: isa.c,v 1.33 1995/06/28 04:30:51 cgd Exp */
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@ -75,7 +75,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: jazzisabr.c,v 1.10 2006/04/15 08:49:47 tsutsui Exp $");
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__KERNEL_RCSID(0, "$NetBSD: jazzisabr.c,v 1.11 2006/06/24 03:50:38 tsutsui Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -117,7 +117,7 @@ jazzisabrattach(struct device *parent, struct device *self, void *aux)
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struct isabr_softc *sc = (struct isabr_softc *)self;
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jazz_bus_dma_tag_init(&sc->sc_dmat);
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(*platform->set_intr)(MIPS_INT_MASK_2, isabr_iointr, 3);
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(*platform->set_intr)(MIPS_INT_MASK_2, isabr_iointr, ARC_INTPRI_PCIISA);
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isabrattach(sc);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: timer_jazzio.c,v 1.8 2005/12/11 12:16:39 christos Exp $ */
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/* $NetBSD: timer_jazzio.c,v 1.9 2006/06/24 03:50:38 tsutsui Exp $ */
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/* $OpenBSD: clock.c,v 1.6 1998/10/15 21:30:15 imp Exp $ */
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/*
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@ -80,7 +80,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: timer_jazzio.c,v 1.8 2005/12/11 12:16:39 christos Exp $");
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__KERNEL_RCSID(0, "$NetBSD: timer_jazzio.c,v 1.9 2006/06/24 03:50:38 tsutsui Exp $");
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#include <sys/param.h>
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#include <sys/kernel.h>
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@ -146,7 +146,7 @@ timer_jazzio_attach(struct device *parent, struct device *self, void *aux)
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evcnt_attach_static(&timer_jazzio_ev);
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(*platform->set_intr)(timer_jazzio_conf->tjc_intr_mask,
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timer_jazzio_conf->tjc_intr, 1);
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timer_jazzio_conf->tjc_intr, ARC_INTPRI_TIMER_INT);
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timerattach(&sc->sc_dev, &timerfns_jazzio);
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@ -1,4 +1,4 @@
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/* $NetBSD: necpb.c,v 1.27 2006/04/16 07:10:45 tsutsui Exp $ */
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/* $NetBSD: necpb.c,v 1.28 2006/06/24 03:50:38 tsutsui Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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@ -68,7 +68,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: necpb.c,v 1.27 2006/04/16 07:10:45 tsutsui Exp $");
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||||
__KERNEL_RCSID(0, "$NetBSD: necpb.c,v 1.28 2006/06/24 03:50:38 tsutsui Exp $");
|
||||
|
||||
#include "opt_pci.h"
|
||||
|
||||
|
|
@ -259,7 +259,7 @@ necpbattach(struct device *parent, struct device *self, void *aux)
|
|||
for (i = 0; i < 4; i++)
|
||||
necpb_inttbl[i] = NULL;
|
||||
|
||||
(*platform->set_intr)(MIPS_INT_MASK_2, necpb_intr, 3);
|
||||
(*platform->set_intr)(MIPS_INT_MASK_2, necpb_intr, ARC_INTPRI_PCIISA);
|
||||
|
||||
pba.pba_iot = &sc->sc_ncp->nc_iot;
|
||||
pba.pba_memt = &sc->sc_ncp->nc_memt;
|
||||
|
|
|
|||
Loading…
Reference in New Issue