Disable UHS modes if signaling voltage regulator is unavailable.
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73ac277564
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29db065a43
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@ -1,4 +1,4 @@
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/* $NetBSD: tegra_sdhc.c,v 1.20 2017/05/25 23:53:50 jmcneill Exp $ */
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/* $NetBSD: tegra_sdhc.c,v 1.21 2017/07/21 01:00:58 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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@ -31,7 +31,7 @@
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#include "locators.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: tegra_sdhc.c,v 1.20 2017/05/25 23:53:50 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: tegra_sdhc.c,v 1.21 2017/07/21 01:00:58 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -165,6 +165,14 @@ tegra_sdhc_attach(device_t parent, device_t self, void *aux)
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"vqmmc-supply");
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if (sc->sc_reg_vqmmc) {
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sc->sc.sc_vendor_signal_voltage = tegra_sdhc_signal_voltage;
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} else {
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/* Regulator required for UHS signaling */
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sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS;
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sc->sc.sc_caps = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
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SDHC_CAPABILITIES);
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sc->sc.sc_caps2 = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
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SDHC_CAPABILITIES2);
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sc->sc.sc_caps2 &= ~(SDHC_SDR50_SUPP|SDHC_SDR104_SUPP|SDHC_DDR50_SUPP);
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}
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sc->sc_clk = fdtbus_clock_get_index(faa->faa_phandle, 0);
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