add aarch64 support for cpuctl identify.
This commit is contained in:
ryo
parent
cfdea5e9ed
commit
2972297404
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@ -0,0 +1,619 @@
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/* $NetBSD: aarch64.c,v 1.1 2018/05/03 15:47:36 ryo Exp $ */
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/*
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* Copyright (c) 2018 Ryo Shimizu <ryo@nerv.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#ifndef lint
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__RCSID("$NetBSD: aarch64.c,v 1.1 2018/05/03 15:47:36 ryo Exp $");
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#endif /* no lint */
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#include <sys/types.h>
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#include <sys/cpuio.h>
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#include <sys/sysctl.h>
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#include <stdio.h>
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#include <stdbool.h>
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#include <stdlib.h>
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#include <string.h>
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#include <inttypes.h>
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#include <err.h>
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#include <arm/cputypes.h>
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#include <aarch64/armreg.h>
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#include "../cpuctl.h"
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struct cpuidtab {
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uint32_t cpu_partnum;
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const char *cpu_name;
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const char *cpu_class;
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const char *cpu_architecture;
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};
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struct impltab {
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uint32_t impl_id;
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const char *impl_name;
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};
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struct fieldinfo {
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int bitpos;
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int bitwidth;
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const char *name;
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const char * const *info;
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};
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#define CPU_PARTMASK (CPU_ID_IMPLEMENTOR_MASK | CPU_ID_PARTNO_MASK)
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const struct cpuidtab cpuids[] = {
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{ CPU_ID_CORTEXA53R0 & CPU_PARTMASK, "Cortex-A53", "Cortex", "V8-A" },
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{ CPU_ID_CORTEXA57R0 & CPU_PARTMASK, "Cortex-A57", "Cortex", "V8-A" },
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{ CPU_ID_CORTEXA72R0 & CPU_PARTMASK, "Cortex-A72", "Cortex", "V8-A" },
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{ CPU_ID_CORTEXA73R0 & CPU_PARTMASK, "Cortex-A73", "Cortex", "V8-A" },
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{ CPU_ID_CORTEXA55R1 & CPU_PARTMASK, "Cortex-A55", "Cortex", "V8.2-A" },
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{ CPU_ID_CORTEXA75R2 & CPU_PARTMASK, "Cortex-A75", "Cortex", "V8.2-A" }
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};
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const struct impltab implids[] = {
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{ CPU_ID_ARM_LTD, "ARM Limited" },
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{ CPU_ID_BROADCOM, "Broadcom Corporation" },
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{ CPU_ID_CAVIUM, "Cavium Inc." },
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{ CPU_ID_DEC, "Digital Equipment Corporation" },
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{ CPU_ID_INFINEON, "Infineon Technologies AG" },
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{ CPU_ID_MOTOROLA, "Motorola or Freescale Semiconductor Inc." },
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{ CPU_ID_NVIDIA, "NVIDIA Corporation" },
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{ CPU_ID_APM, "Applied Micro Circuits Corporation" },
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{ CPU_ID_QUALCOMM, "Qualcomm Inc." },
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{ CPU_ID_SAMSUNG, "SAMSUNG" },
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{ CPU_ID_TI, "Texas Instruments" },
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{ CPU_ID_MARVELL, "Marvell International Ltd." },
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{ CPU_ID_APPLE, "Apple Inc." },
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{ CPU_ID_FARADAY, "Faraday Technology Corporation" },
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{ CPU_ID_INTEL, "Intel Corporation" }
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};
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/* ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0 */
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struct fieldinfo id_aa64pfr0_fieldinfo[] = {
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{
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.bitpos = 0, .bitwidth = 4, .name = "EL0",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No EL0",
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[1] = "AArch64",
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[2] = "AArch64/AArch32"
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}
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},
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{
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.bitpos = 4, .bitwidth = 4, .name = "EL1",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No EL1",
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[1] = "AArch64",
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[2] = "AArch64/AArch32"
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}
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},
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{
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.bitpos = 8, .bitwidth = 4, .name = "EL2",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No EL2",
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[1] = "AArch64",
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[2] = "AArch64/AArch32"
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}
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},
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{
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.bitpos = 12, .bitwidth = 4, .name = "EL3",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No EL3",
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[1] = "AArch64",
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[2] = "AArch64/AArch32"
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}
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},
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{
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.bitpos = 16, .bitwidth = 4, .name = "FP",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "Floating Point",
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[15] = "No Floating Point"
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}
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},
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{
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.bitpos = 20, .bitwidth = 4, .name = "AdvSIMD",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "Advanced SIMD",
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[15] = "No Advanced SIMD"
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}
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},
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{
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.bitpos = 24, .bitwidth = 4, .name = "GIC",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No GIC",
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[1] = "GICv3"
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}
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},
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{ .bitwidth = 0 } /* end of table */
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};
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/* ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0 */
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struct fieldinfo id_aa64isar0_fieldinfo[] = {
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{
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.bitpos = 4, .bitwidth = 4, .name = "AES",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No AES",
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[1] = "AESE/AESD/AESMC/AESIMC",
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[2] = "AESE/AESD/AESMC/AESIMC+PMULL/PMULL2"
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}
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},
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{
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.bitpos = 8, .bitwidth = 4, .name = "SHA1",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No SHA1",
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[1] = "SHA1C/SHA1P/SHA1M/SHA1H/SHA1SU0/SHA1SU1"
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}
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},
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{
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.bitpos = 12, .bitwidth = 4, .name = "SHA2",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No SHA2",
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[1] = "SHA256H/SHA256H2/SHA256SU0/SHA256U1"
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}
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},
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{
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.bitpos = 16, .bitwidth = 4, .name = "CRC32",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No CRC32",
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[1] = "CRC32B/CRC32H/CRC32W/CRC32X"
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"/CRC32CB/CRC32CH/CRC32CW/CRC32CX"
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}
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},
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{ .bitwidth = 0 } /* end of table */
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};
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/* ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0 */
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struct fieldinfo id_aa64mmfr0_fieldinfo[] = {
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{
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.bitpos = 0, .bitwidth = 4, .name = "PARange",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "32bits/4GB",
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[1] = "36bits/64GB",
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[2] = "40bits/1TB",
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[3] = "42bits/4TB",
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[4] = "44bits/16TB",
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[5] = "48bits/256TB"
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}
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},
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{
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.bitpos = 4, .bitwidth = 4, .name = "ASIDBit",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "8bits",
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[2] = "16bits"
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}
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},
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{
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.bitpos = 8, .bitwidth = 4, .name = "BigEnd",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No mixed-endian",
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[1] = "Mixed-endian"
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}
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},
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{
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.bitpos = 12, .bitwidth = 4, .name = "SNSMem",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No distinction B/W Secure and Non-secure Memory",
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[1] = "Distinction B/W Secure and Non-secure Memory"
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}
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},
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{
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.bitpos = 16, .bitwidth = 4, .name = "BigEndEL0",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No mixed-endian at EL0",
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[1] = "Mixed-endian at EL0"
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}
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},
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{
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.bitpos = 20, .bitwidth = 4, .name = "TGran16",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No 16KB granule",
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[1] = "16KB granule"
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}
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},
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{
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.bitpos = 24, .bitwidth = 4, .name = "TGran64",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No 64KB granule",
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[15] = "64KB granule"
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}
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},
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{
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.bitpos = 28, .bitwidth = 4, .name = "TGran4",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "4KB granule",
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[15] = "No 4KB granule"
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}
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},
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{ .bitwidth = 0 } /* end of table */
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};
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/* MVFR0_EL1 - Media and VFP Feature Register 0 */
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struct fieldinfo mvfr0_fieldinfo[] = {
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{
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.bitpos = 0, .bitwidth = 4, .name = "SIMDreg",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No SIMD",
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[1] = "16x64-bit SIMD",
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[2] = "32x64-bit SIMD"
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}
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},
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{
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.bitpos = 4, .bitwidth = 4, .name = "FPSP",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No VFP support single precision",
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[1] = "VFPv2 support single precision",
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[2] = "VFPv2/VFPv3/VFPv4 support single precision"
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}
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},
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{
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.bitpos = 8, .bitwidth = 4, .name = "FPDP",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No VFP support double precision",
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[1] = "VFPv2 support double precision",
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[2] = "VFPv2/VFPv3/VFPv4 support double precision"
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}
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},
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{
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.bitpos = 12, .bitwidth = 4, .name = "FPTrap",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "VFPv2 support exception trapping",
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[1] = "VFPv2/VFPv3/VFPv4 support exception trapping"
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}
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},
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{
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.bitpos = 16, .bitwidth = 4, .name = "FPDivide",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "VDIV not supported",
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[1] = "VDIV supported"
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}
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},
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{
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.bitpos = 20, .bitwidth = 4, .name = "FPSqrt",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "VSQRT not supported",
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[1] = "VSQRT supported"
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}
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},
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{
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.bitpos = 24, .bitwidth = 4, .name = "FPShVec",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "Short Vectors not supported",
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[1] = "Short Vectors supported"
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}
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},
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{
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.bitpos = 28, .bitwidth = 4, .name = "FPRound",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "Only Round to Nearest mode",
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[1] = "All rounding modes"
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}
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},
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{ .bitwidth = 0 } /* end of table */
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};
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/* MVFR1_EL1 - Media and VFP Feature Register 1 */
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struct fieldinfo mvfr1_fieldinfo[] = {
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{
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.bitpos = 0, .bitwidth = 4, .name = "FPFtZ",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "only the Flush-to-Zero",
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[1] = "full Denormalized number arithmetic"
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}
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},
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{
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.bitpos = 4, .bitwidth = 4, .name = "FPDNan",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "Default NaN",
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[1] = "Propagation of NaN"
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}
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},
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{
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.bitpos = 8, .bitwidth = 4, .name = "SIMDLS",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No Advanced SIMD Load/Store",
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[1] = "Advanced SIMD Load/Store"
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}
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},
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{
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.bitpos = 12, .bitwidth = 4, .name = "SIMDInt",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No Advanced SIMD Integer",
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[1] = "Advanced SIMD Integer"
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}
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},
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{
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.bitpos = 16, .bitwidth = 4, .name = "SIMDSP",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No Advanced SIMD single precision",
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[1] = "Advanced SIMD single precision"
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}
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},
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{
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.bitpos = 20, .bitwidth = 4, .name = "SIMDHP",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No Advanced SIMD half precision",
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[1] = "Advanced SIMD half precision"
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}
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},
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{
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.bitpos = 24, .bitwidth = 4, .name = "FPHP",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No half precision conversion",
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[1] = "half/single precision conversion",
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[2] = "half/single/double precision conversion"
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}
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},
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{
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.bitpos = 28, .bitwidth = 4, .name = "SIMDFMAC",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No Fused Multiply-Accumulate",
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[1] = "Fused Multiply-Accumulate"
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}
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},
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{ .bitwidth = 0 } /* end of table */
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};
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/* MVFR2_EL1 - Media and VFP Feature Register 2 */
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struct fieldinfo mvfr2_fieldinfo[] = {
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{
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.bitpos = 0, .bitwidth = 4, .name = "SIMDMisc",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No miscellaneous features",
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[1] = "Conversion to Integer w/Directed Rounding modes",
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[2] = "Conversion to Integer w/Directed Rounding modes"
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", Round to Integral floating point",
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[3] = "Conversion to Integer w/Directed Rounding modes"
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", Round to Integral floating point"
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", MaxNum and MinNum"
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}
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},
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{
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.bitpos = 4, .bitwidth = 4, .name = "FPMisc",
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.info = (const char *[16]) { /* 16=4bit */
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[0] = "No miscellaneous features",
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[1] = "Floating point selection",
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[2] = "Floating point selection"
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", Conversion to Integer w/Directed Rounding modes",
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[3] = "Floating point selection"
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", Conversion to Integer w/Directed Rounding modes"
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", Round to Integral floating point",
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[4] = "Floating point selection"
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", Conversion to Integer w/Directed Rounding modes"
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", Round to Integral floating point"
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", MaxNum and MinNum"
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}
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},
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{ .bitwidth = 0 } /* end of table */
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};
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static void
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print_fieldinfo(const char *cpuname, const char *setname,
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struct fieldinfo *fieldinfo, uint64_t data)
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{
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uint64_t v;
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const char *info;
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int i;
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#define WIDTHMASK(w) (0xffffffffffffffffULL >> (64 - (w)))
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for (i = 0; fieldinfo[i].bitwidth != 0; i++) {
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v = (data >> fieldinfo[i].bitpos) &
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WIDTHMASK(fieldinfo[i].bitwidth);
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info = fieldinfo[i].info[v];
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if (info == NULL)
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printf("%s: %s: %s: 0x%"PRIx64"\n",
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cpuname, setname, fieldinfo[i].name, v);
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else
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printf("%s: %s: %s: %s\n",
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cpuname, setname, fieldinfo[i].name, info);
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}
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}
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|
||||
/* MIDR_EL1 - Main ID Register */
|
||||
static void
|
||||
identify_midr(const char *cpuname, uint32_t cpuid)
|
||||
{
|
||||
unsigned int i;
|
||||
uint32_t implid, cpupart, variant, revision;
|
||||
const char *implementer = NULL;
|
||||
static char implbuf[128];
|
||||
|
||||
implid = cpuid & CPU_ID_IMPLEMENTOR_MASK;
|
||||
cpupart = cpuid & CPU_PARTMASK;
|
||||
variant = __SHIFTOUT(cpuid, CPU_ID_VARIANT_MASK);
|
||||
revision = __SHIFTOUT(cpuid, CPU_ID_REVISION_MASK);
|
||||
|
||||
for (i = 0; i < __arraycount(implids); i++) {
|
||||
if (implid == implids[i].impl_id) {
|
||||
implementer = implids[i].impl_name;
|
||||
}
|
||||
}
|
||||
if (implementer == NULL) {
|
||||
snprintf(implbuf, sizeof(implbuf), "unknown implementer: 0x%02x",
|
||||
implid >> 24);
|
||||
implementer = implbuf;
|
||||
}
|
||||
|
||||
for (i = 0; i < __arraycount(cpuids); i++) {
|
||||
if (cpupart == cpuids[i].cpu_partnum) {
|
||||
printf("%s: %s, %s r%dp%d (%s %s core)\n",
|
||||
cpuname, implementer,
|
||||
cpuids[i].cpu_name, variant, revision,
|
||||
cpuids[i].cpu_class,
|
||||
cpuids[i].cpu_architecture);
|
||||
return;
|
||||
}
|
||||
}
|
||||
printf("%s: unknown CPU ID: 0x%08x\n", cpuname, cpuid);
|
||||
}
|
||||
|
||||
/* REVIDR_EL1 - Revision ID Register */
|
||||
static void
|
||||
identify_revidr(const char *cpuname, uint32_t revidr)
|
||||
{
|
||||
printf("%s: revision: 0x%08x\n", cpuname, revidr);
|
||||
}
|
||||
|
||||
/* MPIDR_EL1 - Multiprocessor Affinity Register */
|
||||
static void
|
||||
identify_mpidr(const char *cpuname, uint32_t mpidr)
|
||||
{
|
||||
const char *setname = "multiprocessor affinity";
|
||||
|
||||
printf("%s: %s: Affinity-Level: %"PRIu64"-%"PRIu64"-%"PRIu64"-%"PRIu64"\n",
|
||||
cpuname, setname,
|
||||
__SHIFTOUT(mpidr, MPIDR_AFF3),
|
||||
__SHIFTOUT(mpidr, MPIDR_AFF2),
|
||||
__SHIFTOUT(mpidr, MPIDR_AFF1),
|
||||
__SHIFTOUT(mpidr, MPIDR_AFF0));
|
||||
|
||||
if ((mpidr & MPIDR_U) == 0)
|
||||
printf("%s: %s: Multiprocessor system\n", cpuname, setname);
|
||||
else
|
||||
printf("%s: %s: Uniprocessor system\n", cpuname, setname);
|
||||
|
||||
if ((mpidr & MPIDR_MT) == 0)
|
||||
printf("%s: %s: Core Independent\n", cpuname, setname);
|
||||
else
|
||||
printf("%s: %s: Multi-Threading\n", cpuname, setname);
|
||||
|
||||
}
|
||||
|
||||
static void *
|
||||
sysctlfetch(const char *sname, size_t *lenp)
|
||||
{
|
||||
size_t len;
|
||||
void *data;
|
||||
|
||||
if (sysctlbyname(sname, NULL, &len, NULL, 0) != 0) {
|
||||
warn("sysctlbyname: %s", sname);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
data = malloc(len);
|
||||
if (data == NULL) {
|
||||
warn("malloc");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (sysctlbyname(sname, data, &len, NULL, 0) != 0) {
|
||||
warn("sysctlbyname: %s", sname);
|
||||
free(data);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
*lenp = len;
|
||||
return data;
|
||||
}
|
||||
|
||||
void
|
||||
identifycpu(int fd, const char *cpuname)
|
||||
{
|
||||
void *regs;
|
||||
size_t len;
|
||||
|
||||
/* MIDR_EL1 */
|
||||
regs = sysctlfetch("machdep.cpu_id", &len);
|
||||
if (regs != NULL) {
|
||||
if (len >= sizeof(uint32_t))
|
||||
identify_midr(cpuname, ((uint32_t *)regs)[0]);
|
||||
free(regs);
|
||||
}
|
||||
|
||||
/* REVIDR_EL1 */
|
||||
regs = sysctlfetch("machdep.id_revidr", &len);
|
||||
if (regs != NULL) {
|
||||
if (len >= sizeof(uint32_t))
|
||||
identify_revidr(cpuname, ((uint32_t *)regs)[0]);
|
||||
free(regs);
|
||||
}
|
||||
|
||||
/* MPIDR_EL1 */
|
||||
regs = sysctlfetch("machdep.id_mpidr", &len);
|
||||
if (regs != NULL) {
|
||||
if (len >= sizeof(uint64_t))
|
||||
identify_mpidr(cpuname, ((uint64_t *)regs)[0]);
|
||||
free(regs);
|
||||
}
|
||||
|
||||
/* ID_AA64ISAR0_EL1 */
|
||||
regs = sysctlfetch("machdep.id_aa64isar", &len);
|
||||
if (regs != NULL) {
|
||||
if (len >= sizeof(uint64_t))
|
||||
print_fieldinfo(cpuname, "isa features 0",
|
||||
id_aa64isar0_fieldinfo, ((uint64_t *)regs)[0]);
|
||||
free(regs);
|
||||
}
|
||||
|
||||
/* ID_AA64MMFR0_EL1 */
|
||||
regs = sysctlfetch("machdep.id_aa64mmfr", &len);
|
||||
if (regs != NULL) {
|
||||
if (len >= sizeof(uint64_t))
|
||||
print_fieldinfo(cpuname, "memory model 0",
|
||||
id_aa64mmfr0_fieldinfo, ((uint64_t *)regs)[0]);
|
||||
free(regs);
|
||||
}
|
||||
|
||||
/* ID_AA64PFR0_EL1 */
|
||||
regs = sysctlfetch("machdep.id_aa64pfr", &len);
|
||||
if (regs != NULL) {
|
||||
if (len >= sizeof(uint64_t))
|
||||
print_fieldinfo(cpuname, "processor feature 0",
|
||||
id_aa64pfr0_fieldinfo, ((uint64_t *)regs)[0]);
|
||||
free(regs);
|
||||
}
|
||||
|
||||
/* MVFR[012]_EL1 */
|
||||
regs = sysctlfetch("machdep.id_mvfr", &len);
|
||||
if (regs != NULL) {
|
||||
if (len >= sizeof(uint32_t))
|
||||
print_fieldinfo(cpuname, "media and VFP features 0",
|
||||
mvfr0_fieldinfo, ((uint32_t *)regs)[0]);
|
||||
if (len >= sizeof(uint32_t) * 2)
|
||||
print_fieldinfo(cpuname, "media and VFP features 1",
|
||||
mvfr1_fieldinfo, ((uint32_t *)regs)[1]);
|
||||
if (len >= sizeof(uint32_t) * 3)
|
||||
print_fieldinfo(cpuname, "media and VFP features 2",
|
||||
mvfr2_fieldinfo, ((uint32_t *)regs)[2]);
|
||||
free(regs);
|
||||
}
|
||||
}
|
||||
|
||||
bool
|
||||
identifycpu_bind(void)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
int
|
||||
ucodeupdate_check(int fd, struct cpu_ucode *uc)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue