- use RTK_IDR[0-5] registers to get MAC address on RTL8168C
- change sc_rev numbers to match quirk numbers used in Realtek's driver - tweak some register definitions Taken from Realtek's FreeBSD driver. Untested yet on 8168C, but no bad sideeffect on older chips.
This commit is contained in:
tsutsui
parent
b127908947
commit
2925cedf26
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: rtl8169.c,v 1.103 2008/04/29 14:16:57 tsutsui Exp $ */
|
||||
/* $NetBSD: rtl8169.c,v 1.104 2008/05/06 11:45:00 tsutsui Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997, 1998-2003
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.103 2008/04/29 14:16:57 tsutsui Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.104 2008/05/06 11:45:00 tsutsui Exp $");
|
||||
/* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -390,7 +390,7 @@ re_reset(struct rtk_softc *sc)
|
|||
|
||||
/*
|
||||
* NB: Realtek-supplied Linux driver does this only for
|
||||
* MCFG_METHOD_2, which corresponds to sc->sc_rev == 2.
|
||||
* MCFG_METHOD_2, which corresponds to sc->sc_rev == 3.
|
||||
*/
|
||||
if (1) /* XXX check softc flag for 8169s version */
|
||||
CSR_WRITE_1(sc, RTK_LDPS, 1);
|
||||
|
|
@ -570,53 +570,52 @@ re_attach(struct rtk_softc *sc)
|
|||
/* Reset the adapter. */
|
||||
re_reset(sc);
|
||||
|
||||
if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129)
|
||||
addr_len = RTK_EEADDR_LEN1;
|
||||
else
|
||||
addr_len = RTK_EEADDR_LEN0;
|
||||
|
||||
/*
|
||||
* Get station address from the EEPROM.
|
||||
*/
|
||||
for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
|
||||
val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len);
|
||||
eaddr[(i * 2) + 0] = val & 0xff;
|
||||
eaddr[(i * 2) + 1] = val >> 8;
|
||||
}
|
||||
|
||||
if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
|
||||
uint32_t hwrev;
|
||||
|
||||
/* Revision of 8169/8169S/8110s in bits 30..26, 23 */
|
||||
hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV;
|
||||
/* These rev numbers are taken from Realtek's driver */
|
||||
if ( hwrev == RTK_HWREV_8100E_SPIN2) {
|
||||
sc->sc_rev = 15;
|
||||
} else if (hwrev == RTK_HWREV_8100E) {
|
||||
sc->sc_rev = 14;
|
||||
} else if (hwrev == RTK_HWREV_8101E) {
|
||||
sc->sc_rev = 13;
|
||||
} else if (hwrev == RTK_HWREV_8168_SPIN2 ||
|
||||
hwrev == RTK_HWREV_8168_SPIN3) {
|
||||
sc->sc_rev = 12;
|
||||
} else if (hwrev == RTK_HWREV_8168_SPIN1) {
|
||||
sc->sc_rev = 11;
|
||||
} else if (hwrev == RTK_HWREV_8169_8110SC) {
|
||||
sc->sc_rev = 5;
|
||||
} else if (hwrev == RTK_HWREV_8169_8110SB) {
|
||||
sc->sc_rev = 4;
|
||||
} else if (hwrev == RTK_HWREV_8169S) {
|
||||
sc->sc_rev = 3;
|
||||
} else if (hwrev == RTK_HWREV_8110S) {
|
||||
sc->sc_rev = 2;
|
||||
} else if (hwrev == RTK_HWREV_8169) {
|
||||
switch (hwrev) {
|
||||
case RTK_HWREV_8169:
|
||||
/* XXX not in the Realtek driver */
|
||||
sc->sc_rev = 1;
|
||||
sc->sc_quirk |= RTKQ_8169NONS;
|
||||
} else {
|
||||
break;
|
||||
case RTK_HWREV_8169S:
|
||||
case RTK_HWREV_8110S:
|
||||
sc->sc_rev = 3;
|
||||
break;
|
||||
case RTK_HWREV_8169_8110SB:
|
||||
sc->sc_rev = 4;
|
||||
break;
|
||||
case RTK_HWREV_8169_8110SC:
|
||||
sc->sc_rev = 5;
|
||||
break;
|
||||
case RTK_HWREV_8101E:
|
||||
sc->sc_rev = 11;
|
||||
break;
|
||||
case RTK_HWREV_8168_SPIN1:
|
||||
sc->sc_rev = 21;
|
||||
break;
|
||||
case RTK_HWREV_8168_SPIN2:
|
||||
sc->sc_rev = 22;
|
||||
break;
|
||||
case RTK_HWREV_8168_SPIN3:
|
||||
sc->sc_rev = 23;
|
||||
break;
|
||||
case RTK_HWREV_8168C:
|
||||
sc->sc_rev = 24;
|
||||
break;
|
||||
case RTK_HWREV_8100E:
|
||||
case RTK_HWREV_8100E_SPIN2:
|
||||
/* XXX not in the Realtek driver */
|
||||
sc->sc_rev = 0;
|
||||
break;
|
||||
default:
|
||||
aprint_normal_dev(sc->sc_dev,
|
||||
"Unknown revision (0x%08x)\n", hwrev);
|
||||
/* assume the latest one */
|
||||
sc->sc_rev = 15;
|
||||
sc->sc_rev = 0;
|
||||
}
|
||||
|
||||
/* Set RX length mask */
|
||||
|
|
@ -628,6 +627,31 @@ re_attach(struct rtk_softc *sc)
|
|||
sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139;
|
||||
}
|
||||
|
||||
if (sc->sc_rev == 24) {
|
||||
/*
|
||||
* Get station address from ID registers.
|
||||
*/
|
||||
for (i = 0; i < ETHER_ADDR_LEN; i++)
|
||||
eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i);
|
||||
} else {
|
||||
/*
|
||||
* Get station address from the EEPROM.
|
||||
*/
|
||||
if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129)
|
||||
addr_len = RTK_EEADDR_LEN1;
|
||||
else
|
||||
addr_len = RTK_EEADDR_LEN0;
|
||||
|
||||
/*
|
||||
* Get station address from the EEPROM.
|
||||
*/
|
||||
for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
|
||||
val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len);
|
||||
eaddr[(i * 2) + 0] = val & 0xff;
|
||||
eaddr[(i * 2) + 1] = val >> 8;
|
||||
}
|
||||
}
|
||||
|
||||
aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
|
||||
ether_sprintf(eaddr));
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: rtl81x9reg.h,v 1.30 2008/04/05 18:26:39 tsutsui Exp $ */
|
||||
/* $NetBSD: rtl81x9reg.h,v 1.31 2008/05/06 11:45:00 tsutsui Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997, 1998
|
||||
|
|
@ -88,9 +88,6 @@
|
|||
/* 005F reserved */
|
||||
#define RTK_TXSTAT_ALL 0x0060 /* TX status of all descriptors */
|
||||
|
||||
#define RTK_CSIDR 0x0064
|
||||
#define RTK_CSIAR 0x0068
|
||||
|
||||
/* Direct PHY access registers only available on 8139 */
|
||||
#define RTK_BMCR 0x0062 /* PHY basic mode control */
|
||||
#define RTK_BMSR 0x0064 /* PHY basic mode status */
|
||||
|
|
@ -129,11 +126,13 @@
|
|||
#define RTK_GTXSTART 0x0038 /* 8 bits */
|
||||
#define RTK_TIMERINT_8169 0x0058 /* different offset than 8139 */
|
||||
#define RTK_PHYAR 0x0060
|
||||
#define RTK_TBICSR 0x0064
|
||||
#define RTK_TBI_ANAR 0x0068
|
||||
#define RTK_CSIDR 0x0064
|
||||
#define RTK_CSIAR 0x0068
|
||||
#define RTK_TBI_LPAR 0x006A
|
||||
#define RTK_GMEDIASTAT 0x006C /* 8 bits */
|
||||
#define RTK_EPHYAR 0x0080
|
||||
#define RTK_LDPS 0x0082 /* Link Down Power Saving */
|
||||
#define RTK_DBG_REG 0x00D1
|
||||
#define RTK_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */
|
||||
#define RTK_IM 0x00E2
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue