Blocking soft interrupts can be useful..
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.2 2000/03/21 01:05:54 soren Exp $ */
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/* $NetBSD: machdep.c,v 1.3 2000/03/21 02:27:50 soren Exp $ */
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/*
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* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
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@ -129,8 +129,6 @@ cobalt_hardware_intr(mask, pc, status, cause)
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static u_int32_t cycles;
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int s;
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cf.pc = pc;
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cf.sr = status;
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/* XXX Reverse hardlock and statclock? */
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@ -139,6 +137,9 @@ cobalt_hardware_intr(mask, pc, status, cause)
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cycles = mips3_cycle_count();
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mips3_write_compare(cycles + TICK_CYCLES);
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cf.pc = pc;
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cf.sr = status;
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s = splstatclock(); /* XXX redo interrupts XXX */
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statclock(&cf);
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splx(s); /* XXX redo interrupts XXX */
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@ -178,6 +179,10 @@ cobalt_hardware_intr(mask, pc, status, cause)
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if (*irq_src & 0x00000100) {
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*irq_src = 0;
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cf.pc = pc;
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cf.sr = status;
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s = splclock(); /* XXX redo interrupts XXX */
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hardclock(&cf);
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splx(s); /* XXX redo interrupts XXX */
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.h,v 1.1 2000/03/19 23:07:46 soren Exp $ */
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/* $NetBSD: intr.h,v 1.2 2000/03/21 02:27:50 soren Exp $ */
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#include <mips/cpuregs.h>
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@ -44,7 +44,8 @@ extern void _clrsoftintr(int);
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#define splhigh() _splraise(MIPS_INT_MASK)
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#define spl0() (void)_spllower(0)
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#define splx(s) (void)_splset(s)
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#define SPLBIO MIPS_INT_MASK_4
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#define SPLSOFT MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1
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#define SPLBIO SPLSOFT | MIPS_INT_MASK_4
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#define SPLNET SPLBIO | MIPS_INT_MASK_1 | MIPS_INT_MASK_2
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#define SPLTTY SPLNET | MIPS_INT_MASK_3
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#define SPLCLOCK SPLTTY | MIPS_INT_MASK_0 | MIPS_INT_MASK_5
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@ -1,4 +1,4 @@
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/* $NetBSD: pci_machdep.c,v 1.2 2000/03/21 01:05:53 soren Exp $ */
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/* $NetBSD: pci_machdep.c,v 1.3 2000/03/21 02:27:50 soren Exp $ */
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/*
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* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
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@ -175,10 +175,14 @@ pci_intr_establish(pc, ih, level, func, arg)
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* XXX XXX XXX
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*/
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if (ih == 4)
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if (ih == 4) {
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tlp0 = arg;
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if (ih == 13)
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return (void *)-1;
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}
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if (ih == 13) {
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tlp1 = arg;
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return (void *)-1;
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}
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return intr_establish(NULL, ih, IST_LEVEL, level, func, arg);
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}
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