ibss and hostap support from stsp @ openbsd.
This commit is contained in:
christos
parent
b99196035c
commit
28e311e50e
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@ -1,4 +1,4 @@
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/* $NetBSD: if_urtwn.c,v 1.25 2013/08/10 21:15:26 jnemeth Exp $ */
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/* $NetBSD: if_urtwn.c,v 1.26 2014/02/14 04:17:41 christos Exp $ */
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/* $OpenBSD: if_urtwn.c,v 1.20 2011/11/26 06:39:33 ckuethe Exp $ */
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/*-
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@ -22,7 +22,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.25 2013/08/10 21:15:26 jnemeth Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.26 2014/02/14 04:17:41 christos Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_inet.h"
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@ -246,6 +246,7 @@ static int urtwn_init(struct ifnet *);
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static void urtwn_stop(struct ifnet *, int);
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static int urtwn_reset(struct ifnet *);
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static void urtwn_chip_stop(struct urtwn_softc *);
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static void urtwn_newassoc(struct ieee80211_node *, int);
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/* Aliases. */
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#define urtwn_bb_write urtwn_write_4
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@ -352,6 +353,8 @@ urtwn_attach(device_t parent, device_t self, void *aux)
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/* Set device capabilities. */
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ic->ic_caps =
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IEEE80211_C_MONITOR | /* Monitor mode supported. */
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IEEE80211_C_IBSS | /* IBSS mode supported */
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IEEE80211_C_HOSTAP | /* HostAp mode supported */
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IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */
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IEEE80211_C_SHSLOT | /* Short slot time supported. */
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IEEE80211_C_WME | /* 802.11e */
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@ -383,6 +386,7 @@ urtwn_attach(device_t parent, device_t self, void *aux)
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ieee80211_ifattach(ic);
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/* override default methods */
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ic->ic_newassoc = urtwn_newassoc;
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ic->ic_reset = urtwn_reset;
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ic->ic_wme.wme_update = urtwn_wme_update;
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@ -1498,6 +1502,15 @@ urtwn_next_scan(void *arg)
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splx(s);
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}
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static void
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urtwn_newassoc(struct ieee80211_node *ni, int isnew)
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{
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DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__,
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ether_sprintf(ni->ni_macaddr)));
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/* start with lowest Tx rate */
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ni->ni_txrate = 0;
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}
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static int
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urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
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{
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@ -1527,7 +1540,7 @@ urtwn_newstate_cb(struct urtwn_softc *sc, void *arg)
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enum ieee80211_state ostate = ic->ic_state;
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enum ieee80211_state nstate = cmd->state;
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uint32_t reg;
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uint8_t sifs_time;
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uint8_t sifs_time, msr;
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int s;
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DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n",
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@ -1744,7 +1757,10 @@ urtwn_newstate_cb(struct urtwn_softc *sc, void *arg)
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/* Set beacon interval. */
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urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval);
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if (ic->ic_opmode == IEEE80211_M_STA) {
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msr = urtwn_read_1(sc, R92C_MSR);
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msr &= 0xfc;
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switch (ic->ic_opmode) {
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case IEEE80211_M_STA:
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/* Allow Rx from our BSSID only. */
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urtwn_write_4(sc, R92C_RCR,
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urtwn_read_4(sc, R92C_RCR) |
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@ -1752,7 +1768,28 @@ urtwn_newstate_cb(struct urtwn_softc *sc, void *arg)
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/* Enable TSF synchronization. */
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urtwn_tsf_sync_enable(sc);
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}
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/*FALLTHROUGH*/
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default:
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msr |= R92C_MSR_ADHOC;
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break;
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case IEEE80211_M_HOSTAP:
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urtwn_write_2(sc, R92C_BCNTCFG, 0x000f);
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/* Allow Rx from any BSSID. */
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urtwn_write_4(sc, R92C_RCR,
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urtwn_read_4(sc, R92C_RCR) &
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~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN));
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/* Reset TSF timer to zero. */
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reg = urtwn_read_4(sc, R92C_TCR);
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reg &= ~0x01;
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urtwn_write_4(sc, R92C_TCR, reg);
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reg |= 0x01;
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urtwn_write_4(sc, R92C_TCR, reg);
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msr |= R92C_MSR_AP;
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break;
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}
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urtwn_write_1(sc, R92C_MSR, msr);
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sifs_time = 10;
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urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time);
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@ -3732,8 +3769,8 @@ urtwn_init(struct ifnet *ifp)
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/* Initialize beacon parameters. */
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urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404);
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urtwn_write_1(sc, R92C_DRVERLYINT, 0x05);
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urtwn_write_1(sc, R92C_BCNDMATIM, 0x02);
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urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRIVER_EARLY_INT_TIME);
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urtwn_write_1(sc, R92C_BCNDMATIM, R92C_DMA_ATIME_INT_TIME);
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urtwn_write_2(sc, R92C_BCNTCFG, 0x660f);
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/* Setup AMPDU aggregation. */
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@ -1,4 +1,4 @@
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/* $NetBSD: if_urtwnreg.h,v 1.3 2013/01/28 23:46:33 christos Exp $ */
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/* $NetBSD: if_urtwnreg.h,v 1.4 2014/02/14 04:17:41 christos Exp $ */
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/* $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ */
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/*-
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@ -83,6 +83,7 @@
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#define R92C_SYS_CFG 0x0f0
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/* MAC General Configuration. */
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#define R92C_CR 0x100
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#define R92C_MSR 0x102
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#define R92C_PBP 0x104
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#define R92C_TRXDMA_CTRL 0x10c
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#define R92C_TRXFF_BNDY 0x114
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@ -384,6 +385,13 @@
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#define R92C_CR_NETTYPE_INFRA 2
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#define R92C_CR_NETTYPE_AP 3
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/* Bits for R92C_MSR. */
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#define R92C_MSR_NOLINK 0x00
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#define R92C_MSR_ADHOC 0x01
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#define R92C_MSR_INFRA 0x02
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#define R92C_MSR_AP 0x03
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/* Bits for R92C_PBP. */
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/* Bits for R92C_PBP. */
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#define R92C_PBP_PSRX_M 0x0f
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#define R92C_PBP_PSRX_S 0
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@ -483,6 +491,12 @@
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#define R92C_BCN_CTRL_EN_BCN 0x08
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#define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10
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/* Bits for R92C_DRVERLYINT */
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#define R92C_DRIVER_EARLY_INT_TIME 0x05
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/* Bits for R92C_BCNDMATIM */
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#define R92C_DMA_ATIME_INT_TIME 0x02
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/* Bits for R92C_APSD_CTRL. */
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#define R92C_APSD_CTRL_OFF 0x40
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#define R92C_APSD_CTRL_OFF_STATUS 0x80
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