From 28cbee6941917503f2c6f212a4c715aa84a5dc60 Mon Sep 17 00:00:00 2001 From: cgd Date: Wed, 28 Jun 1995 04:02:13 +0000 Subject: [PATCH] move to more appropriate (...reg.h) names. --- sys/dev/ic/cd1400.h | 123 ---------- sys/dev/ic/dp8390.h | 550 ------------------------------------------ sys/dev/ic/i8042.h | 44 ---- sys/dev/ic/i8237.h | 13 - sys/dev/ic/i82586.h | 289 ---------------------- sys/dev/ic/mb86960.h | 320 ------------------------ sys/dev/ic/mc146818.h | 194 --------------- sys/dev/ic/nec765.h | 73 ------ sys/dev/ic/ns16450.h | 51 ---- sys/dev/ic/ns16550.h | 53 ---- sys/dev/ic/z8530.h | 432 --------------------------------- 11 files changed, 2142 deletions(-) delete mode 100644 sys/dev/ic/cd1400.h delete mode 100644 sys/dev/ic/dp8390.h delete mode 100644 sys/dev/ic/i8042.h delete mode 100644 sys/dev/ic/i8237.h delete mode 100644 sys/dev/ic/i82586.h delete mode 100644 sys/dev/ic/mb86960.h delete mode 100644 sys/dev/ic/mc146818.h delete mode 100644 sys/dev/ic/nec765.h delete mode 100644 sys/dev/ic/ns16450.h delete mode 100644 sys/dev/ic/ns16550.h delete mode 100644 sys/dev/ic/z8530.h diff --git a/sys/dev/ic/cd1400.h b/sys/dev/ic/cd1400.h deleted file mode 100644 index d8498a9b3b88..000000000000 --- a/sys/dev/ic/cd1400.h +++ /dev/null @@ -1,123 +0,0 @@ -/* $NetBSD: cd1400.h,v 1.2 1994/10/27 04:18:37 cgd Exp $ */ - -/* - * cyclades cyclom-y serial driver - * Andrew Herbert , 17 August 1993 - * - * Copyright (c) 1993 Andrew Herbert. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name Andrew Herbert may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL I BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#define CD1400_NO_OF_CHANNELS 4 /* four serial channels per chip */ -#define CD1400_FIFOSIZE 12 /* 12 chars */ - -/* register definitions */ - -#define CD1400_CCR 2*0x05 /* channel control */ -#define CD1400_CMD_RESET 0x81 /* full reset */ - -#define CD1400_SRER 2*0x06 /* service request enable */ - -#define CD1400_GFRCR 2*0x40 /* global firmware revision code */ - -#define CD1400_LIVR 2*0x18 /* local intr vector */ -#define CD1400_MIVR 2*0x41 /* modem intr vector */ -#define CD1400_TIVR 2*0x42 /* transmit intr vector */ -#define CD1400_RIVR 2*0x43 /* receive intr vector */ -#define CD1400_RIVR_EXCEPTION (1<<2) /* receive exception bit */ - -#define CD1400_RICR 2*0x44 /* receive intr channel */ -#define CD1400_TICR 2*0x45 /* transmit intr channel */ -#define CD1400_MICR 2*0x46 /* modem intr channel */ - -#define CD1400_RDCR 2*0x0e /* rx data count */ - -#define CD1400_EOSRR 2*0x60 /* end of service request */ -#define CD1400_RDSR 2*0x62 /* rx data/status */ -#define CD1400_RDSR_OVERRUN (1<<0) /* rx overrun error */ -#define CD1400_RDSR_FRAMING (1<<1) /* rx framing error */ -#define CD1400_RDSR_PARITY (1<<2) /* rx parity error */ -#define CD1400_RDSR_BREAK (1<<3) /* rx break */ -#define CD1400_RDSR_SPECIAL (7<<4) /* rx special char */ -#define CD1400_RDSR_SPECIAL_SHIFT 4 /* rx special char shift */ -#define CD1400_RDSR_TIMEOUT (1<<7) /* rx timeout */ - -#define CD1400_TDR 2*0x63 /* tx data */ - -#define CD1400_MISR 2*0x4c /* modem intr status */ -#define CD1400_MISR_DSRd (1<<7) /* DSR delta */ -#define CD1400_MISR_CTSd (1<<6) /* CTS delta */ -#define CD1400_MISR_RId (1<<5) /* RI delta */ -#define CD1400_MISR_CDd (1<<4) /* CD delta */ - -#define CD1400_MSVR 2*0x6d /* modem signals */ -#define CD1400_MSVR_DSR (1<<7) /* !DSR line */ -#define CD1400_MSVR_CTS (1<<6) /* !CTS line */ -#define CD1400_MSVR_RI (1<<5) /* !RI line */ -#define CD1400_MSVR_CD (1<<4) /* !CD line */ -#define CD1400_MSVR_DTR (1<<1) /* DTR line */ - -#define CD1400_DTR 2*0x6d /* dtr control */ -#define CD1400_DTR_CLEAR 0 -#define CD1400_DTR_SET (1<<1) - -#define CD1400_PPR 2*0x7e -#define CD1400_CLOCK_25_1MS 0x31 - -#define CD1400_CAR 2*0x68 /* channel access */ - -#define CD1400_RIR 2*0x6B /* receive interrupt status */ -#define CD1400_TIR 2*0x6A /* transmit interrupt status */ -#define CD1400_MIR 2*0x69 /* modem interrupt status */ - -#define CD1400_RBPR 2*0x78 /* receive baud rate period */ -#define CD1400_RCOR 2*0x7C /* receive clock option */ -#define CD1400_TBPR 2*0x72 /* transmit baud rate period */ -#define CD1400_TCOR 2*0x76 /* transmit clock option */ - -#define CD1400_COR1 2*0x08 /* channel option 1 */ -#define CD1400_COR2 2*0x09 /* channel option 2 */ -#define CD1400_COR3 2*0x0A /* channel option 3 */ -#define CD1400_COR4 2*0x1E /* channel option 4 */ -#define CD1400_COR5 2*0x1F /* channel option 5 */ - -#define CD1400_SCHR1 2*0x1A /* special character 1 */ -#define CD1400_SCHR2 2*0x1B /* special character 2 */ -#define CD1400_SCHR3 2*0x1C /* special character 3 */ -#define CD1400_SCHR4 2*0x1D /* special character 4 */ - -#define CD1400_MCOR1 2*0x15 /* modem change 1 */ -#define CD1400_MCOR2 2*0x16 /* modem change 2 */ -#define CD1400_RTPR 2*0x21 /* receive timeout period */ - -#define CD1400_SVRR 2*0x67 /* service request */ -#define CD1400_SVRR_RX (1<<0) -#define CD1400_SVRR_TX (1<<1) -#define CD1400_SVRR_MDM (1<<2) - -/* hardware SVCACK addresses, for use in interrupt handlers */ -#define CD1400_SVCACKR 0x100 -#define CD1400_SVCACKT 0x200 -#define CD1400_SVCACKM 0x300 diff --git a/sys/dev/ic/dp8390.h b/sys/dev/ic/dp8390.h deleted file mode 100644 index 23c1ba7e1508..000000000000 --- a/sys/dev/ic/dp8390.h +++ /dev/null @@ -1,550 +0,0 @@ -/* $NetBSD: dp8390.h,v 1.2 1995/04/12 16:12:42 mycroft Exp $ */ - -/* - * National Semiconductor DS8390 NIC register definitions. - * - * Copyright (C) 1993, David Greenman. This software may be used, modified, - * copied, distributed, and sold, in both source and binary form provided that - * the above copyright and these terms are retained. Under no circumstances is - * the author responsible for the proper functioning of this software, nor does - * the author assume any responsibility for damages incurred with its use. - */ - -/* - * Page 0 register offsets - */ -#define ED_P0_CR 0x00 /* Command Register */ - -#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */ -#define ED_P0_PSTART 0x01 /* Page Start register (write) */ - -#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */ -#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */ - -#define ED_P0_BNRY 0x03 /* Boundary Pointer */ - -#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */ -#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */ - -#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */ -#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */ - -#define ED_P0_FIFO 0x06 /* FIFO register (read) */ -#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */ - -#define ED_P0_ISR 0x07 /* Interrupt Status Register */ - -#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */ -#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */ - -#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */ -#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */ - -#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */ - -#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */ - -#define ED_P0_RSR 0x0c /* Receive Status (read) */ -#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */ - -#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */ -#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */ - -#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */ -#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */ - -#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */ -#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */ - -/* - * Page 1 register offsets - */ -#define ED_P1_CR 0x00 /* Command Register */ -#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */ -#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */ -#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */ -#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */ -#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */ -#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */ -#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */ -#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */ -#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */ -#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */ -#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */ -#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */ -#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */ -#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */ -#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */ - -/* - * Page 2 register offsets - */ -#define ED_P2_CR 0x00 /* Command Register */ -#define ED_P2_PSTART 0x01 /* Page Start (read) */ -#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */ -#define ED_P2_PSTOP 0x02 /* Page Stop (read) */ -#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */ -#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */ -#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */ -#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */ -#define ED_P2_ACU 0x06 /* Address Counter Upper */ -#define ED_P2_ACL 0x07 /* Address Counter Lower */ -#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */ -#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */ -#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */ -#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */ - -/* - * Command Register (CR) definitions - */ - -/* - * STP: SToP. Software reset command. Takes the controller offline. No - * packets will be received or transmitted. Any reception or transmission in - * progress will continue to completion before entering reset state. To exit - * this state, the STP bit must reset and the STA bit must be set. The - * software reset has executed only when indicated by the RST bit in the ISR - * being set. - */ -#define ED_CR_STP 0x01 - -/* - * STA: STArt. This bit is used to activate the NIC after either power-up, or - * when the NIC has been put in reset mode by software command or error. - */ -#define ED_CR_STA 0x02 - -/* - * TXP: Transmit Packet. This bit must be set to indicate transmission of a - * packet. TXP is internally reset either after the transmission is completed - * or aborted. This bit should be set only after the Transmit Byte Count and - * Transmit Page Start register have been programmed. - */ -#define ED_CR_TXP 0x04 - -/* - * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation - * of the remote DMA channel. RD2 can be set to abort any remote DMA command - * in progress. The Remote Byte Count registers should be cleared when a - * remote DMA has been aborted. The Remote Start Addresses are not restored - * to the starting address if the remote DMA is aborted. - * - * RD2 RD1 RD0 function - * 0 0 0 not allowed - * 0 0 1 remote read - * 0 1 0 remote write - * 0 1 1 send packet - * 1 X X abort - */ -#define ED_CR_RD0 0x08 -#define ED_CR_RD1 0x10 -#define ED_CR_RD2 0x20 - -/* - * PS0, PS1: Page Select. The two bits select which register set or 'page' to - * access. - * - * PS1 PS0 page - * 0 0 0 - * 0 1 1 - * 1 0 2 - * 1 1 reserved - */ -#define ED_CR_PS0 0x40 -#define ED_CR_PS1 0x80 -/* bit encoded aliases */ -#define ED_CR_PAGE_0 0x00 /* (for consistency) */ -#define ED_CR_PAGE_1 0x40 -#define ED_CR_PAGE_2 0x80 - -/* - * Interrupt Status Register (ISR) definitions - */ - -/* - * PRX: Packet Received. Indicates packet received with no errors. - */ -#define ED_ISR_PRX 0x01 - -/* - * PTX: Packet Transmitted. Indicates packet transmitted with no errors. - */ -#define ED_ISR_PTX 0x02 - -/* - * RXE: Receive Error. Indicates that a packet was received with one or more - * the following errors: CRC error, frame alignment error, FIFO overrun, - * missed packet. - */ -#define ED_ISR_RXE 0x04 - -/* - * TXE: Transmission Error. Indicates that an attempt to transmit a packet - * resulted in one or more of the following errors: excessive collisions, FIFO - * underrun. - */ -#define ED_ISR_TXE 0x08 - -/* - * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network - * would exceed (has exceeded?) the boundary pointer, resulting in data that - * was previously received and not yet read from the buffer to be overwritten. - */ -#define ED_ISR_OVW 0x10 - -/* - * CNT: Counter Overflow. Set when the MSB of one or more of the Network Tally - * Counters has been set. - */ -#define ED_ISR_CNT 0x20 - -/* - * RDC: Remote Data Complete. Indicates that a Remote DMA operation has - * completed. - */ -#define ED_ISR_RDC 0x40 - -/* - * RST: Reset status. Set when the NIC enters the reset state and cleared when - * a Start Command is issued to the CR. This bit is also set when a receive - * ring-buffer overrun (OverWrite) occurs and is cleared when one or more - * packets have been removed from the ring. This is a read-only bit. - */ -#define ED_ISR_RST 0x80 - -/* - * Interrupt Mask Register (IMR) definitions - */ - -/* - * PRXE: Packet Received interrupt Enable. If set, a received packet will - * cause an interrupt. - */ -#define ED_IMR_PRXE 0x01 - -/* - * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated - * when a packet transmission completes. - */ -#define ED_IMR_PTXE 0x02 - -/* - * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur - * whenever a packet is received with an error. - */ -#define ED_IMR_RXEE 0x04 - -/* - * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur - * whenever a transmission results in an error. - */ -#define ED_IMR_TXEE 0x08 - -/* - * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated - * whenever the receive ring-buffer is overrun. i.e. when the boundary pointer - * is exceeded. - */ -#define ED_IMR_OVWE 0x10 - -/* - * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated - * whenever the MSB of one or more of the Network Statistics counters has been - * set. - */ -#define ED_IMR_CNTE 0x20 - -/* - * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is - * generated when a remote DMA transfer has completed. - */ -#define ED_IMR_RDCE 0x40 - -/* - * Bit 7 is unused/reserved. - */ - -/* - * Data Configuration Register (DCR) definitions - */ - -/* - * WTS: Word Transfer Select. WTS establishes byte or word transfers for both - * remote and local DMA transfers - */ -#define ED_DCR_WTS 0x01 - -/* - * BOS: Byte Order Select. BOS sets the byte order for the host. Should be 0 - * for 80x86, and 1 for 68000 series processors - */ -#define ED_DCR_BOS 0x02 - -/* - * LAS: Long Address Select. When LAS is 1, the contents of the remote DMA - * registers RSAR0 and RSAR1 are used to provide A16-A31. - */ -#define ED_DCR_LAS 0x04 - -/* - * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 of - * the TCR must also be programmed for loopback operation. When 1, normal - * operation is selected. - */ -#define ED_DCR_LS 0x08 - -/* - * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer - * under program control. When 1, remote DMA is automatically initiated and - * the boundary pointer is automatically updated. - */ -#define ED_DCR_AR 0x10 - -/* - * FT0, FT1: Fifo Threshold select. - * - * FT1 FT0 Word-width Byte-width - * 0 0 1 word 2 bytes - * 0 1 2 words 4 bytes - * 1 0 4 words 8 bytes - * 1 1 8 words 12 bytes - * - * During transmission, the FIFO threshold indicates the number of bytes or - * words that the FIFO has filled from the local DMA before BREQ is asserted. - * The transmission threshold is 16 bytes minus the receiver threshold. - */ -#define ED_DCR_FT0 0x20 -#define ED_DCR_FT1 0x40 - -/* - * bit 7 (0x80) is unused/reserved - */ - -/* - * Transmit Configuration Register (TCR) definitions - */ - -/* - * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC - * is not appended by the transmitter. - */ -#define ED_TCR_CRC 0x01 - -/* - * LB0, LB1: Loopback control. These two bits set the type of loopback that is - * to be performed. - * - * LB1 LB0 mode - * 0 0 0 - normal operation (DCR_LS = 0) - * 0 1 1 - internal loopback (DCR_LS = 0) - * 1 0 2 - external loopback (DCR_LS = 1) - * 1 1 3 - external loopback (DCR_LS = 0) - */ -#define ED_TCR_LB0 0x02 -#define ED_TCR_LB1 0x04 - -/* - * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows - * another station to disable the NIC's transmitter by transmitting to a - * multicast address hashing to bit 62. Reception of a multicast address - * hashing to bit 63 enables the transmitter. - */ -#define ED_TCR_ATD 0x08 - -/* - * OFST: Collision Offset enable. This bit when set modifies the backoff - * algorithm to allow prioritization of nodes. - */ -#define ED_TCR_OFST 0x10 - -/* - * bits 5, 6, and 7 are unused/reserved - */ - -/* - * Transmit Status Register (TSR) definitions - */ - -/* - * PTX: Packet Transmitted. Indicates successful transmission of packet. - */ -#define ED_TSR_PTX 0x01 - -/* - * bit 1 (0x02) is unused/reserved - */ - -/* - * COL: Transmit Collided. Indicates that the transmission collided at least - * once with another station on the network. - */ -#define ED_TSR_COL 0x04 - -/* - * ABT: Transmit aborted. Indicates that the transmission was aborted due to - * excessive collisions. - */ -#define ED_TSR_ABT 0x08 - -/* - * CRS: Carrier Sense Lost. Indicates that carrier was lost during the - * transmission of the packet. (Transmission is not aborted because of a loss - * of carrier). - */ -#define ED_TSR_CRS 0x10 - -/* - * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/ - * transmission memory before the FIFO emptied. Transmission of the packet was - * aborted. - */ -#define ED_TSR_FU 0x20 - -/* - * CDH: CD Heartbeat. Indicates that the collision detection circuitry isn't - * working correctly during a collision heartbeat test. - */ -#define ED_TSR_CDH 0x40 - -/* - * OWC: Out of Window Collision: Indicates that a collision occurred after a - * slot time (51.2us). The transmission is rescheduled just as in normal - * collisions. - */ -#define ED_TSR_OWC 0x80 - -/* - * Receiver Configuration Register (RCR) definitions - */ - -/* - * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1, - * packets with CRC and frame errors are not discarded. - */ -#define ED_RCR_SEP 0x01 - -/* - * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded. - * If set to 1, packets with less than 64 byte are not discarded. - */ -#define ED_RCR_AR 0x02 - -/* - * AB: Accept Broadcast. If set, packets sent to the broadcast address will be - * accepted. - */ -#define ED_RCR_AB 0x04 - -/* - * AM: Accept Multicast. If set, packets sent to a multicast address are - * checked for a match in the hashing array. If clear, multicast packets are - * ignored. - */ -#define ED_RCR_AM 0x08 - -/* - * PRO: Promiscuous Physical. If set, all packets with a physical addresses - * are accepted. If clear, a physical destination address must match this - * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM must - * also be set. In addition, the multicast hashing array must be set to all - * 1's so that all multicast addresses are accepted. - */ -#define ED_RCR_PRO 0x10 - -/* - * MON: Monitor Mode. If set, packets will be checked for good CRC and - * framing, but are not stored in the ring-buffer. If clear, packets are - * stored (normal operation). - */ -#define ED_RCR_MON 0x20 - -/* - * Bits 6 and 7 are unused/reserved. - */ - -/* - * Receiver Status Register (RSR) definitions - */ - -/* - * PRX: Packet Received without error. - */ -#define ED_RSR_PRX 0x01 - -/* - * CRC: CRC error. Indicates that a packet has a CRC error. Also set for - * frame alignment errors. - */ -#define ED_RSR_CRC 0x02 - -/* - * FAE: Frame Alignment Error. Indicates that the incoming packet did not end - * on a byte boundary and the CRC did not match at the last byte boundary. - */ -#define ED_RSR_FAE 0x04 - -/* - * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local - * DMA) causing it to overrun. Reception of the packet is aborted. - */ -#define ED_RSR_FO 0x08 - -/* - * MPA: Missed Packet. Indicates that the received packet couldn't be stored - * in the ring-buffer because of insufficient buffer space (exceeding the - * boundary pointer), or because the transfer to the ring-buffer was inhibited - * by RCR_MON - monitor mode. - */ -#define ED_RSR_MPA 0x10 - -/* - * PHY: Physical address. If 0, the packet received was sent to a physical - * address. If 1, the packet was accepted because of a multicast/broadcast - * address match. - */ -#define ED_RSR_PHY 0x20 - -/* - * DIS: Receiver Disabled. Set to indicate that the receiver has enetered - * monitor mode. Cleared when the receiver exits monitor mode. - */ -#define ED_RSR_DIS 0x40 - -/* - * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL - * inputs are active, and the transceiver has set the CD line as a result of - * the jabber. - */ -#define ED_RSR_DFR 0x80 - -/* - * receive ring discriptor - * - * The National Semiconductor DS8390 Network interface controller uses the - * following receive ring headers. The way this works is that the memory on - * the interface card is chopped up into 256 bytes blocks. A contiguous - * portion of those blocks are marked for receive packets by setting start and - * end block #'s in the NIC. For each packet that is put into the receive - * ring, one of these headers (4 bytes each) is tacked onto the front. The - * first byte is a copy of the receiver status register at the time the packet - * was received. - */ -struct ed_ring { -#if BYTE_ORDER == BIG_ENDIAN - u_char next_packet; /* pointer to next packet */ - u_char rsr; /* receiver status */ -#else - u_char rsr; /* receiver status */ - u_char next_packet; /* pointer to next packet */ -#endif - u_short count; /* bytes in packet (length + 4) */ -}; - -/* - * Common constants - */ -#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */ -#define ED_PAGE_MASK 255 -#define ED_PAGE_SHIFT 8 - -#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */ diff --git a/sys/dev/ic/i8042.h b/sys/dev/ic/i8042.h deleted file mode 100644 index 65637a225c61..000000000000 --- a/sys/dev/ic/i8042.h +++ /dev/null @@ -1,44 +0,0 @@ -/* $NetBSD: i8042.h,v 1.6 1995/04/21 09:16:16 mycroft Exp $ */ - -#define KBSTATP 0x64 /* kbd controller status port (I) */ -#define KBS_DIB 0x01 /* kbd data in buffer */ -#define KBS_IBF 0x02 /* kbd input buffer low */ -#define KBS_WARM 0x04 /* kbd input buffer low */ -#define KBS_OCMD 0x08 /* kbd output buffer has command */ -#define KBS_NOSEC 0x10 /* kbd security lock not engaged */ -#define KBS_TERR 0x20 /* kbd transmission error */ -#define KBS_RERR 0x40 /* kbd receive error */ -#define KBS_PERR 0x80 /* kbd parity error */ - -#define KBCMDP 0x64 /* kbd controller port (O) */ -#define KBC_RAMREAD 0x20 /* read from RAM */ -#define KBC_RAMWRITE 0x60 /* write to RAM */ -#define KBC_AUXDISABLE 0xa7 /* disable auxiliary port */ -#define KBC_AUXENABLE 0xa8 /* enable auxiliary port */ -#define KBC_AUXTEST 0xa9 /* test auxiliary port */ -#define KBC_KBDECHO 0xd2 /* echo to keyboard port */ -#define KBC_AUXECHO 0xd3 /* echo to auxiliary port */ -#define KBC_AUXWRITE 0xd4 /* write to auxiliary port */ -#define KBC_SELFTEST 0xaa /* start self-test */ -#define KBC_KBDTEST 0xab /* test keyboard port */ -#define KBC_KBDDISABLE 0xad /* disable keyboard port */ -#define KBC_KBDENABLE 0xae /* enable keyboard port */ -#define KBC_PULSE0 0xfe /* pulse output bit 0 */ -#define KBC_PULSE1 0xfd /* pulse output bit 1 */ -#define KBC_PULSE2 0xfb /* pulse output bit 2 */ -#define KBC_PULSE3 0xf7 /* pulse output bit 3 */ - -#define KBDATAP 0x60 /* kbd data port (I) */ -#define KBOUTP 0x60 /* kbd data port (O) */ - -#define K_RDCMDBYTE 0x20 -#define K_LDCMDBYTE 0x60 - -#define KC8_TRANS 0x40 /* convert to old scan codes */ -#define KC8_MDISABLE 0x20 /* disable mouse */ -#define KC8_KDISABLE 0x10 /* disable keyboard */ -#define KC8_IGNSEC 0x08 /* ignore security lock */ -#define KC8_CPU 0x04 /* exit from protected mode reset */ -#define KC8_MENABLE 0x02 /* enable mouse interrupt */ -#define KC8_KENABLE 0x01 /* enable keyboard interrupt */ -#define CMDBYTE (KC8_TRANS|KC8_CPU|KC8_MENABLE|KC8_KENABLE) diff --git a/sys/dev/ic/i8237.h b/sys/dev/ic/i8237.h deleted file mode 100644 index 4a59f99892e4..000000000000 --- a/sys/dev/ic/i8237.h +++ /dev/null @@ -1,13 +0,0 @@ -/* $NetBSD: i8237.h,v 1.4 1994/10/27 04:18:39 cgd Exp $ */ - -/* - * Intel 8237 DMA Controller - */ - -#define DMA37MD_SINGLE 0x40 /* single pass mode */ -#define DMA37MD_CASCADE 0xc0 /* cascade mode */ -#define DMA37MD_WRITE 0x04 /* read the device, write memory operation */ -#define DMA37MD_READ 0x08 /* write the device, read memory operation */ - -#define DMA37SM_CLEAR 0x00 /* clear mask bit */ -#define DMA37SM_SET 0x04 /* set mask bit */ diff --git a/sys/dev/ic/i82586.h b/sys/dev/ic/i82586.h deleted file mode 100644 index 7af3e6556854..000000000000 --- a/sys/dev/ic/i82586.h +++ /dev/null @@ -1,289 +0,0 @@ -/* $NetBSD: i82586.h,v 1.5 1995/04/04 01:59:34 mycroft Exp $ */ - -/*- - * Copyright (c) 1992, University of Vermont and State Agricultural College. - * Copyright (c) 1992, Garrett A. Wollman. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * Vermont and State Agricultural College and Garrett A. Wollman. - * 4. Neither the name of the University nor the name of the author - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OR AUTHOR BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * Intel 82586 Ethernet chip - * Register, bit, and structure definitions. - * - * Written by GAW with reference to the Clarkson Packet Driver code for this - * chip written by Russ Nelson and others. - */ - -struct ie_en_addr { - u_char data[6]; -}; - -/* - * This is the master configuration block. It tells the hardware where all - * the rest of the stuff is. - */ -struct ie_sys_conf_ptr { - u_short mbz; /* must be zero */ - u_char ie_bus_use; /* true if 8-bit only */ - u_char mbz2[5]; /* must be zero */ - caddr_t ie_iscp_ptr; /* 24-bit physaddr of ISCP */ -}; - -/* - * Note that this is wired in hardware; the SCP is always located here, no - * matter what. - */ -#define IE_SCP_ADDR 0xfffff4 - -/* - * The tells the hardware where all the rest of the stuff is, too. - * FIXME: some of these should be re-commented after we figure out their - * REAL function. - */ -struct ie_int_sys_conf_ptr { - u_char ie_busy; /* zeroed after init */ - u_char mbz; - u_short ie_scb_offset; /* 16-bit physaddr of next struct */ - caddr_t ie_base; /* 24-bit physaddr for all 16-bit vars */ -}; - -/* - * This FINALLY tells the hardware what to do and where to put it. - */ -struct ie_sys_ctl_block { - u_short ie_status; /* status word */ - u_short ie_command; /* command word */ - u_short ie_command_list; /* 16-pointer to command block list */ - u_short ie_recv_list; /* 16-pointer to receive frame list */ - u_short ie_err_crc; /* CRC errors */ - u_short ie_err_align; /* Alignment errors */ - u_short ie_err_resource; /* Resource errors */ - u_short ie_err_overrun; /* Overrun errors */ -}; - -/* Command values */ -#define IE_RU_COMMAND 0x0070 /* mask for RU command */ -#define IE_RU_NOP 0 /* for completeness */ -#define IE_RU_START 0x0010 /* start receive unit command */ -#define IE_RU_ENABLE 0x0020 /* enable receiver command */ -#define IE_RU_DISABLE 0x0030 /* disable receiver command */ -#define IE_RU_ABORT 0x0040 /* abort current receive operation */ - -#define IE_CU_COMMAND 0x0700 /* mask for CU command */ -#define IE_CU_NOP 0 /* included for completeness */ -#define IE_CU_START 0x0100 /* do-command command */ -#define IE_CU_RESUME 0x0200 /* resume a suspended cmd list */ -#define IE_CU_STOP 0x0300 /* SUSPEND was already taken */ -#define IE_CU_ABORT 0x0400 /* abort current command */ - -#define IE_ACK_COMMAND 0xf000 /* mask for ACK command */ -#define IE_ACK_CX 0x8000 /* ack IE_ST_CX */ -#define IE_ACK_FR 0x4000 /* ack IE_ST_FR */ -#define IE_ACK_CNA 0x2000 /* ack IE_ST_CNA */ -#define IE_ACK_RNR 0x1000 /* ack IE_ST_RNR */ - -#define IE_ACTION_COMMAND(x) (((x) & IE_CU_COMMAND) == IE_CU_START) - /* is this command an action command? */ - -/* Status values */ -#define IE_ST_WHENCE 0xf000 /* mask for cause of interrupt */ -#define IE_ST_CX 0x8000 /* command with I bit completed */ -#define IE_ST_FR 0x4000 /* frame received */ -#define IE_ST_CNA 0x2000 /* all commands completed */ -#define IE_ST_RNR 0x1000 /* receive not ready */ - -#define IE_CU_STATUS 0x700 /* mask for command unit status */ -#define IE_CU_ACTIVE 0x200 /* command unit is active */ -#define IE_CU_SUSPEND 0x100 /* command unit is suspended */ - -#define IE_RU_STATUS 0x70 /* mask for receiver unit status */ -#define IE_RU_SUSPEND 0x10 /* receiver is suspended */ -#define IE_RU_NOSPACE 0x20 /* receiver has no resources */ -#define IE_RU_READY 0x40 /* reveiver is ready */ - -/* - * This is filled in partially by the chip, partially by us. - */ -struct ie_recv_frame_desc { - u_short ie_fd_status; /* status for this frame */ - u_short ie_fd_last; /* end of frame list flag */ - u_short ie_fd_next; /* 16-pointer to next RFD */ - u_short ie_fd_buf_desc; /* 16-pointer to list of buffer desc's */ - struct ie_en_addr dest; /* destination ether */ - struct ie_en_addr src; /* source ether */ - u_short ie_length; /* 802 length/Ether type */ - u_short mbz; /* must be zero */ -}; - -#define IE_FD_LAST 0x8000 /* last rfd in list */ -#define IE_FD_SUSP 0x4000 /* suspend RU after receipt */ - -#define IE_FD_COMPLETE 0x8000 /* frame is complete */ -#define IE_FD_BUSY 0x4000 /* frame is busy */ -#define IE_FD_OK 0x2000 /* frame is bad */ -#define IE_FD_RNR 0x0200 /* receiver out of resources here */ - -/* - * linked list of buffers... - */ -struct ie_recv_buf_desc { - u_short ie_rbd_actual; /* status for this buffer */ - u_short ie_rbd_next; /* 16-pointer to next RBD */ - caddr_t ie_rbd_buffer; /* 24-pointer to buffer for this RBD */ - u_short ie_rbd_length; /* length of the buffer */ - u_short mbz; /* must be zero */ -}; - -#define IE_RBD_LAST 0x8000 /* last buffer */ -#define IE_RBD_USED 0x4000 /* this buffer has data */ -/* - * All commands share this in common. - */ -struct ie_cmd_common { - u_short ie_cmd_status; /* status of this command */ - u_short ie_cmd_cmd; /* command word */ - u_short ie_cmd_link; /* link to next command */ -}; - -#define IE_STAT_COMPL 0x8000 /* command is completed */ -#define IE_STAT_BUSY 0x4000 /* command is running now */ -#define IE_STAT_OK 0x2000 /* command completed successfully */ -#define IE_STAT_ABORT 0x1000 /* command was aborted */ - -#define IE_CMD_NOP 0x0000 /* NOP */ -#define IE_CMD_IASETUP 0x0001 /* initial address setup */ -#define IE_CMD_CONFIG 0x0002 /* configure command */ -#define IE_CMD_MCAST 0x0003 /* multicast setup command */ -#define IE_CMD_XMIT 0x0004 /* transmit command */ -#define IE_CMD_TDR 0x0005 /* time-domain reflectometer command */ -#define IE_CMD_DUMP 0x0006 /* dump command */ -#define IE_CMD_DIAGNOSE 0x0007 /* diagnostics command */ - -#define IE_CMD_LAST 0x8000 /* this is the last command in the list */ -#define IE_CMD_SUSPEND 0x4000 /* suspend CU after this command */ -#define IE_CMD_INTR 0x2000 /* post an interrupt after completion */ - -/* - * This is the command to transmit a frame. - */ -struct ie_xmit_cmd { - struct ie_cmd_common com; /* common part */ -#define ie_xmit_status com.ie_cmd_status - - u_short ie_xmit_desc; /* 16-pointer to buffer descriptor */ - struct ie_en_addr ie_xmit_addr; /* destination address */ - - u_short ie_xmit_length; /* 802.3 length/Ether type field */ -}; - -#define IE_XS_MAXCOLL 0x000f /* number of collisions during transmit */ -#define IE_XS_EXCMAX 0x0020 /* exceeded maximum number of collisions */ -#define IE_XS_SQE 0x0040 /* SQE positive */ -#define IE_XS_DEFERRED 0x0080 /* transmission deferred */ -#define IE_XS_UNDERRUN 0x0100 /* DMA underrun */ -#define IE_XS_LOSTCTS 0x0200 /* Lost CTS */ -#define IE_XS_NOCARRIER 0x0400 /* No Carrier */ -#define IE_XS_LATECOLL 0x0800 /* Late collision */ - -/* - * This is a buffer descriptor for a frame to be transmitted. - */ - -struct ie_xmit_buf { - u_short ie_xmit_flags; /* see below */ - u_short ie_xmit_next; /* 16-pointer to next desc. */ - caddr_t ie_xmit_buf; /* 24-pointer to the actual buffer */ -}; - -#define IE_XMIT_LAST 0x8000 /* this TBD is the last one */ -/* The rest of the `flags' word is actually the length. */ - -/* - * Multicast setup command. - */ - -#define MAXMCAST 250 /* must fit in transmit buffer */ - -struct ie_mcast_cmd { - struct ie_cmd_common com; /* common part */ -#define ie_mcast_status com.ie_cmd_status - - u_short ie_mcast_bytes; /* size (in bytes) of multicast addresses */ - struct ie_en_addr ie_mcast_addrs[MAXMCAST + 1]; /* space for them */ -}; - -/* - * Time Domain Reflectometer command. - */ - -struct ie_tdr_cmd { - struct ie_cmd_common com; /* common part */ -#define ie_tdr_status com.ie_cmd_status - - u_short ie_tdr_time; /* error bits and time */ -}; - -#define IE_TDR_SUCCESS 0x8000 /* TDR succeeded without error */ -#define IE_TDR_XCVR 0x4000 /* detected a transceiver problem */ -#define IE_TDR_OPEN 0x2000 /* detected an open */ -#define IE_TDR_SHORT 0x1000 /* TDR detected a short */ -#define IE_TDR_TIME 0x07ff /* mask for reflection time */ - -/* - * Initial Address Setup command - */ -struct ie_iasetup_cmd { - struct ie_cmd_common com; -#define ie_iasetup_status com.ie_cmd_status - - struct ie_en_addr ie_address; -}; - -/* - * Configuration command - */ -struct ie_config_cmd { - struct ie_cmd_common com; /* common part */ -#define ie_config_status com.ie_cmd_status - - u_char ie_config_count; /* byte count (0x0c) */ - u_char ie_fifo; /* fifo (8) */ - u_char ie_save_bad; /* save bad frames (0x40) */ - u_char ie_addr_len; /* address length (0x2e) (AL-LOC == 1) */ - u_char ie_priority; /* priority and backoff (0x0) */ - u_char ie_ifs; /* inter-frame spacing (0x60) */ - u_char ie_slot_low; /* slot time, LSB (0x0) */ - u_char ie_slot_high; /* slot time, MSN, and retries (0xf2) */ - u_char ie_promisc; /* 1 if promiscuous, else 0 */ - u_char ie_crs_cdt; /* CSMA/CD parameters (0x0) */ - u_char ie_min_len; /* min frame length (0x40) */ - u_char ie_junk; /* stuff for 82596 (0xff) */ -}; diff --git a/sys/dev/ic/mb86960.h b/sys/dev/ic/mb86960.h deleted file mode 100644 index ebbb0ea70aa2..000000000000 --- a/sys/dev/ic/mb86960.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * All Rights Reserved, Copyright (C) Fujitsu Limited 1995 - * - * This software may be used, modified, copied, distributed, and sold, in - * both source and binary form provided that the above copyright, these - * terms and the following disclaimer are retained. The name of the author - * and/or the contributor may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND THE CONTRIBUTOR ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR THE CONTRIBUTOR BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#define FE_MB86960_H_VERSION "mb86960.h ver. 0.8" - -/* - * Registers of Fujitsu MB86960A/MB86965A Ethernet controller. - * Written and contributed by M.S. - */ - -/* - * Notes on register naming: - * - * Fujitsu documents for MB86960A/MB86965A uses no mnemorable names - * for their registers. They defined only three names for 32 - * registers and appended numbers to distinguish registers of - * same name. Surprisingly, the numbers represent I/O address - * offsets of the registers from the base addresses, and their - * names correspond to the "bank" the registers are allocated. - * All this means that, for example, to say "read DLCR8" has no more - * than to say "read a register at offset 8 on bank DLCR." - * - * The following definitions may look silly, but that's what Fujitsu - * did, and it is necessary to know these names to read Fujitsu - * documents.. - */ - -/* Data Link Control Registrs, on invaliant port addresses. */ -#define FE_DLCR0 0 -#define FE_DLCR1 1 -#define FE_DLCR2 2 -#define FE_DLCR3 3 -#define FE_DLCR4 4 -#define FE_DLCR5 5 -#define FE_DLCR6 6 -#define FE_DLCR7 7 - -/* More DLCRs, on register bank #0. */ -#define FE_DLCR8 8 -#define FE_DLCR9 9 -#define FE_DLCR10 10 -#define FE_DLCR11 11 -#define FE_DLCR12 12 -#define FE_DLCR13 13 -#define FE_DLCR14 14 -#define FE_DLCR15 15 - -/* Malticast Address Registers. On register bank #1. */ -#define FE_MAR8 8 -#define FE_MAR9 9 -#define FE_MAR10 10 -#define FE_MAR11 11 -#define FE_MAR12 12 -#define FE_MAR13 13 -#define FE_MAR14 14 -#define FE_MAR15 15 - -/* Buffer Memory Port Registers. On register back #2. */ -#define FE_BMPR8 8 -#define FE_BMPR9 9 -#define FE_BMPR10 10 -#define FE_BMPR11 11 -#define FE_BMPR12 12 -#define FE_BMPR13 13 -#define FE_BMPR14 14 -#define FE_BMPR15 15 - -/* More BMPRs, only on MB86965A, accessible only when JLI mode. */ -#define FE_BMPR16 16 -#define FE_BMPR17 17 -#define FE_BMPR18 18 -#define FE_BMPR19 19 - -#define FE_RESET 31 - -/* - * Definitions of registers. - * I don't have Fujitsu documents of MB86960A/MB86965A, so I don't - * know the official names for each flags and fields. The following - * names are assigned by me (the author of this file,) since I cannot - * mnemorize hexadecimal constants for all of these functions. - * Comments? FIXME. - */ - -/* DLCR0 -- transmitter status */ -#define FE_D0_BUSERR 0x01 /* Bus write error */ -#define FE_D0_COLL16 0x02 /* Collision limit (16) encountered */ -#define FE_D0_COLLID 0x04 /* Collision on last transmission */ -#define FE_D0_JABBER 0x08 /* Jabber */ -#define FE_D0_CRLOST 0x10 /* Carrier lost on last transmission */ -#define FE_D0_PKTRCD 0x20 /* No corrision on last transmission */ -#define FE_D0_NETBSY 0x40 /* Network Busy (Carrier Detected) */ -#define FE_D0_TXDONE 0x80 /* Transmission complete */ - -/* DLCR1 -- receiver status */ -#define FE_D1_OVRFLO 0x01 /* Receiver buffer overflow */ -#define FE_D1_CRCERR 0x02 /* CRC error on last packet */ -#define FE_D1_ALGERR 0x04 /* Alignment error on last packet */ -#define FE_D1_SRTPKT 0x08 /* Short (RUNT) packet is received */ -#define FE_D1_RMTRST 0x10 /* Remote reset packet (type = 0x0900) */ -#define FE_D1_DMAEOP 0x20 /* Host asserted End of DMA OPeration */ -#define FE_D1_BUSERR 0x40 /* Bus read error */ -#define FE_D1_PKTRDY 0x80 /* Packet(s) ready on receive buffer */ - -#define FE_D1_ERRBITS "\20\4SRTPKT\3ALGERR\2CRCERR\1OVRFLO" - -/* DLCR2 -- transmitter interrupt control; same layout as DLCR0 */ -#define FE_D2_BUSERR FE_D0_BUSERR -#define FE_D2_COLL16 FE_D0_COLL16 -#define FE_D2_COLLID FE_D0_COLLID -#define FE_D2_JABBER FE_D0_JABBER -#define FE_D2_TXDONE FE_D0_TXDONE - -#define FE_D2_RESERVED 0x70 - -/* DLCR3 -- receiver interrupt control; same layout as DLCR1 */ -#define FE_D3_OVRFLO FE_D1_OVRFLO -#define FE_D3_CRCERR FE_D1_CRCERR -#define FE_D3_ALGERR FE_D1_ALGERR -#define FE_D3_SRTPKT FE_D1_SRTPKT -#define FE_D3_RMTRST FE_D1_RMTRST -#define FE_D3_DMAEOP FE_D1_DMAEOP -#define FE_D3_BUSERR FE_D1_BUSERR -#define FE_D3_PKTRDY FE_D1_PKTRDY - -/* DLCR4 -- transmitter operation mode */ -#define FE_D4_DSC 0x01 /* Disable carrier sense on trans. */ -#define FE_D4_LBC 0x02 /* Loop back test control */ -#define FE_D4_CNTRL 0x04 /* - ??? */ -#define FE_D4_TEST1 0x08 /* Test output #1 */ -#define FE_D4_COL 0xF0 /* Collision counter */ - -#define FE_D4_LBC_ENABLE 0x00 /* Perform loop back test */ -#define FE_D4_LBC_DISABLE 0x02 /* Normal operation */ - -#define FE_D4_COL_SHIFT 4 - -/* DLCR5 -- receiver operation mode */ -#define FE_D5_AFM0 0x01 /* Receive packets for other stations */ -#define FE_D5_AFM1 0x02 /* Receive packets for this station */ -#define FE_D5_RMTRST 0x04 /* Enable remote reset operation */ -#define FE_D5_SRTPKT 0x08 /* Accept short (RUNT) packets */ -#define FE_D5_SRTADR 0x10 /* Short (16 bits?) MAC address */ -#define FE_D5_BADPKT 0x20 /* Accept packets with error */ -#define FE_D5_BUFEMP 0x40 /* Receive buffer is empty */ -#define FE_D5_TEST2 0x80 /* Test output #2 */ - -/* DLCR6 -- hardware configuration #0 */ -#define FE_D6_BUFSIZ 0x03 /* Size of NIC buffer SRAM */ -#define FE_D6_TXBSIZ 0x0C /* Size (and config)of trans. buffer */ -#define FE_D6_BBW 0x10 /* Buffer SRAM bus width */ -#define FE_D6_SBW 0x20 /* System bus width */ -#define FE_D6_SRAM 0x40 /* Buffer SRAM access time */ -#define FE_D6_DLC 0x80 /* Disable DLC (recever/transmitter) */ - -#define FE_D6_BUFSIZ_8KB 0x00 /* The board has 8KB SRAM */ -#define FE_D6_BUFSIZ_16KB 0x01 /* The board has 16KB SRAM */ -#define FE_D6_BUFSIZ_32KB 0x02 /* The board has 32KB SRAM */ -#define FE_D6_BUFSIZ_64KB 0x03 /* The board has 64KB SRAM */ - -#define FE_D6_TXBSIZ_1x2KB 0x00 /* Single 2KB buffer for trans. */ -#define FE_D6_TXBSIZ_2x2KB 0x04 /* Double 2KB buffers */ -#define FE_D6_TXBSIZ_2x4KB 0x08 /* Double 4KB buffers */ -#define FE_D6_TXBSIZ_2x8KB 0x0C /* Double 8KB buffers */ - -#define FE_D6_BBW_WORD 0x00 /* SRAM has 16 bit data line */ -#define FE_D6_BBW_BYTE 0x10 /* SRAM has 8 bit data line */ - -#define FE_D6_SBW_WORD 0x00 /* Access with 16 bit (AT) bus */ -#define FE_D6_SBW_BYTE 0x20 /* Access with 8 bit (XT) bus */ - -#define FE_D6_SRAM_150ns 0x00 /* The board has slow SRAM */ -#define FE_D6_SRAM_100ns 0x40 /* The board has fast SRAM */ - -#define FE_D6_DLC_ENABLE 0x00 /* Normal operation */ -#define FE_D6_DLC_DISABLE 0x80 /* Stop sending/receiving */ - -/* DLC7 -- hardware configuration #1 */ -#define FE_D7_BYTSWP 0x01 /* Host byte order control */ -#define FE_D7_EOPPOL 0x02 /* Polarity of DMA EOP signal */ -#define FE_D7_RBS 0x0C /* Register bank select */ -#define FE_D7_RDYPNS 0x10 /* Senses RDYPNSEL input signal */ -#define FE_D7_POWER 0x20 /* Stand-by (power down) mode control */ -#define FE_D7_IDENT 0xC0 /* Chip identification */ - -#define FE_D7_BYTSWP_LH 0x00 /* DEC/Intel byte order */ -#define FE_D7_BYTSWP_HL 0x01 /* IBM/Motorolla byte order */ - -#define FE_D7_RBS_DLCR 0x00 /* Select DLCR8-15 */ -#define FE_D7_RBS_MAR 0x04 /* Select MAR8-15 */ -#define FE_D7_RBS_BMPR 0x08 /* Select BMPR8-15 */ - -#define FE_D7_POWER_DOWN 0x00 /* Power down (stand-by) mode */ -#define FE_D7_POWER_UP 0x20 /* Normal operation */ - -#define FE_D7_IDENT_NICE 0x80 -#define FE_D7_IDENT_EC 0xC0 - -/* DLCR8 thru DLCR13 are for Ethernet station address. */ - -/* DLCR14 and DLCR15 are for TDR. (BTW, what is TDR? FIXME.) */ - -/* MAR8 thru MAR15 are for Multicast address filter. */ - -/* BMPR8 and BMPR9 are for packet data. */ - -/* BMPR10 -- transmitter start trigger */ -#define FE_B10_START 0x80 /* Start transmitter */ -#define FE_B10_COUNT 0x7F /* Packet count */ - -/* BMPR11 -- 16 collisions control */ -#define FE_B11_CTRL 0x01 /* Skip or resend errored packets */ -#define FE_B11_MODE1 0x02 /* Restart transmitter after COLL16 */ -#define FE_B11_MODE2 0x04 /* Automatic restart enable */ - -#define FE_B11_CTRL_RESEND 0x00 /* Re-send the collided packet */ -#define FE_B11_CTRL_SKIP 0x01 /* Skip the collided packet */ - -/* BMPR12 -- DMA enable */ -#define FE_B12_TXDMA 0x01 /* Enable transmitter DMA */ -#define FE_B12_RXDMA 0x02 /* Enable receiver DMA */ - -/* BMPR13 -- DMA control */ -#define FE_B13_BSTCTL 0x03 /* DMA burst mode control */ -#define FE_B13_TPTYPE 0x04 /* Twisted pair cable impedance */ -#define FE_B13_PORT 0x18 /* Port (TP/AUI) selection */ -#define FE_B13_LNKTST 0x20 /* Link test enable */ -#define FE_B13_SQTHLD 0x40 /* Lower squelch threshold */ -#define FE_B13_IOUNLK 0x80 /* Change I/O base address */ - -#define FE_B13_BSTCTL_1 0x00 -#define FE_B13_BSTCTL_4 0x01 -#define FE_B13_BSTCTL_8 0x02 -#define FE_B13_BSTCLT_12 0x03 - -#define FE_B13_TPTYPE_UTP 0x00 /* Unshielded (standard) cable */ -#define FE_B13_TPTYPE_STP 0x04 /* Shielded (IBM) cable */ - -#define FE_B13_PORT_AUTO 0x00 /* Auto detected */ -#define FE_B13_PORT_TP 0x08 /* Force TP */ -#define FE_B13_PORT_AUI 0x18 /* Force AUI */ - -/* BMPR14 -- More receiver control and more transmission interrupts */ -#define FE_B14_FILTER 0x01 /* Filter out self-originated packets */ -#define FE_B14_SQE 0x02 /* SQE interrupt enable */ -#define FE_B14_SKIP 0x04 /* Skip a received packet */ -#define FE_B14_RJAB 0x20 /* RJAB interrupt enable */ -#define FE_B14_LLD 0x40 /* Local-link-down interrupt enable */ -#define FE_B14_RLD 0x80 /* Remote-link-down interrupt enable */ - -/* BMPR15 -- More transmitter status; basically same layout as BMPR14 */ -#define FE_B15_SQE FE_B14_SQE -#define FE_B15_RCVPOL 0x08 /* Reversed receive line polarity */ -#define FE_B15_RMTPRT 0x10 /* ??? */ -#define FE_B15_RAJB FE_B14_RJAB -#define FE_B15_LLD FE_B14_LLD -#define FE_B15_RLD FE_B14_RLD - -/* BMPR16 -- EEPROM control */ -#define FE_B16_DOUT 0x04 /* EEPROM Data in (CPU to EEPROM) */ -#define FE_B16_SELECT 0x20 /* EEPROM chip select */ -#define FE_B16_CLOCK 0x40 /* EEPROM shift clock */ -#define FE_B16_DIN 0x80 /* EEPROM data out (EEPROM to CPU) */ - -/* BMPR17 -- EEPROM data */ -#define FE_B17_DATA 0x80 /* EEPROM data bit */ - -/* BMPR18 ??? */ - -/* BMPR19 -- ISA interface configuration */ -#define FE_B19_IRQ 0xC0 -#define FE_B19_IRQ_SHIFT 6 - -#define FE_B19_ROM 0x38 -#define FE_B19_ROM_SHIFT 3 - -#define FE_B19_ADDR 0x07 -#define FE_B19_ADDR_SHIFT 0 - -/* - * EEPROM specification (of JLI mode). - */ - -/* Number of bytes in an EEPROM accessible through 86965. */ -#define FE_EEPROM_SIZE 32 - -/* Offset for JLI config; automatically copied into BMPR19 at startup. */ -#define FE_EEPROM_CONF 0 - -/* - * Some 86960 specific constants. - */ - -/* Length (in bytes) of a Multicast Address Filter. */ -#define FE_FILTER_LEN 8 - -/* How many packets we can put in the transmission buffer on NIC memory. */ -#define FE_QUEUEING_MAX 127 - -/* Length (in bytes) of a "packet length" word in transmission buffer. */ -#define FE_DATA_LEN_LEN 2 diff --git a/sys/dev/ic/mc146818.h b/sys/dev/ic/mc146818.h deleted file mode 100644 index ff4011cf2b35..000000000000 --- a/sys/dev/ic/mc146818.h +++ /dev/null @@ -1,194 +0,0 @@ -/* $NetBSD: mc146818.h,v 1.1 1995/05/04 19:31:18 cgd Exp $ */ - -/* - * Copyright (c) 1995 Carnegie-Mellon University. - * All rights reserved. - * - * Permission to use, copy, modify and distribute this software and - * its documentation is hereby granted, provided that both the copyright - * notice and this permission notice appear in all copies of the - * software, derivative works or modified versions, and any portions - * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND - * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * - * Carnegie Mellon requests users of this software to return to - * - * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU - * School of Computer Science - * Carnegie Mellon University - * Pittsburgh PA 15213-3890 - * - * any improvements or extensions that they make and grant Carnegie the - * rights to redistribute these changes. - */ - -/* - * Definitions for the Motorola MC146818A Real Time Clock. - * They also apply for the (compatible) Dallas Semicontuctor DS1287A RTC. - * - * Though there are undoubtedly other (better) sources, this material was - * culled from the DEC "KN121 System Module Programmer's Reference - * Information." - * - * The MC146818A has 16 registers. The first 10 contain time-of-year - * and alarm data. The rest contain various control and status bits. - * - * To read or write the registers, one writes the register number to - * the RTC's control port, then either reads from or writes the new - * data to the RTC's data port. Since the locations of these ports - * and the method used to access them can be machine-dependent, the - * low-level details of reading and writing the RTC's registers are - * handled by machine-specific functions. - * - * The time-of-year and alarm data can be expressed in either binary - * or BCD, and they are selected by a bit in register B. - * - * The "hour" time-of-year and alarm fields can either be expressed in - * AM/PM format, or in 24-hour format. If AM/PM format is chosen, the - * hour fields can have the values: 1-12 and 81-92 (the latter being - * PM). If the 24-hour format is chosen, they can have the values - * 0-24. The hour format is selectable by a bit in register B. - * (XXX IS AM/PM MODE DESCRIPTION CORRECT?) - * - * It is assumed the if systems are going to use BCD (rather than - * binary) mode, or AM/PM hour format, they'll do the appropriate - * conversions in machine-dependent code. Also, if the clock is - * switched between BCD and binary mode, or between AM/PM mode and - * 24-hour mode, the time-of-day and alarm registers are NOT - * automatically reset; they must be reprogrammed with correct values. - */ - -/* - * The registers, and the bits within each register. - */ - -#define MC_SEC 0x0 /* Time of year: seconds (0-59) */ -#define MC_ASEC 0x1 /* Alarm: seconds */ -#define MC_MIN 0x2 /* Time of year: minutes (0-59) */ -#define MC_AMIN 0x3 /* Alarm: minutes */ -#define MC_HOUR 0x4 /* Time of year: hour (see above) */ -#define MC_AHOUR 0x5 /* Alarm: hour */ -#define MC_DOW 0x6 /* Time of year: day of week (1-7) */ -#define MC_DOM 0x7 /* Time of year: day of month (1-31) */ -#define MC_MONTH 0x8 /* Time of year: month (1-12) */ -#define MC_YEAR 0x9 /* Time of year: year in century (0-99) */ - -#define MC_REGA 0xa /* Control register A */ - -#define MC_REGA_RSMASK 0x0f /* Interrupt rate select mask (see below) */ -#define MC_REGA_DVMASK 0x70 /* Divisor select mask (see below) */ -#define MC_REGA_UIP 0x80 /* Update in progress; read only. */ - -#define MC_REGB 0xb /* Control register B */ - -#define MC_REGB_DSE 0x01 /* Daylight Savings Enable */ -#define MC_REGB_24HR 0x02 /* 24-hour mode (AM/PM mode when clear) */ -#define MC_REGB_BINARY 0x04 /* Binary mode (BCD mode when clear) */ -/* MC_REGB_UNUSED 0x08 UNUSED */ -#define MC_REGB_UIE 0x10 /* Update End interrupt enable */ -#define MC_REGB_AIE 0x20 /* Alarm interrupt enable */ -#define MC_REGB_PIE 0x40 /* Periodic interrupt enable */ -#define MC_REGB_SET 0x80 /* Allow time to be set; stops updates */ - -#define MC_REGC 0xc /* Control register C */ - -/* MC_REGC_UNUSED 0x0f UNUSED */ -#define MC_REGC_UF 0x10 /* Update End interrupt flag */ -#define MC_REGC_AF 0x20 /* Alarm interrupt flag */ -#define MC_REGC_PF 0x40 /* Periodic interrupt flag */ -#define MC_REGC_IRQF 0x80 /* Interrupt request pending flag */ - -#define MC_REGD 0xd /* Control register D */ - -/* MC_REGD_UNUSED 0x7f UNUSED */ -#define MC_REGD_VRT 0x80 /* Valid RAM and Time bit */ - - -#define MC_NREGS 0xe /* 14 registers; CMOS follows */ -#define MC_NTODREGS 0xa /* 10 of those regs are for TOD and alarm */ - -#define MC_NVRAM_START 0xe /* start of NVRAM: offset 14 */ -#define MC_NVRAM_SIZE 50 /* 50 bytes of NVRAM */ - -/* - * Periodic Interrupt Rate Select constants (Control register A) - */ -#define MC_RATE_NONE 0x0 /* No periodic interrupt */ -#define MC_RATE_1 0x1 /* 256 Hz if MC_BASE_32_KHz, else 32768 Hz */ -#define MC_RATE_2 0x2 /* 128 Hz if MC_BASE_32_KHz, else 16384 Hz */ -#define MC_RATE_8192_Hz 0x3 /* 122.070 us period */ -#define MC_RATE_4096_Hz 0x4 /* 244.141 us period */ -#define MC_RATE_2048_Hz 0x5 /* 488.281 us period */ -#define MC_RATE_1024_Hz 0x6 /* 976.562 us period */ -#define MC_RATE_512_Hz 0x7 /* 1.953125 ms period */ -#define MC_RATE_256_Hz 0x8 /* 3.90625 ms period */ -#define MC_RATE_128_Hz 0x9 /* 7.8125 ms period */ -#define MC_RATE_64_Hz 0xa /* 15.625 ms period */ -#define MC_RATE_32_Hz 0xb /* 31.25 ms period */ -#define MC_RATE_16_Hz 0xc /* 62.5 ms period */ -#define MC_RATE_8_Hz 0xd /* 125 ms period */ -#define MC_RATE_4_Hz 0xe /* 250 ms period */ -#define MC_RATE_2_Hz 0xf /* 500 ms period */ - -/* - * Time base (divisor select) constants (Control register A) - */ -#define MC_BASE_4_MHz 0x00 /* 4MHz crystal */ -#define MC_BASE_1_MHz 0x10 /* 1MHz crystal */ -#define MC_BASE_32_KHz 0x20 /* 32KHz crystal */ -#define MC_BASE_NONE 0x60 /* actually, both of these reset */ -#define MC_BASE_RESET 0x70 - - -/* - * RTC register/NVRAM read and write functions -- machine-dependent. - * Appropriately manipulate RTC registers to get/put data values. - */ -u_int mc146818_read __P((void *sc, u_int reg)); -void mc146818_write __P((void *sc, u_int reg, u_int datum)); - -/* - * A collection of TOD/Alarm registers. - */ -typedef u_int mc_todregs[MC_NTODREGS]; - -/* - * Get all of the TOD/Alarm registers - * Must be called at splhigh(), and with the RTC properly set up. - */ -#define MC146818_GETTOD(sc, regs) \ - do { \ - int i; \ - \ - /* update in progress; spin loop */ \ - while (mc146818_read(sc, MC_REGA) & MC_REGA_UIP) \ - ; \ - \ - /* read all of the tod/alarm regs */ \ - for (i = 0; i < MC_NTODREGS; i++) \ - (*regs)[i] = mc146818_read(sc, i); \ - } while (0); - -/* - * Set all of the TOD/Alarm registers - * Must be called at splhigh(), and with the RTC properly set up. - */ -#define MC146818_PUTTOD(sc, regs) \ - do { \ - int i; \ - \ - /* stop updates while setting */ \ - mc146818_write(sc, MC_REGB, \ - mc146818_read(sc, MC_REGB) | MC_REGB_SET); \ - \ - /* write all of the tod/alarm regs */ \ - for (i = 0; i < MC_NTODREGS; i++) \ - mc146818_write(sc, i, (*regs)[i]); \ - \ - /* reenable updates */ \ - mc146818_write(sc, MC_REGB, \ - mc146818_read(sc, MC_REGB) & ~MC_REGB_SET); \ - } while (0); diff --git a/sys/dev/ic/nec765.h b/sys/dev/ic/nec765.h deleted file mode 100644 index 1418f03a6be4..000000000000 --- a/sys/dev/ic/nec765.h +++ /dev/null @@ -1,73 +0,0 @@ -/* $NetBSD: nec765.h,v 1.3 1994/10/27 04:18:41 cgd Exp $ */ - -/*- - * Copyright (c) 1991 The Regents of the University of California. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)nec765.h 7.1 (Berkeley) 5/9/91 - */ - -/* - * Nec 765 floppy disc controller definitions - */ - -/* Main status register */ -#define NE7_DAB 0x01 /* Diskette drive A is seeking, thus busy */ -#define NE7_DBB 0x02 /* Diskette drive B is seeking, thus busy */ -#define NE7_CB 0x10 /* Diskette Controller Busy */ -#define NE7_NDM 0x20 /* Diskette Controller in Non Dma Mode */ -#define NE7_DIO 0x40 /* Diskette Controller Data register I/O */ -#define NE7_RQM 0x80 /* Diskette Controller ReQuest for Master */ - -/* Status register ST0 */ -#define NE7_ST0BITS "\020\010invld\007abnrml\006seek_cmplt\005drv_chck\004drive_rdy\003top_head" - -/* Status register ST1 */ -#define NE7_ST1BITS "\020\010end_of_cyl\006bad_crc\005data_overrun\003sec_not_fnd\002write_protect\001no_am" - -/* Status register ST2 */ -#define NE7_ST2BITS "\020\007ctrl_mrk\006bad_crc\005wrong_cyl\004scn_eq\003scn_not_fnd\002bad_cyl\001no_dam" - -/* Status register ST3 */ -#define NE7_ST3BITS "\020\010fault\007write_protect\006drdy\005tk0\004two_side\003side_sel\002" - -/* Commands */ -#define NE7CMD_SPECIFY 3 /* specify drive parameters - requires unit - parameters byte */ -#define NE7CMD_SENSED 4 /* sense drive - requires unit select byte */ -#define NE7CMD_WRITE 0xc5 /* write - requires eight additional bytes */ -#define NE7CMD_READ 0xe6 /* read - requires eight additional bytes */ -#define NE7CMD_FORMAT 0x4c /* format - requires five additional bytes */ -#define NE7CMD_RECAL 7 /* recalibrate drive - requires - unit select byte */ -#define NE7CMD_SENSEI 8 /* sense controller interrupt status */ -#define NE7CMD_SEEK 15 /* seek drive - requires unit select byte - and new cyl byte */ diff --git a/sys/dev/ic/ns16450.h b/sys/dev/ic/ns16450.h deleted file mode 100644 index ad654cd12971..000000000000 --- a/sys/dev/ic/ns16450.h +++ /dev/null @@ -1,51 +0,0 @@ -/* $NetBSD: ns16450.h,v 1.3 1994/10/27 04:18:42 cgd Exp $ */ - -/*- - * Copyright (c) 1991 The Regents of the University of California. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)ns16450.h 7.1 (Berkeley) 5/9/91 - */ - -/* - * NS16450 UART registers - */ - -#define com_data 0 /* data register (R/W) */ -#define com_dlbl 0 /* divisor latch low (W) */ -#define com_dlbh 1 /* divisor latch high (W) */ -#define com_ier 1 /* interrupt enable (W) */ -#define com_iir 2 /* interrupt identification (R) */ -#define com_lctl 3 /* line control register (R/W) */ -#define com_cfcr 3 /* line control register (R/W) */ -#define com_mcr 4 /* modem control register (R/W) */ -#define com_lsr 5 /* line status register (R/W) */ -#define com_msr 6 /* modem status register (R/W) */ diff --git a/sys/dev/ic/ns16550.h b/sys/dev/ic/ns16550.h deleted file mode 100644 index 840f78f7d87d..000000000000 --- a/sys/dev/ic/ns16550.h +++ /dev/null @@ -1,53 +0,0 @@ -/* $NetBSD: ns16550.h,v 1.4 1994/10/27 04:18:43 cgd Exp $ */ - -/*- - * Copyright (c) 1991 The Regents of the University of California. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)ns16550.h 7.1 (Berkeley) 5/9/91 - */ - -/* - * NS16550 UART registers - */ - -#define com_data 0 /* data register (R/W) */ -#define com_dlbl 0 /* divisor latch low (W) */ -#define com_dlbh 1 /* divisor latch high (W) */ -#define com_ier 1 /* interrupt enable (W) */ -#define com_iir 2 /* interrupt identification (R) */ -#define com_fifo 2 /* FIFO control (W) */ -#define com_lctl 3 /* line control register (R/W) */ -#define com_cfcr 3 /* line control register (R/W) */ -#define com_mcr 4 /* modem control register (R/W) */ -#define com_lsr 5 /* line status register (R/W) */ -#define com_msr 6 /* modem status register (R/W) */ -#define com_scratch 7 /* scratch register (R/W) */ diff --git a/sys/dev/ic/z8530.h b/sys/dev/ic/z8530.h deleted file mode 100644 index 4b1fafd7a259..000000000000 --- a/sys/dev/ic/z8530.h +++ /dev/null @@ -1,432 +0,0 @@ -/* $NetBSD: z8530.h,v 1.3 1995/06/19 13:15:08 briggs Exp $ */ - -/* - * Copyright (c) 1992, 1993 - * The Regents of the University of California. All rights reserved. - * - * This software was developed by the Computer Systems Engineering group - * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and - * contributed to Berkeley. - * - * All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Lawrence Berkeley Laboratory. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)zsreg.h 8.1 (Berkeley) 6/11/93 - */ - -/* - * Zilog SCC registers, as implemented on the Sun-4c. - * - * Each Z8530 implements two channels (called `a' and `b'). - * - * The damnable chip was designed to fit on Z80 I/O ports, and thus - * has everything multiplexed out the wazoo. We have to select - * a register, then read or write the register, and so on. Worse, - * the parameter bits are scattered all over the register space. - * This thing is full of `miscellaneous' control registers. - * - * Worse yet, the registers have incompatible functions on read - * and write operations. We describe the registers below according - * to whether they are `read registers' (RR) or `write registers' (WR). - * As if this were not enough, some of the channel B status bits show - * up in channel A, and vice versa. The blasted thing shares write - * registers 2 and 9 across both channels, and reads registers 2 and 3 - * differently for the two channels. We can, however, ignore this much - * of the time. - */ -#ifndef LOCORE -struct zschan { -#if BYTE_ORDER == BIG_ENDIAN - u_char zc_csr; /* control and status, and indirect access */ - u_char zc_xxx0; - u_char zc_data; /* data */ - u_char zc_xxx1; -#else - u_char zc_xxx0; - u_char zc_csr; /* control and status, and indirect access */ - u_char zc_xxx1; - u_char zc_data; /* data */ -#endif -}; - -struct zsdevice { - struct zschan zs_chan[2]; -}; -#endif - -/* - * Some of the names in this files were chosen to make the hsis driver - * work unchanged (which means that they will match some in SunOS). - * - * `S.C.' stands for Special Condition, which is any of these: - * receiver overrun (aka silo overflow) - * framing error (missing stop bit, etc) - * end of frame (in synchronous modes) - * parity error (when `parity error is S.C.' is set) - */ - -/* - * Registers with only a single `numeric value' get a name. - * Other registers hold bits and are only numbered; the bit - * definitions imply the register number (see below). - * - * We never use the receive and transmit data registers as - * indirects (choosing instead the zc_data register), so they - * are not defined here. - */ -#define ZSRR_IVEC 2 /* interrupt vector (channel 0) */ -#define ZSRR_IPEND 3 /* interrupt pending (ch. 0 only) */ -#define ZSRR_BAUDLO 12 /* baud rate generator (low half) */ -#define ZSRR_BAUDHI 13 /* baud rate generator (high half) */ - -#define ZSWR_IVEC 2 /* interrupt vector (shared) */ -#define ZSWR_TXSYNC 6 /* sync transmit char (monosync mode) */ -#define ZSWR_RXSYNC 7 /* sync receive char (monosync mode) */ -#define ZSWR_SYNCLO 6 /* sync low byte (bisync mode) */ -#define ZSWR_SYNCHI 7 /* sync high byte (bisync mode) */ -#define ZSWR_SDLC_ADDR 6 /* SDLC address (SDLC mode) */ -#define ZSWR_SDLC_FLAG 7 /* SDLC flag 0x7E (SDLC mode) */ -#define ZSWR_BAUDLO 12 /* baud rate generator (low half) */ -#define ZSWR_BAUDHI 13 /* baud rate generator (high half) */ - -/* - * Registers 0 through 7 may be written with any one of the 8 command - * modifiers, and/or any one of the 4 reset modifiers, defined below. - * To write registers 8 through 15, however, the command modifier must - * always be `point high'. Rather than track this bizzareness all over - * the driver, we try to avoid using any modifiers, ever (but they are - * defined here if you want them). - */ -#define ZSM_RESET_TXUEOM 0xc0 /* reset xmit underrun / eom latch */ -#define ZSM_RESET_TXCRC 0x80 /* reset xmit crc generator */ -#define ZSM_RESET_RXCRC 0x40 /* reset recv crc checker */ -#define ZSM_NULL 0x00 /* nothing special */ - -#define ZSM_RESET_IUS 0x38 /* reset interrupt under service */ -#define ZSM_RESET_ERR 0x30 /* reset error cond */ -#define ZSM_RESET_TXINT 0x28 /* reset xmit interrupt pending */ -#define ZSM_EI_NEXTRXC 0x20 /* enable int. on next rcvd char */ -#define ZSM_SEND_ABORT 0x18 /* send abort (SDLC) */ -#define ZSM_RESET_STINT 0x10 /* reset external/status interrupt */ -#define ZSM_POINTHIGH 0x08 /* `point high' (use r8-r15) */ -#define ZSM_NULL 0x00 /* nothing special */ - -/* - * Commands for Write Register 0 (`Command Register'). - * These are just the command modifiers or'ed with register number 0 - * (which of course equals the command modifier). - */ -#define ZSWR0_RESET_EOM ZSM_RESET_TXUEOM -#define ZSWR0_RESET_TXCRC ZSM_RESET_TXCRC -#define ZSWR0_RESET_RXCRC ZSM_RESET_RXCRC -#define ZSWR0_CLR_INTR ZSM_RESET_IUS -#define ZSWR0_RESET_ERRORS ZSM_RESET_ERR -#define ZSWR0_EI_NEXTRXC ZSM_EI_NEXTRXC -#define ZSWR0_SEND_ABORT ZSM_SEND_ABORT -#define ZSWR0_RESET_STATUS ZSM_RESET_STINT -#define ZSWR0_RESET_TXINT ZSM_RESET_TXINT - -/* - * Bits in Write Register 1 (`Transmit/Receive Interrupt and Data - * Transfer Mode Definition'). Note that bits 3 and 4 are taken together - * as a single unit, and bits 5 and 6 are useful only if bit 7 is set. - */ -#define ZSWR1_REQ_WAIT 0x80 /* WAIT*-REQ* pin gives WAIT* */ -#define ZSWR1_REQ_REQ 0xc0 /* WAIT*-REQ* pin gives REQ* */ -#define ZSWR1_REQ_TX 0x00 /* WAIT*-REQ* pin follows xmit buf */ -#define ZSWR1_REQ_RX 0x20 /* WAIT*-REQ* pin follows recv buf */ - -#define ZSWR1_RIE_NONE 0x00 /* disable rxint entirely */ -#define ZSWR1_RIE_FIRST 0x08 /* rxint on first char & on S.C. */ -#define ZSWR1_RIE 0x10 /* rxint per char & on S.C. */ -#define ZSWR1_RIE_SPECIAL_ONLY 0x18 /* rxint on S.C. only */ - -#define ZSWR1_PE_SC 0x04 /* parity error is special condition */ -#define ZSWR1_TIE 0x02 /* transmit interrupt enable */ -#define ZSWR1_SIE 0x01 /* external/status interrupt enable */ - -/* HSIS compat */ -#define ZSWR1_REQ_ENABLE (ZSWR1_REQ_WAIT | ZSWR1_REQ_TX) - -/* - * Bits in Write Register 3 (`Receive Parameters and Control'). - * Bits 7 and 6 are taken as a unit. Note that the receive bits - * per character ordering is insane. - * - * Here `hardware flow control' means CTS enables the transmitter - * and DCD enables the receiver. The latter is neither interesting - * nor useful, and gets in our way, making it almost unusable. - */ -#define ZSWR3_RX_5 0x00 /* receive 5 bits per char */ -#define ZSWR3_RX_7 0x40 /* receive 7 bits per char */ -#define ZSWR3_RX_6 0x80 /* receive 6 bits per char */ -#define ZSWR3_RX_8 0xc0 /* receive 8 bits per char */ - -#define ZSWR3_HFC 0x20 /* hardware flow control */ -#define ZSWR3_HUNT 0x10 /* enter hunt mode */ -#define ZSWR3_RXCRC_ENABLE 0x08 /* enable recv crc calculation */ -#define ZSWR3_ADDR_SEARCH_MODE 0x04 /* address search mode (SDLC only) */ -#define ZSWR3_SYNC_LOAD_INH 0x02 /* sync character load inhibit */ -#define ZSWR3_RX_ENABLE 0x01 /* receiver enable */ - -/* - * Bits in Write Register 4 (`Transmit/Receive Miscellaneous Parameters - * and Modes'). Bits 7&6, 5&4, and 3&2 are taken as units. - */ -#define ZSWR4_CLK_X1 0x00 /* clock divisor = 1 */ -#define ZSWR4_CLK_X16 0x40 /* clock divisor = 16 */ -#define ZSWR4_CLK_X32 0x80 /* clock divisor = 32 */ -#define ZSWR4_CLK_X64 0xc0 /* clock divisor = 64 */ - -#define ZSWR4_MONOSYNC 0x00 /* 8 bit sync char (sync only) */ -#define ZSWR4_BISYNC 0x10 /* 16 bit sync char (sync only) */ -#define ZSWR4_SDLC 0x20 /* SDLC mode */ -#define ZSWR4_EXTSYNC 0x30 /* external sync mode */ - -#define ZSWR4_SYNCMODE 0x00 /* one of the above sync modes */ -#define ZSWR4_ONESB 0x04 /* 1 stop bit */ -#define ZSWR4_1P5SB 0x08 /* 1.5 stop bits (clk cannot be 1x) */ -#define ZSWR4_TWOSB 0x0c /* 2 stop bits */ - -#define ZSWR4_EVENP 0x02 /* check for even parity */ -#define ZSWR4_PARENB 0x01 /* enable parity checking */ - -/* - * Bits in Write Register 5 (`Transmit Parameter and Controls'). - * Bits 6 and 5 are taken as a unit; the ordering is, as with RX - * bits per char, not sensible. - */ -#define ZSWR5_DTR 0x80 /* assert (set to -12V) DTR */ - -#define ZSWR5_TX_5 0x00 /* transmit 5 or fewer bits */ -#define ZSWR5_TX_7 0x20 /* transmit 7 bits */ -#define ZSWR5_TX_6 0x40 /* transmit 6 bits */ -#define ZSWR5_TX_8 0x60 /* transmit 8 bits */ - -#define ZSWR5_BREAK 0x10 /* send break (continuous 0s) */ -#define ZSWR5_TX_ENABLE 0x08 /* enable transmitter */ -#define ZSWR5_CRC16 0x04 /* use CRC16 (off => use SDLC) */ -#define ZSWR5_RTS 0x02 /* assert RTS */ -#define ZSWR5_TXCRC_ENABLE 0x01 /* enable xmit crc calculation */ - -#ifdef not_done_here -/* - * Bits in Write Register 7 when the chip is in SDLC mode. - */ -#define ZSWR7_SDLCFLAG 0x7e /* this value makes SDLC mode work */ -#endif - -/* - * Bits in Write Register 9 (`Master Interrupt Control'). Bits 7 & 6 - * are taken as a unit and indicate the type of reset; 00 means no reset - * (and is not defined here). - */ -#define ZSWR9_HARD_RESET 0xc0 /* force hardware reset */ -#define ZSWR9_A_RESET 0x80 /* reset channel A (0) */ -#define ZSWR9_B_RESET 0x40 /* reset channel B (1) */ - /* 0x20 unused */ - -#define ZSWR9_STATUS_HIGH 0x10 /* status in high bits of intr vec */ -#define ZSWR9_MASTER_IE 0x08 /* master interrupt enable */ -#define ZSWR9_DLC 0x04 /* disable lower chain */ -#define ZSWR9_NO_VECTOR 0x02 /* no vector */ -#define ZSWR9_VECTOR_INCL_STAT 0x01 /* vector includes status */ - -/* - * Bits in Write Register 10 (`Miscellaneous Transmitter/Receiver Control - * Bits'). Bits 6 & 5 are taken as a unit, and some of the bits are - * meaningful only in certain modes. Bleah. - */ -#define ZSWR10_PRESET_ONES 0x80 /* preset CRC to all 1 (else all 0) */ - -#define ZSWR10_NRZ 0x00 /* NRZ encoding */ -#define ZSWR10_NRZI 0x20 /* NRZI encoding */ -#define ZSWR10_FM1 0x40 /* FM1 encoding */ -#define ZSWR10_FM0 0x60 /* FM0 encoding */ - -#define ZSWR10_GA_ON_POLL 0x10 /* go active on poll (loop mode) */ -#define ZSWR10_MARK_IDLE 0x08 /* all 1s (vs flag) when idle (SDLC) */ -#define ZSWR10_ABORT_ON_UNDERRUN 0x4 /* abort on xmit underrun (SDLC) */ -#define ZSWR10_LOOP_MODE 0x02 /* loop mode (SDLC) */ -#define ZSWR10_6_BIT_SYNC 0x01 /* 6 bits per sync char (sync modes) */ - -/* - * Bits in Write Register 11 (`Clock Mode Control'). Bits 6&5, 4&3, and - * 1&0 are taken as units. Various bits depend on other bits in complex - * ways; see the Zilog manual. - */ -#define ZSWR11_XTAL 0x80 /* have xtal between RTxC* and SYNC* */ - /* (else have TTL oscil. on RTxC*) */ -#define ZSWR11_RXCLK_RTXC 0x00 /* recv clock taken from TRxC* pin */ -#define ZSWR11_RXCLK_TRXC 0x20 /* recv clock taken from TRxC* pin */ -#define ZSWR11_RXCLK_BAUD 0x40 /* recv clock taken from BRG */ -#define ZSWR11_RXCLK_DPLL 0x60 /* recv clock taken from DPLL */ - -#define ZSWR11_TXCLK_RTXC 0x00 /* xmit clock taken from TRxC* pin */ -#define ZSWR11_TXCLK_TRXC 0x08 /* xmit clock taken from RTxC* pin */ -#define ZSWR11_TXCLK_BAUD 0x10 /* xmit clock taken from BRG */ -#define ZSWR11_TXCLK_DPLL 0x18 /* xmit clock taken from DPLL */ - -#define ZSWR11_TRXC_OUT_ENA 0x04 /* TRxC* pin will be an output */ - /* (unless it is being used above) */ -#define ZSWR11_TRXC_XTAL 0x00 /* TRxC output from xtal oscillator */ -#define ZSWR11_TRXC_XMIT 0x01 /* TRxC output from xmit clock */ -#define ZSWR11_TRXC_BAUD 0x02 /* TRxC output from BRG */ -#define ZSWR11_TRXC_DPLL 0x03 /* TRxC output from DPLL */ - -/* - * Formula for Write Registers 12 and 13 (`Lower Byte of Baud Rate - * Generator Time Constant' and `Upper Byte of ...'). Inputs: - * - * f BRG input clock frequency (in Hz) AFTER division - * by 1, 16, 32, or 64 (per clock divisor in WR4) - * bps desired rate in bits per second (9600, etc) - * - * We want - * - * f - * ----- + 0.5 - 2 - * 2 bps - * - * rounded down to an integer. This can be computed entirely - * in integer arithemtic as: - * - * f + bps - * ------- - 2 - * 2 bps - */ -#define BPS_TO_TCONST(f, bps) ((((f) + (bps)) / (2 * (bps))) - 2) - -/* inverse of above: given a BRG Time Constant, return Bits Per Second */ -#define TCONST_TO_BPS(f, tc) ((f) / 2 / ((tc) + 2)) - -/* - * Bits in Write Register 14 (`Miscellaneous Control Bits'). - * Bits 7 through 5 are taken as a unit and make up a `DPLL command'. - */ -#define ZSWR14_DPLL_NOOP 0x00 /* leave DPLL alone */ -#define ZSWR14_DPLL_SEARCH 0x20 /* enter search mode */ -#define ZSWR14_DPLL_RESET_CM 0x40 /* reset `clock missing' in RR10 */ -#define ZSWR14_DPLL_DISABLE 0x60 /* disable DPLL (continuous search) */ -#define ZSWR14_DPLL_SRC_BAUD 0x80 /* set DPLL src = BRG */ -#define ZSWR14_DPLL_SRC_RTXC 0xa0 /* set DPLL src = RTxC* or xtal osc */ -#define ZSWR14_DPLL_FM 0xc0 /* operate in FM mode */ -#define ZSWR14_DPLL_NRZI 0xe0 /* operate in NRZI mode */ - -#define ZSWR14_LOCAL_LOOPBACK 0x10 /* set local loopback mode */ -#define ZSWR14_AUTO_ECHO 0x08 /* set auto echo mode */ -#define ZSWR14_DTR_REQ 0x04 /* DTR* / REQ* pin gives REQ* */ -#define ZSWR14_BAUD_FROM_PCLK 0x02 /* BRG clock taken from PCLK */ - /* (else from RTxC* pin or xtal osc) */ -#define ZSWR14_BAUD_ENA 0x01 /* enable BRG countdown */ - -/* - * Bits in Write Register 15 (`External/Status Interrupt Control'). - * Most of these cause status interrupts whenever the corresponding - * bit or pin changes state (i.e., any rising or falling edge). - */ -#define ZSWR15_BREAK_IE 0x80 /* enable break/abort status int */ -#define ZSWR15_TXUEOM_IE 0x40 /* enable TX underrun/EOM status int */ -#define ZSWR15_CTS_IE 0x20 /* enable CTS* pin status int */ -#define ZSWR15_SYNCHUNT_IE 0x10 /* enable SYNC* pin/hunt status int */ -#define ZSWR15_DCD_IE 0x08 /* enable DCD* pin status int */ - /* 0x04 unused, must be zero */ -#define ZSWR15_ZERO_COUNT_IE 0x02 /* enable BRG-counter = 0 status int */ - /* 0x01 unused, must be zero */ - -/* - * Bits in Read Register 0 (`Transmit/Receive Buffer Status and External - * Status'). - */ -#define ZSRR0_BREAK 0x80 /* break/abort detected */ -#define ZSRR0_TXUNDER 0x40 /* transmit underrun/EOM (sync) */ -#define ZSRR0_CTS 0x20 /* clear to send */ -#define ZSRR0_SYNC_HUNT 0x10 /* sync/hunt (sync mode) */ -#define ZSRR0_DCD 0x08 /* data carrier detect */ -#define ZSRR0_TX_READY 0x04 /* transmit buffer empty */ -#define ZSRR0_ZERO_COUNT 0x02 /* zero count in baud clock */ -#define ZSRR0_RX_READY 0x01 /* received character ready */ - -/* - * Bits in Read Register 1 (the Zilog book does not name this one). - */ -#define ZSRR1_EOF 0x80 /* end of frame (SDLC mode) */ -#define ZSRR1_FE 0x40 /* CRC/framing error */ -#define ZSRR1_DO 0x20 /* data (receiver) overrun */ -#define ZSRR1_PE 0x10 /* parity error */ -#define ZSRR1_RC0 0x08 /* residue code 0 (SDLC mode) */ -#define ZSRR1_RC1 0x04 /* residue code 1 (SDLC mode) */ -#define ZSRR1_RC2 0x02 /* residue code 2 (SDLC mode) */ -#define ZSRR1_ALL_SENT 0x01 /* all chars out of xmitter (async) */ - -/* - * Read Register 2 in B channel contains status bits if VECTOR_INCL_STAT - * is set. - */ - -/* - * Bits in Read Register 3 (`Interrupt Pending'). Only channel A - * has an RR3. - */ - /* 0x80 unused, returned as 0 */ - /* 0x40 unused, returned as 0 */ -#define ZSRR3_IP_A_RX 0x20 /* channel A recv int pending */ -#define ZSRR3_IP_A_TX 0x10 /* channel A xmit int pending */ -#define ZSRR3_IP_A_STAT 0x08 /* channel A status int pending */ -#define ZSRR3_IP_B_RX 0x04 /* channel B recv int pending */ -#define ZSRR3_IP_B_TX 0x02 /* channel B xmit int pending */ -#define ZSRR3_IP_B_STAT 0x01 /* channel B status int pending */ - -/* - * Bits in Read Register 10 (`contains some miscellaneous status bits'). - */ -#define ZSRR10_1_CLOCK_MISSING 0x80 /* 1 clock edge missing (FM mode) */ -#define ZSRR10_2_CLOCKS_MISSING 0x40 /* 2 clock edges missing (FM mode) */ - /* 0x20 unused */ -#define ZSRR10_LOOP_SENDING 0x10 /* xmitter controls loop (SDLC loop) */ - /* 0x08 unused */ - /* 0x04 unused */ -#define ZSRR10_ON_LOOP 0x02 /* SCC is on loop (SDLC/X.21 modes) */ - -/* - * Bits in Read Register 15. This register is one of the few that - * simply reads back the corresponding Write Register. - */ -#define ZSRR15_BREAK_IE 0x80 /* break/abort status int enable */ -#define ZSRR15_TXUEOM_IE 0x40 /* TX underrun/EOM status int enable */ -#define ZSRR15_CTS_IE 0x20 /* CTS* pin status int enable */ -#define ZSRR15_SYNCHUNT_IE 0x10 /* SYNC* pin/hunt status int enable */ -#define ZSRR15_DCD_IE 0x08 /* DCD* pin status int enable */ - /* 0x04 unused, returned as zero */ -#define ZSRR15_ZERO_COUNT_IE 0x02 /* BRG-counter = 0 status int enable */ - /* 0x01 unused, returned as zero */