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regen.

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This commit is contained in:
cegger 2009-02-11 14:42:52 +00:00
parent 807b74b329
commit 276d5496f2
2 changed files with 18 additions and 5 deletions
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17
sys/dev/mii/miidevs.h
View File

@ -1,10 +1,10 @@
/* $NetBSD: miidevs.h,v 1.84 2009/01/16 20:42:19 cegger Exp $ */
/* $NetBSD: miidevs.h,v 1.85 2009/02/11 14:42:52 cegger Exp $ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* NetBSD: miidevs,v 1.81 2009/01/16 20:41:39 cegger Exp
* NetBSD: miidevs,v 1.83 2009/02/11 14:41:56 cegger Exp
*/
/*-
@ -52,10 +52,15 @@
* which is mangled accordingly to compensate.
*/
/*
* Use "make -f Makefile.miidevs" to regenerate miidevs.h and miidevs_data.h
*/
#define MII_OUI_AGERE 0x00053d /* Agere */
#define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */
#define MII_OUI_ATHEROS 0x001374 /* Atheros */
#define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */
#define MII_OUI_ATHEROS 0x001374 /* Atheros */
#define MII_OUI_ATTANSIC 0x00c82e /* Attansic Technology */
#define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */
#define MII_OUI_BROADCOM2 0x000af7 /* Broadcom Corporation */
#define MII_OUI_CICADA 0x0003F1 /* Cicada Semiconductor */
@ -122,6 +127,12 @@
#define MII_MODEL_ATHEROS_F2 0x0002
#define MII_STR_ATHEROS_F2 "F2 10/100 PHY"
/* Attansic PHYs */
#define MII_MODEL_ATTANSIC_L1 0x0001
#define MII_STR_ATTANSIC_L1 "L1 10/100/1000 PHY"
#define MII_MODEL_ATTANSIC_L2 0x0002
#define MII_STR_ATTANSIC_L2 "L2 10/100 PHY"
/* Altima Communications PHYs */
/* Don't know the model for ACXXX */
#define MII_MODEL_ALTIMA_ACXXX 0x0001

6
sys/dev/mii/miidevs_data.h
View File

@ -1,10 +1,10 @@
/* $NetBSD: miidevs_data.h,v 1.74 2009/01/16 20:42:19 cegger Exp $ */
/* $NetBSD: miidevs_data.h,v 1.75 2009/02/11 14:42:52 cegger Exp $ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* NetBSD: miidevs,v 1.81 2009/01/16 20:41:39 cegger Exp
* NetBSD: miidevs,v 1.83 2009/02/11 14:41:56 cegger Exp
*/
/*-
@ -40,6 +40,8 @@ struct mii_knowndev mii_knowndevs[] = {
{ MII_OUI_AGERE, MII_MODEL_AGERE_ET1011, MII_STR_AGERE_ET1011 },
{ MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F1, MII_STR_ATHEROS_F1 },
{ MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F2, MII_STR_ATHEROS_F2 },
{ MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L1, MII_STR_ATTANSIC_L1 },
{ MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L2, MII_STR_ATTANSIC_L2 },
{ MII_OUI_ALTIMA, MII_MODEL_ALTIMA_ACXXX, MII_STR_ALTIMA_ACXXX },
{ MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101, MII_STR_ALTIMA_AC101 },
{ MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101L, MII_STR_ALTIMA_AC101L },