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Support PowerPC 405EX/EXr. 

1. Add some new source and header files.
     (MAL(split) and RGMII(new) relations for EMAC)
  2. Create dcr4xx.h.  Its moved from dcr405gp.h.  Also remove dcr405xx.h.
  3. intr.c supports MULTIUIC with virtual-irq.  likes to oea.
     support 32-virq/128-hwirq.
  4. multiple emac support.
  5. WALNUT and VIRTEX_* includes arch/powerpc/conf/files.ibm4xx.
  6. WALNUT pci uses arch/powerpc/ibm4xx/pci/.
This commit is contained in:
kiyohara 2010-03-18 13:47:04 +00:00
parent f3ce7002f4
commit 2692e2e238
38 changed files with 2205 additions and 2391 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
sys/arch/evbppc/conf/WALNUT
View File

@ -1,4 +1,4 @@
# $NetBSD: WALNUT,v 1.45 2010/02/08 19:02:28 joerg Exp $
# $NetBSD: WALNUT,v 1.46 2010/03/18 13:47:04 kiyohara Exp $
#
# GENERIC -- everything that's currently supported
#
@ -39,7 +39,7 @@ options USERCONF # userconf(4) support
options DDB # in-kernel debugger
options DDB_HISTORY_SIZE=512 # enable history editing in DDB
options TRAP_PANICWAIT
options SYMTAB_SPACE=410000 # size for embedded symbol table
options SYMTAB_SPACE=420000 # size for embedded symbol table
makeoptions DEBUG="-g" # compile full symbol table

30
sys/arch/evbppc/conf/files.obs200
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@ -1,36 +1,8 @@
# $NetBSD: files.obs200,v 1.7 2008/02/20 21:43:34 drochner Exp $
# $NetBSD: files.obs200,v 1.8 2010/03/18 13:47:04 kiyohara Exp $
# Original Tag: files.obs405,v 1.9 2005/01/24 18:47:37 shige Exp
#
# obs200-specific configuration info
file arch/powerpc/ibm4xx/ibm4xx_autoconf.c
file arch/powerpc/ibm4xx/ibm40x_machdep.c
file arch/powerpc/ibm4xx/ibm4xx_machdep.c
file arch/powerpc/ibm4xx/intr.c
file arch/evbppc/obs405/dev/century_bios.c
file arch/evbppc/obs405/consinit.c
file arch/evbppc/obs405/obs200_autoconf.c
file arch/evbppc/obs405/obs200_machdep.c
file arch/evbppc/obs405/obs405_autoconf.c
file arch/evbppc/obs405/obs405_machdep.c
# Memory Disk for install kernel
file dev/md_root.c memory_disk_hooks
# Machine-independent SCSI drivers
include "dev/scsipi/files.scsipi"
# Machine-independent ATA drivers
include "dev/ata/files.ata"
#
# Machine-independent CardBus drivers
#
include "dev/cardbus/files.cardbus"
include "dev/pcmcia/files.pcmcia"
file arch/evbppc/obs405/rbus_machdep.c cardbus
include "dev/usb/files.usb"
include "dev/ieee1394/files.ieee1394"

21
sys/arch/evbppc/conf/files.obs405
View File

@ -1,15 +1,10 @@
# $NetBSD: files.obs405,v 1.20 2008/07/04 17:31:07 kiyohara Exp $
# $NetBSD: files.obs405,v 1.21 2010/03/18 13:47:04 kiyohara Exp $
#
# obs405-specific configuration info
file arch/powerpc/ibm4xx/ibm4xx_autoconf.c
file arch/powerpc/ibm4xx/ibm40x_machdep.c
file arch/powerpc/ibm4xx/ibm4xx_machdep.c
file arch/powerpc/ibm4xx/intr.c
file arch/powerpc/ibm4xx/openbios/openbios.c
file arch/evbppc/obs405/consinit.c
file arch/evbppc/obs405/obs266_autoconf.c
file arch/evbppc/obs405/obs266_machdep.c
file arch/evbppc/obs405/obs405_autoconf.c
file arch/evbppc/obs405/obs405_machdep.c
@ -21,17 +16,3 @@ include "dev/scsipi/files.scsipi"
# Machine-independent ATA drivers
include "dev/ata/files.ata"
#
# Machine-independent CardBus drivers
#
include "dev/cardbus/files.cardbus"
include "dev/pcmcia/files.pcmcia"
file arch/evbppc/obs405/rbus_machdep.c cardbus
include "dev/usb/files.usb"
include "dev/ieee1394/files.ieee1394"
include "dev/bluetooth/files.bluetooth"

19
sys/arch/evbppc/conf/files.virtex
View File

@ -1,4 +1,4 @@
# $NetBSD: files.virtex,v 1.3 2008/02/20 21:43:34 drochner Exp $
# $NetBSD: files.virtex,v 1.4 2010/03/18 13:47:04 kiyohara Exp $
#
# Xilinx Virtex specific configuration
@ -10,8 +10,6 @@ defflag opt_virtex.h DESIGN_DFC
defparam opt_xintc.h DCR_XINTC_BASE
defparam opt_cons.h CONADDR CONSDEV
file arch/powerpc/ibm4xx/intr.c
file arch/evbppc/virtex/autoconf.c
file arch/evbppc/virtex/consinit.c
file arch/evbppc/virtex/machdep.c
@ -20,14 +18,9 @@ file arch/evbppc/virtex/dcr.c
file arch/evbppc/virtex/design_gsrd1.c design_gsrd1
file arch/evbppc/virtex/design_gsrd2.c design_gsrd2 | design_dfc
# Board Properties
file arch/powerpc/ibm4xx/board_prop.c
# Memory Disk for install kernel
file dev/md_root.c memory_disk_hooks
# FPU emulation
include "arch/powerpc/fpu/files.fpu"
# MI drivers
include "dev/pckbport/files.pckbport"
@ -37,16 +30,6 @@ define llbus { } # LocalLink
define plbus { } # PLB
define xcvbus { } # generic
# Processor Local Bus XXX files.ibm4xx
device plb { [irq = -1] }
attach plb at root
file arch/powerpc/ibm4xx/dev/plb.c plb
# Processor XXX files.ibm4xx
device cpu { }
attach cpu at plb
file arch/powerpc/ibm4xx/cpu.c
# Effective mainbus
device xcvbus: xcvbus, plbus, llbus
attach xcvbus at plb

20
sys/arch/evbppc/conf/files.walnut
View File

@ -1,39 +1,21 @@
# $NetBSD: files.walnut,v 1.15 2008/02/20 21:43:34 drochner Exp $
# $NetBSD: files.walnut,v 1.16 2010/03/18 13:47:04 kiyohara Exp $
#
# walnut-specific configuration info
file arch/evbppc/walnut/autoconf.c
file arch/evbppc/walnut/consinit.c
file arch/evbppc/walnut/machdep.c
file arch/powerpc/ibm4xx/intr.c
file arch/powerpc/ibm4xx/ibm4xx_autoconf.c
# Memory Disk for install kernel
file dev/md_root.c memory_disk_hooks
# Machine-independent I2O drivers.
include "dev/i2o/files.i2o"
# Machine-independent SCSI drivers
include "dev/scsipi/files.scsipi"
# Machine-independent ATA drivers
include "dev/ata/files.ata"
# PCI bus support
include "dev/pci/files.pci"
# On-chip PCI bridge
#
# XXX: Move these to a 405gp-specific file and re-think the
# layout of the powerpc/ibm4xx hierarchy to accommodate SoCs.
#
device pchb : pcibus
attach pchb at plb
file arch/evbppc/walnut/pci/pchb.c pchb
file arch/evbppc/walnut/pci/pci_machdep.c pci
file arch/powerpc/ibm4xx/dev/ibm405gp.c
# Off-chip peripheral bus
device pbus {[addr=-1], [irq=-1]}
attach pbus at plb

3
sys/arch/evbppc/conf/std.virtex
View File

@ -1,4 +1,4 @@
# $NetBSD: std.virtex,v 1.1 2006/12/02 22:18:47 freza Exp $
# $NetBSD: std.virtex,v 1.2 2010/03/18 13:47:04 kiyohara Exp $
#
# Standard/required options for NetBSD/virtex.
@ -21,4 +21,5 @@ options PPC_INTR_IMPL="<powerpc/ibm4xx/ibm4xx_intr.h>"
options KERNBASE=0x25000
options INTSTK=16384
include "arch/powerpc/conf/files.ibm4xx"
include "arch/evbppc/conf/files.virtex"

9
sys/arch/evbppc/obs405/obs200_autoconf.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: obs200_autoconf.c,v 1.4 2006/10/07 14:59:53 tsutsui Exp $ */
/* $NetBSD: obs200_autoconf.c,v 1.5 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright 2004 Shigeyuki Fukushima.
@ -33,14 +33,17 @@
* DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: obs200_autoconf.c,v 1.4 2006/10/07 14:59:53 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: obs200_autoconf.c,v 1.5 2010/03/18 13:47:04 kiyohara Exp $");
#include <sys/systm.h>
#include <sys/device.h>
#include <machine/obs200.h>
#include <powerpc/ibm4xx/dcr405gp.h>
#include <powerpc/ibm4xx/cpu.h>
#include <powerpc/ibm4xx/dcr4xx.h>
#include <dev/ic/comreg.h>
/*

4
sys/arch/evbppc/obs405/obs200_locore.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: obs200_locore.S,v 1.8 2010/02/25 23:33:44 matt Exp $ */
/* $NetBSD: obs200_locore.S,v 1.9 2010/03/18 13:47:04 kiyohara Exp $ */
/* Original Tag: locore.S,v 1.1 2003/09/23 15:21:58 shige Exp */
/* $OpenBSD: locore.S,v 1.4 1997/01/26 09:06:38 rahnds Exp $ */
@ -90,7 +90,7 @@
#include <powerpc/spr.h>
#include <powerpc/ibm4xx/spr.h>
#include <powerpc/ibm4xx/dcr405gp.h>
#include <powerpc/ibm4xx/dcr4xx.h>
#include <powerpc/ibm4xx/pmap.h>
/* Function pointer for requesting board_config_data from OpenBlockS S/R BIOS */

25
sys/arch/evbppc/obs405/obs200_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: obs200_machdep.c,v 1.10 2010/02/25 23:33:44 matt Exp $ */
/* $NetBSD: obs200_machdep.c,v 1.11 2010/03/18 13:47:04 kiyohara Exp $ */
/* Original: machdep.c,v 1.3 2005/01/17 17:24:09 shige Exp */
/*
@ -68,7 +68,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: obs200_machdep.c,v 1.10 2010/02/25 23:33:44 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: obs200_machdep.c,v 1.11 2010/03/18 13:47:04 kiyohara Exp $");
#include "opt_compat_netbsd.h"
#include "opt_ddb.h"
@ -92,8 +92,9 @@ __KERNEL_RCSID(0, "$NetBSD: obs200_machdep.c,v 1.10 2010/02/25 23:33:44 matt Exp
#include <machine/century_bios.h>
#include <powerpc/spr.h>
#include <powerpc/ibm4xx/spr.h>
#include <powerpc/ibm4xx/dcr405gp.h>
#include <powerpc/ibm4xx/dcr4xx.h>
#include <powerpc/ibm4xx/ibm405gp.h>
#include <powerpc/ibm4xx/dev/comopbvar.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pciconf.h>
@ -127,7 +128,7 @@ initppc(u_int startkernel, u_int endkernel, char *args, void *info_block)
u_int memsize;
/* Disable all external interrupts */
mtdcr(DCR_UIC0_ER, 0);
mtdcr(DCR_UIC0_BASE + DCR_UIC_ER, 0);
pllmode = mfdcr(DCR_CPC0_PLLMR);
psr = mfdcr(DCR_CPC0_PSR);
@ -304,6 +305,17 @@ cpu_reboot(int howto, char *what)
#endif
}
int
pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
{
/*
* Bus number is irrelevant. Configuration Mechanism 1 is in
* use, can have devices 0-32 (i.e. the `normal' range).
*/
return 31;
}
int
pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
{
@ -384,7 +396,6 @@ pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin,
return;
}
*iline = ilinemap[dev - 1];
} else {
} else
*iline = 19 + ((swiz + dev + 1) & 3);
}
}

24
sys/arch/evbppc/obs405/obs266_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: obs266_machdep.c,v 1.11 2010/02/25 23:33:44 matt Exp $ */
/* $NetBSD: obs266_machdep.c,v 1.12 2010/03/18 13:47:04 kiyohara Exp $ */
/* Original: md_machdep.c,v 1.3 2005/01/24 18:47:37 shige Exp $ */
/*
@ -68,7 +68,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: obs266_machdep.c,v 1.11 2010/02/25 23:33:44 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: obs266_machdep.c,v 1.12 2010/03/18 13:47:04 kiyohara Exp $");
#include "opt_compat_netbsd.h"
#include "opt_ddb.h"
@ -90,9 +90,11 @@ __KERNEL_RCSID(0, "$NetBSD: obs266_machdep.c,v 1.11 2010/02/25 23:33:44 matt Exp
#include <machine/cpu.h>
#include <machine/obs266.h>
#include <powerpc/spr.h>
#include <powerpc/ibm4xx/spr.h>
#include <powerpc/ibm4xx/dcr405gp.h>
#include <powerpc/ibm4xx/dcr4xx.h>
#include <powerpc/ibm4xx/dev/comopbvar.h>
#include <powerpc/ibm4xx/ibm405gp.h>
#include <powerpc/ibm4xx/openbios.h>
#include <powerpc/ibm4xx/spr.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pciconf.h>
@ -123,9 +125,6 @@ initppc(u_int startkernel, u_int endkernel, char *args, void *info_block)
vaddr_t va;
u_int memsize;
/* Disable all external interrupts */
mtdcr(DCR_UIC0_ER, 0);
/* Setup board from OpenBIOS */
openbios_board_init(info_block, startkernel);
memsize = openbios_board_memsize_get();
@ -297,6 +296,17 @@ cpu_reboot(int howto, char *what)
#endif
}
int
pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
{
/*
* Bus number is irrelevant. Configuration Mechanism 1 is in
* use, can have devices 0-32 (i.e. the `normal' range).
*/
return 31;
}
int
pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
{

281
sys/arch/evbppc/walnut/pci/pci_machdep.c
View File

@ -1,281 +0,0 @@
/* $NetBSD: pci_machdep.c,v 1.8 2008/05/30 19:26:35 ad Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
* Copyright (c) 1994 Charles M. Hannum. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Charles M. Hannum.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Machine-specific functions for PCI autoconfiguration.
*
* On PCs, there are two methods of generating PCI configuration cycles.
* We try to detect the appropriate mechanism for this machine and set
* up a few function pointers to access the correct method directly.
*
* The configuration method can be hard-coded in the config file by
* using `options PCI_CONF_MODE=N', where `N' is the configuration mode
* as defined section 3.6.4.1, `Generating Configuration Cycles'.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.8 2008/05/30 19:26:35 ad Exp $");
#include <sys/types.h>
#include <sys/param.h>
#include <sys/time.h>
#include <sys/systm.h>
#include <sys/errno.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <uvm/uvm_extern.h>
#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcidevs.h>
#include <dev/pci/pciconf.h>
#include <powerpc/ibm4xx/ibm405gp.h>
#include <powerpc/ibm4xx/dev/pcicreg.h>
static struct powerpc_bus_space pci_iot = {
_BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_MEM_TYPE,
0x00000000,
IBM405GP_PCIC0_BASE, /* extent base */
IBM405GP_PCIC0_BASE + 8, /* extent limit */
};
static bus_space_handle_t pci_ioh;
void
pci_machdep_init(void)
{
if (pci_ioh == 0 &&
(bus_space_init(&pci_iot, "pcicfg", NULL, 0) ||
bus_space_map(&pci_iot, IBM405GP_PCIC0_BASE, 8, 0, &pci_ioh)))
panic("Cannot map PCI registers");
}
void
pci_attach_hook(struct device *parent, struct device *self,
struct pcibus_attach_args *pba)
{
#ifdef PCI_CONFIGURE_VERBOSE
printf("pci_attach_hook\n");
ibm4xx_show_pci_map();
#endif
ibm4xx_setup_pci();
#ifdef PCI_CONFIGURE_VERBOSE
ibm4xx_show_pci_map();
#endif
}
int
pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
{
/*
* Bus number is irrelevant. Configuration Mechanism 1 is in
* use, can have devices 0-32 (i.e. the `normal' range).
*/
return 5;
}
pcitag_t
pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function)
{
pcitag_t tag;
if (bus >= 256 || device >= 32 || function >= 8)
panic("pci_make_tag: bad request");
/* XXX magic number */
tag = 0x80000000 | (bus << 16) | (device << 11) | (function << 8);
return tag;
}
void
pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp)
{
if (bp != NULL)
*bp = (tag >> 16) & 0xff;
if (dp != NULL)
*dp = (tag >> 11) & 0x1f;
if (fp != NULL)
*fp = (tag >> 8) & 0x07;
}
pcireg_t
pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
{
pcireg_t data;
/* 405GT BIOS disables interrupts here. Should we? --Art */
bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, tag | reg);
data = bus_space_read_4(&pci_iot, pci_ioh, PCIC_CFGDATA);
/* 405GP pass2 errata #6 */
bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, 0);
return data;
}
void
pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
{
bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, tag | reg);
bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGDATA, data);
/* 405GP pass2 errata #6 */
bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, 0);
}
int
pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
{
int pin = pa->pa_intrpin;
int dev = pa->pa_device;
if (pin == 0) {
/* No IRQ used. */
goto bad;
}
if (pin > 4) {
printf("pci_intr_map: bad interrupt pin %d\n", pin);
goto bad;
}
/*
* We need to map the interrupt pin to the interrupt bit in the UIC
* associated with it. This is highly machine-dependent.
*/
switch(dev) {
case 1:
case 2:
case 3:
case 4:
*ihp = 27 + dev;
break;
default:
printf("Hmm.. PCI device %d should not exist on this board\n",
dev);
goto bad;
}
return 0;
bad:
*ihp = -1;
return 1;
}
const char *
pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
{
static char irqstr[8]; /* 4 + 2 + NUL + sanity */
/* Make sure it looks sane, intr_establish does the real check. */
if (ih < 0 || ih > 99)
panic("pci_intr_string: handle %d won't fit two digits", ih);
sprintf(irqstr, "irq %d", ih);
return (irqstr);
}
const struct evcnt *
pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih)
{
/* XXX for now, no evcnt parent reported */
return NULL;
}
int
pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih,
int attr, uint64_t data)
{
switch (attr) {
case PCI_INTR_MPSAFE:
return 0;
default:
return ENODEV;
}
}
void *
pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
int (*func)(void *), void *arg)
{
return intr_establish(ih, IST_LEVEL, level, func, arg);
}
void
pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
{
intr_disestablish(cookie);
}
void
pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin,
int swiz, int *iline)
{
if (bus == 0) {
switch(dev) {
case 1:
case 2:
case 3:
case 4:
*iline = 31 - dev;
}
} else {
*iline = 20 + ((swiz + dev + 1) & 3);
}
}
/* Avoid overconfiguration */
int
pci_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, pcireg_t id)
{
if ((PCI_VENDOR(id) == PCI_VENDOR_IBM && PCI_PRODUCT(id) == PCI_PRODUCT_IBM_405GP) ||
(PCI_VENDOR(id) == PCI_VENDOR_INTEL && PCI_PRODUCT(id) == PCI_PRODUCT_INTEL_80960_RP)) {
/* Don't configure the bridge and PCI probe. */
return 0;
}
return PCI_CONF_DEFAULT;
}

21
sys/arch/powerpc/conf/files.ibm405gp
View File

@ -1,21 +0,0 @@
# $NetBSD: files.ibm405gp,v 1.8 2008/02/20 21:43:35 drochner Exp $
#
# IBM 405GPx specific configuration info
# Machine-independent I2O drivers.
include "dev/i2o/files.i2o"
# PCI bus support
include "dev/pci/files.pci"
# On-chip PCI bridge
device pchb : pcibus
attach pchb at plb
file arch/powerpc/ibm4xx/pci/pchb.c pchb
file arch/powerpc/ibm4xx/pci/pci_machdep.c pci
file arch/powerpc/ibm4xx/dev/ibm405gp.c
# On-chip IIC controller
device gpiic: i2cbus, i2c_bitbang
attach gpiic at opb
file arch/powerpc/ibm4xx/dev/gpiic_opb.c gpiic

19
sys/arch/powerpc/ibm4xx/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.27 2009/03/18 10:22:34 cegger Exp $ */
/* $NetBSD: cpu.c,v 1.28 2010/03/18 13:47:05 kiyohara Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.27 2009/03/18 10:22:34 cegger Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.28 2010/03/18 13:47:05 kiyohara Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -68,6 +68,7 @@ static struct cputab models[] = {
{ PVR_405GPR, 0xffff0000, "405GPr" },
{ PVR_405D5X1, 0xfffff000, "Xilinx Virtex II Pro" },
{ PVR_405D5X2, 0xfffff000, "Xilinx Virtex 4 FX" },
{ PVR_405EX, 0xffff0000, "405EX" },
{ 0, 0, NULL }
};
@ -164,12 +165,22 @@ cpuattach(struct device *parent, struct device *self, void *aux)
void
cpu_probe_cache(void)
{
struct cputab *cp = models;
u_int pvr;
pvr = mfpvr();
while (cp->name) {
if ((pvr & cp->mask) == cp->version)
break;
cp++;
}
/*
* First we need to identify the CPU and determine the
* cache line size, or things like memset/memcpy may lose
* badly.
*/
switch (mfpvr() & 0xffff0000) {
switch (cp->version) {
case PVR_401A1:
curcpu()->ci_ci.dcache_size = 1024;
curcpu()->ci_ci.dcache_line_size = 16;
@ -227,6 +238,7 @@ cpu_probe_cache(void)
case PVR_405GPR:
case PVR_405D5X1:
case PVR_405D5X2:
case PVR_405EX:
curcpu()->ci_ci.dcache_size = 16384;
curcpu()->ci_ci.dcache_line_size = 32;
curcpu()->ci_ci.icache_size = 16384;
@ -242,7 +254,6 @@ cpu_probe_cache(void)
curcpu()->ci_ci.icache_line_size = 4;
break;
}
}
/*

6
sys/arch/powerpc/ibm4xx/dev/ecc_plb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ecc_plb.c,v 1.11 2006/05/05 18:04:42 thorpej Exp $ */
/* $NetBSD: ecc_plb.c,v 1.12 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ecc_plb.c,v 1.11 2006/05/05 18:04:42 thorpej Exp $");
__KERNEL_RCSID(0, "$NetBSD: ecc_plb.c,v 1.12 2010/03/18 13:47:04 kiyohara Exp $");
#include "locators.h"
@ -47,7 +47,7 @@ __KERNEL_RCSID(0, "$NetBSD: ecc_plb.c,v 1.11 2006/05/05 18:04:42 thorpej Exp $")
#include <prop/proplib.h>
#include <machine/cpu.h>
#include <powerpc/ibm4xx/dcr405gp.h>
#include <powerpc/ibm4xx/dcr4xx.h>
#include <powerpc/ibm4xx/dev/plbvar.h>

130
sys/arch/powerpc/ibm4xx/dev/emacreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: emacreg.h,v 1.2 2006/10/16 18:14:35 kiyohara Exp $ */
/* $NetBSD: emacreg.h,v 1.3 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -38,8 +38,11 @@
#ifndef _IBM4XX_EMACREG_H_
#define _IBM4XX_EMACREG_H_
#define EMAC_MAX_MTU 9022
/* Number of Ethernet MAC Registers */
#define EMAC_NREG 0x70
#define EMAC_NREG 0x100
/* Ethernet MAC Registers */
#define EMAC_MR0 0x00 /* Mode Register 0 */
@ -60,14 +63,21 @@
#define MR1_MF_MASK 0x00c00000 /* Medium Frequency mask */
#define MR1_MF_10MBS 0x00000000 /* 10MB/sec */
#define MR1_MF_100MBS 0x00400000 /* 100MB/sec */
#define MR1_RFS_MASK 0x00300000 /* Receive FIFO size */
#define MR1_RFS_512 0x00000000 /* 512 bytes */
#define MR1_RFS_1KB 0x00100000 /* 1kByte */
#define MR1_RFS_2KB 0x00200000 /* 2kByte */
#define MR1_RFS_4KB 0x00300000 /* 4kByte */
#define MR1_TFS_MASK 0x000c0000 /* Transmit FIFO size */
#define MR1_TFS_1KB 0x00040000 /* 1kByte */
#define MR1_TFS_2KB 0x00080000 /* 2kByte */
#define MR1_MF_1000MBS 0x00800000 /* 1000MB/sec */
#define MR1_RFS(fs) /* Receive FIFO size */ \
(((fs) << 20) & 0x00300000)
#define MR1_TFS(fs) /* Transmit FIFO size */ \
(((fs) << 18) & 0x000c0000)
#define MR1_RFS_GBE(fs) /* GbE's Receive FIFO size */ \
(((fs) << 19) & 0x00380000)
#define MR1_TFS_GBE(fs) /* GbE's Transmit FIFO size */ \
(((fs) << 16) & 0x00070000)
#define MR1__FS_512 0
#define MR1__FS_1KB 1
#define MR1__FS_2KB 2
#define MR1__FS_4KB 3
#define MR1__FS_8KB 4
#define MR1__FS_16KB 5
#define MR1_TR0_MASK 0x00018000 /* Transmit Request 0 */
#define MR1_TR0_SINGLE 0x00000000 /* Single Packet mode */
#define MR1_TR0_MULTIPLE 0x00008000 /* Multiple Packet mode */
@ -76,6 +86,12 @@
#define MR1_TR1_SINGLE 0x00000000 /* Single Packet mode */
#define MR1_TR1_MULTIPLE 0x00002000 /* Multiply Packet mode */
#define MR1_TR1_DEPENDANT 0x00004000 /* Dependent Mode */
#define MR1_MWSW_MASK 0x00007000 /* Maximum Waiting Status Words (GbE) */
#define MR1_MWSW_SHIFT 12
#define MR1_JPSM 0x00000800 /* Jumbo Packet Support Mode (GbE) */
#define MR1_IPPA_MASK 0x000007c0 /* Internal PCS PHY Address (GbE) */
#define MR1_IPPA_SHIFT 6
#define MR1_OBCI(opbc) ((opbc) << 3) /* OPB Bus Clock Indication (GbE) */
#define EMAC_TMR0 0x08 /* Transmit Mode Register 0 */
#define TMR0_GNP0 0x80000000 /* Get New Packet for Channel 0 */
@ -84,6 +100,14 @@
#define TMR0_FC_MASK 0x10000000 /* First Channel */
#define TMR0_FC_CHAN0 0x00000000 /* Channel 0 */
#define TMR0_FC_CHAN1 0x10000000 /* Channel 1 */
#define TMR0_TFAE_MASK 0x00000007 /* TX FIFO Almost Empty */
#define TMR0_TFAE_2 0x00000001 /* Number of used entries <= 2(32B) */
#define TMR0_TFAE_4 0x00000002 /* Number of used entries <= 4(64B) */
#define TMR0_TFAE_8 0x00000003 /* Number of used entries <= 8(128B) */
#define TMR0_TFAE_16 0x00000004 /* Number of used entries <= 16(256B) */
#define TMR0_TFAE_32 0x00000005 /* Number of used entries <= 32(512B) */
#define TMR0_TFAE_64 0x00000006 /* Number of used entries <= 64(1024B) */
#define TMR0_TFAE_128 0x00000007 /* Number of used entries <= 128(2048B) */
#define EMAC_TMR1 0x0c /* Transmit Mode Register 1 */
#define TMR1_TLR_MASK 0xf8000000 /* Transmit Low Request */
@ -105,8 +129,21 @@
#define RMR_MIAE 0x00200000 /* Multiple Individual Address Enable */
#define RMR_BAE 0x00100000 /* Broadcast Address Enable */
#define RMR_MAE 0x00080000 /* Multicast Address Enable */
#define RMR_NIPMAE 0x00040000 /* Non-IP Multicast Address Enable */
#define RMR_RFAF_MASK 0x00000007 /* RX FIFO Almost Full - IRQ threshold */
#define RMR_TFAE_2 0x00000001 /* Number of used entries <= 2(32B) */
#define RMR_TFAE_4 0x00000002 /* Number of used entries <= 4(64B) */
#define RMR_TFAE_8 0x00000003 /* Number of used entries <= 8(128B) */
#define RMR_TFAE_16 0x00000004 /* Number of used entries <= 16(256B) */
#define RMR_TFAE_32 0x00000005 /* Number of used entries <= 32(512B) */
#define RMR_TFAE_64 0x00000006 /* Number of used entries <= 64(1024B) */
#define RMR_TFAE_128 0x00000007 /* Number of used entries <= 128(2048B) */
#define EMAC_ISR 0x14 /* Interrupt Status Register */
#define ISR_TXPE 0x20000000 /* TX Parity Error */
#define ISR_RXPE 0x10000000 /* RX Parity Error */
#define ISR_TXUE 0x08000000 /* TX Underrun Event */
#define ISR_RXOE 0x04000000 /* RX Overrun Event */
#define ISR_OVR 0x02000000 /* Overrun Error */
#define ISR_PP 0x01000000 /* Pause Packet */
#define ISR_BP 0x00800000 /* Bad Packet */
@ -119,15 +156,27 @@
#define ISR_IRE 0x00010000 /* In Range Error */
#define ISR_DBDM 0x00000200 /* Dead Bit Dependent Mode */
#define ISR_DB0 0x00000100 /* Dead Bit 0 */
#define ISR_SE0 0x00000080 /* SQE Error 0 */
#define ISR_SE0 0x00000080 /* Signal Quality Error 0 (SQE) */
#define ISR_TE0 0x00000040 /* Transmit Error 0 */
#define ISR_DB1 0x00000020 /* Dead Bit 1 */
#define ISR_SE1 0x00000010 /* SQE Error 1 */
#define ISR_SE1 0x00000010 /* Signal Quality Error 1 */
#define ISR_TE1 0x00000008 /* Transmit Error 1 */
#define ISR_MOS 0x00000002 /* MMA Operation Succeeded */
#define ISR_MOF 0x00000001 /* MMA Operation Failed */
#define ISR_ALL ( ISR_TXPE| ISR_RXPE| \
ISR_TXUE| ISR_RXOE| ISR_OVR | ISR_PP | \
ISR_BP | ISR_RP | ISR_SE | ISR_ALE | \
ISR_BFCS| ISR_PTLE| ISR_ORE | ISR_IRE | \
ISR_DBDM| ISR_DB0 | \
ISR_SE0 | ISR_TE0 | ISR_DB1 | ISR_SE1 | \
ISR_TE1 | ISR_MOS | ISR_MOF)
#define EMAC_ISER 0x18 /* Interrupt Status Enable Register */
#define ISER_TXPE ISR_TXPE
#define ISER_RXPE ISR_RXPE
#define ISER_TXUE ISR_TXUE
#define ISER_RXOE ISR_RXOE
#define ISER_OVR ISR_OVR
#define ISER_PP ISR_PP
#define ISER_BP ISR_BP
@ -153,34 +202,37 @@
#define EMAC_VTPID 0x24 /* VLAN TPID Register */
#define EMAC_VTCI 0x28 /* VLAN TCI Register */
#define EMAC_PTR 0x2c /* Pause Timer Register */
#define EMAC_IAHT1 0x30 /* Individual Address Hash Table 1 */
#define EMAC_IAHT2 0x34 /* Individual Address Hash Table 2 */
#define EMAC_IAHT3 0x38 /* Individual Address Hash Table 3 */
#define EMAC_IAHT4 0x3c /* Individual Address Hash Table 4 */
#define EMAC_GAHT1 0x40 /* Group Address Hash Table 1 */
#define EMAC_GAHT2 0x44 /* Group Address Hash Table 2 */
#define EMAC_GAHT3 0x48 /* Group Address Hash Table 3 */
#define EMAC_GAHT4 0x4c /* Group Address Hash Table 4 */
#define EMAC_NHT64 4
#define EMAC_IAHT64(n) 0x30 /* 64b Individual Address Hash Table */
#define EMAC_GAHT64(n) 0x40 /* 64b Group Address Hash Table */
#define EMAC_LSAH 0x50 /* Last Source Address High */
#define EMAC_LSAL 0x54 /* Last Source Address Low */
#define EMAC_IPGVR 0x58 /* Inter-Packet Gap Value Register */
#define EMAC_STACR 0x5c /* STA Control Register */
#define STACR_PHYD 0xffff0000 /* PHY data mask */
#define STACR_PHYDSHIFT 16
#define STACR_PHYD_SHIFT 16
#define STACR_OC 0x00008000 /* operation complete */
#define STACR_PHYE 0x00004000 /* PHY error */
#define STACR_WRITE 0x00002000 /* STA command - write */
#define STACR_READ 0x00001000 /* STA command - read */
#define STACR_OPBC_MASK 0x00000c00 /* OPB bus clock freq mask */
#define STACR_OPBC_50MHZ 0x00000000 /* OPB bus clock freq - 50MHz */
#define STACR_OPBC_66MHZ 0x00000400 /* OPB bus clock freq - 66MHz */
#define STACR_OPBC_83MHZ 0x00000800 /* OPB bus clock freq - 83MHz */
#define STACR_OPBC_100MHZ 0x00000c00 /* OPB bus clock freq - 100MHz */
#define STACR_OPBC_50MHZ 0x0 /* - 50MHz */
#define STACR_OPBC_66MHZ 0x1 /* - 66MHz */
#define STACR_OPBC_83MHZ 0x2 /* - 83MHz */
#define STACR_OPBC_100MHZ 0x3 /* - 100MHz */
#define STACR_OPBC_A100MHZ 0x4 /* - Abobe 100MHz (GbE) */
#define STACR_OPBC(opbc) ((opbc) << 10) /* OPB bus clock freq (!GbE)*/
#define STACR_PCDA 0x000003e0 /* PHY cmd dest address mask */
#define STACR_PCDASHIFT 5
#define STACR_PCDA_SHIFT 5
#define STACR_PRA 0x0000001f /* PHY register address mask */
#define STACR_PRASHIFT 0
#define STACR_PRA_SHIFT 0
#define STACR_IMS 0x00002000 /* Indirect Mode Selection (405EX/440SPe) */
#define STACR_STAOPC_MASK 0x00001800 /* STA Opcode (405EX/440SPe) */
#define STACR_STAOPC_ADDRESS 0x00000000 /* (IMS=1) Address */
#define STACR_STAOPC_WRITE 0x00000800 /* Write */
#define STACR_STAOPC_READ 0x00001000 /* Read */
#define STACR_STAOPC_READINC 0x00001800 /* (IMS=1) Read Inc. */
#define EMAC_TRTR 0x60 /* Transmit Request Threshold Register */
#define TRTR_64 0x00000000 /* 64 bytes */
@ -198,4 +250,26 @@
#define EMAC_OCTX 0x68 /* Number of Octets Transmitted */
#define EMAC_OCRX 0x6c /* Number of Octets Received */
#define EMAC_IPCR 0x70 /* Internal PCS Configuration Register */
#define IPCR_OUI_MASK 0xfffffc00 /* OUI Value */
#define IPCR_OUI_SHIFT 10
#define IPCR_MMN_MASK 0x000003f0 /* Manufacture Model Number */
#define IPCR_MMN_SHIFT 4
#define IPCR_REVID_MASK 0x0000000f /* Revision Number */
#define IPCR_REVID_SHIFT 0
#define EMAC_REVID 0x74 /* Revision ID Register */
#define REVID_REVISION(v) (((v) >> 8) & 0xfff) /* Revision */
#define REVID_BRANCHREV(v) ((v) & 0xff) /* Branch Revision */
#define EMAC_NHT256 8
#define EMAC_IAHT256(n) 0x80 /* 256b Individual Address Hash Table */
#define EMAC_GAHT256(n) 0xa0 /* 256b Group Address Hash Table */
#define EMAC_TPC 0xc0 /* Transmit Pause Control Register */
#define TPC_IPA 0x80000000 /* Issue a Pause Packet */
#define TPC_TV_MASK 0x7fff8000 /* Timer Value */
#define TPC_TV_SHIFT 15
#endif /* _IBM4XX_EMACREG_H_ */

3
sys/arch/powerpc/ibm4xx/dev/gpio_opb.c
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@ -1,4 +1,4 @@
/* $NetBSD: gpio_opb.c,v 1.6 2007/02/06 04:48:15 simonb Exp $ */
/* $NetBSD: gpio_opb.c,v 1.7 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright (c) 2004 Shigeyuki Fukushima.
@ -41,7 +41,6 @@
#include <sys/gpio.h>
#include <dev/gpio/gpiovar.h>
#include <powerpc/ibm4xx/dcr405gp.h>
#include <powerpc/ibm4xx/dev/opbvar.h>
#include <powerpc/ibm4xx/dev/gpioreg.h>

1184
sys/arch/powerpc/ibm4xx/dev/if_emac.c
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File diff suppressed because it is too large Load Diff

32
sys/arch/powerpc/ibm4xx/dev/if_emacvar.h Normal file
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@ -0,0 +1,32 @@
/* $NetBSD: if_emacvar.h,v 1.1 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright (c) 2010 KIYOHARA Takashi
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
int emac_txeob_intr(void *);
int emac_rxeob_intr(void *);
int emac_txde_intr(void *);
int emac_rxde_intr(void *);

295
sys/arch/powerpc/ibm4xx/dev/mal.c Normal file
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@ -0,0 +1,295 @@
/* $NetBSD: mal.c,v 1.1 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright (c) 2010 KIYOHARA Takashi
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mal.c,v 1.1 2010/03/18 13:47:04 kiyohara Exp $");
#include <sys/param.h>
#include <sys/device.h>
#include <machine/intr.h>
#include <powerpc/cpu.h>
#include <powerpc/ibm4xx/dcr4xx.h>
#include <powerpc/ibm4xx/dev/if_emacvar.h>
#include <powerpc/ibm4xx/dev/malvar.h>
#include <powerpc/ibm4xx/spr.h>
#define STAT_TO_CHAN(stat) cntlzw(stat)
static int mal_txeob_intr(void *);
static int mal_rxeob_intr(void *);
static int mal_txde_intr(void *);
static int mal_rxde_intr(void *);
static int mal_serr_intr(void *);
const static struct maltbl {
int pvr;
int intrs[5];
int flags;
#define MAL_GEN2 (1<<0) /* Generation 2 (405EX/EXr/440GP/GX/SP/SPe) */
} maltbl[] = { /* TXEOB RXEOB TXDE RXDE SERR */
{ IBM405GP, { 11, 12, 13, 14, 10 }, 0 },
{ IBM405GPR, { 11, 12, 13, 14, 10 }, 0 },
{ AMCC405EX, { 10, 11, 32+ 1, 32+ 2, 32+ 0 }, MAL_GEN2 },
};
/* Max channel is 4 on 440GX. Others is 2 or 1. */
static void *iargs[4];
void
mal_attach(int pvr)
{
int i, to;
for (i = 0; i < __arraycount(maltbl); i++)
if (maltbl[i].pvr == pvr)
break;
if (i == __arraycount(maltbl)) {
aprint_error("%s: unknwon pvr 0x%x\n", __func__, pvr);
return;
}
/*
* Reset MAL.
* We wait for the completion of reset in maximums for five seconds.
*/
mtdcr(DCR_MAL0_CFG, MAL0_CFG_SR);
to = 0;
while (mfdcr(DCR_MAL0_CFG) & MAL0_CFG_SR) {
if (to > 5000) {
aprint_error("%s: Soft reset failed\n", __func__);
return;
}
delay(1000); /* delay 1m sec */
to++;
}
/* establish MAL interrupts */
intr_establish(maltbl[i].intrs[0], IST_LEVEL, IPL_NET,
mal_txeob_intr, NULL);
intr_establish(maltbl[i].intrs[1], IST_LEVEL, IPL_NET,
mal_rxeob_intr, NULL);
intr_establish(maltbl[i].intrs[2], IST_LEVEL, IPL_NET,
mal_txde_intr, NULL);
intr_establish(maltbl[i].intrs[3], IST_LEVEL, IPL_NET,
mal_rxde_intr, NULL);
intr_establish(maltbl[i].intrs[4], IST_LEVEL, IPL_NET,
mal_serr_intr, NULL);
/* Set the MAL configuration register */
if (maltbl[i].flags & MAL_GEN2)
mtdcr(DCR_MAL0_CFG,
MAL0_CFG_RMBS_32 |
MAL0_CFG_WMBS_32 |
MAL0_CFG_PLBLT |
MAL0_CFG_EOPIE |
MAL0_CFG_PLBB |
MAL0_CFG_OPBBL |
MAL0_CFG_LEA |
MAL0_CFG_SD);
else
mtdcr(DCR_MAL0_CFG,
MAL0_CFG_PLBLT |
MAL0_CFG_PLBB |
MAL0_CFG_OPBBL |
MAL0_CFG_LEA |
MAL0_CFG_SD);
/* Enable MAL SERR Interrupt */
mtdcr(DCR_MAL0_IER,
MAL0_IER_PT |
MAL0_IER_PRE |
MAL0_IER_PWE |
MAL0_IER_DE |
MAL0_IER_NWE |
MAL0_IER_TO |
MAL0_IER_OPB |
MAL0_IER_PLB);
}
static int
mal_txeob_intr(void *arg)
{
uint32_t tcei;
int chan, handled = 0;
while ((tcei = mfdcr(DCR_MAL0_TXEOBISR))) {
chan = STAT_TO_CHAN(tcei);
if (iargs[chan] != NULL) {
mtdcr(DCR_MAL0_TXEOBISR, MAL0__XCAR_CHAN(chan));
handled |= emac_txeob_intr(iargs[chan]);
}
}
return handled;
}
static int
mal_rxeob_intr(void *arg)
{
uint32_t rcei;
int chan, handled = 0;
while ((rcei = mfdcr(DCR_MAL0_RXEOBISR))) {
chan = STAT_TO_CHAN(rcei);
if (iargs[chan] != NULL) {
/* Clear the interrupt */
mtdcr(DCR_MAL0_RXEOBISR, MAL0__XCAR_CHAN(chan));
handled |= emac_rxeob_intr(iargs[chan]);
}
}
return handled;
}
static int
mal_txde_intr(void *arg)
{
uint32_t txde;
int chan, handled = 0;
while ((txde = mfdcr(DCR_MAL0_TXDEIR))) {
chan = STAT_TO_CHAN(txde);
if (iargs[chan] != NULL) {
handled |= emac_txde_intr(iargs[chan]);
/* Clear the interrupt */
mtdcr(DCR_MAL0_TXDEIR, MAL0__XCAR_CHAN(chan));
}
}
return handled;
}
static int
mal_rxde_intr(void *arg)
{
uint32_t rxde;
int chan, handled = 0;
while ((rxde = mfdcr(DCR_MAL0_RXDEIR))) {
chan = STAT_TO_CHAN(rxde);
if (iargs[chan] != NULL) {
handled |= emac_rxde_intr(iargs[chan]);
/* Clear the interrupt */
mtdcr(DCR_MAL0_RXDEIR, MAL0__XCAR_CHAN(chan));
/* Reenable the receive channel */
mtdcr(DCR_MAL0_RXCASR, MAL0__XCAR_CHAN(chan));
}
}
return handled;
}
static int
mal_serr_intr(void *arg)
{
uint32_t esr;
esr = mfdcr(DCR_MAL0_ESR);
/* not yet... */
aprint_error("MAL SERR: ESR 0x%08x\n", esr);
/* Clear the interrupt status bits. */
mtdcr(DCR_MAL0_ESR, esr);
return 1;
}
void
mal_intr_establish(int chan, void *arg)
{
if (chan >= __arraycount(iargs))
panic("MAL channel %d not support (max %d)\n",
chan, __arraycount(iargs));
iargs[chan] = arg;
}
int
mal_start(int chan, uint32_t cdtxaddr, uint32_t cdrxaddr)
{
/*
* Give the transmit and receive rings to the MAL.
* And set the receive channel buffer size (in units of 16 bytes).
*/
#if MCLBYTES > (4096 - 16) /* XXX! */
# error MCLBYTES > max rx channel buffer size
#endif
/* The mtdcr() allows only the constant in the first argument... */
switch (chan) {
case 0:
mtdcr(DCR_MAL0_TXCTP0R, cdtxaddr);
mtdcr(DCR_MAL0_RXCTP0R, cdrxaddr);
mtdcr(DCR_MAL0_RCBS0, MCLBYTES / 16);
break;
case 1:
mtdcr(DCR_MAL0_TXCTP1R, cdtxaddr);
mtdcr(DCR_MAL0_RXCTP1R, cdrxaddr);
mtdcr(DCR_MAL0_RCBS1, MCLBYTES / 16);
break;
case 2:
mtdcr(DCR_MAL0_TXCTP2R, cdtxaddr);
mtdcr(DCR_MAL0_RXCTP2R, cdrxaddr);
mtdcr(DCR_MAL0_RCBS2, MCLBYTES / 16);
break;
case 3:
mtdcr(DCR_MAL0_TXCTP3R, cdtxaddr);
mtdcr(DCR_MAL0_RXCTP3R, cdrxaddr);
mtdcr(DCR_MAL0_RCBS3, MCLBYTES / 16);
break;
default:
aprint_error("MAL unknown channel no.%d\n", chan);
return EINVAL;
}
/* Enable the transmit and receive channel on the MAL. */
mtdcr(DCR_MAL0_RXCASR, MAL0__XCAR_CHAN(chan));
mtdcr(DCR_MAL0_TXCASR, MAL0__XCAR_CHAN(chan));
return 0;
}
void
mal_stop(int chan)
{
/* Disable the receive and transmit channels. */
mtdcr(DCR_MAL0_RXCARR, MAL0__XCAR_CHAN(chan));
mtdcr(DCR_MAL0_TXCARR, MAL0__XCAR_CHAN(chan));
}

32
sys/arch/powerpc/ibm4xx/dev/malvar.h Normal file
View File

@ -0,0 +1,32 @@
/* $NetBSD: malvar.h,v 1.1 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright (c) 2010 KIYOHARA Takashi
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
void mal_attach(int);
void mal_intr_establish(int, void *);
int mal_start(int, uint32_t, uint32_t);
void mal_stop(int);

191
sys/arch/powerpc/ibm4xx/dev/opb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: opb.c,v 1.24 2010/02/25 23:31:47 matt Exp $ */
/* $NetBSD: opb.c,v 1.25 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright 2001,2002 Wasabi Systems, Inc.
@ -66,23 +66,35 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: opb.c,v 1.24 2010/02/25 23:31:47 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: opb.c,v 1.25 2010/03/18 13:47:04 kiyohara Exp $");
#include "locators.h"
#include "opt_emac.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <powerpc/spr.h>
#include <powerpc/ibm4xx/spr.h>
#include <powerpc/ibm4xx/cpu.h>
#include <powerpc/ibm4xx/dev/opbreg.h>
#include <powerpc/ibm4xx/dev/opbvar.h>
#include <powerpc/ibm4xx/dev/plbvar.h>
#include <powerpc/ibm4xx/dev/rgmiireg.h>
#include <powerpc/ibm4xx/dev/zmiireg.h>
#include <powerpc/ibm4xx/dcr4xx.h>
#include <powerpc/ibm4xx/spr.h>
#include <powerpc/spr.h>
#include <powerpc/ibm4xx/ibm405gp.h>
#include <powerpc/ibm4xx/amcc405ex.h>
static int opb_get_frequency_405gp(void);
static int opb_get_frequency_405ex(void);
/*
* The devices on the On-chip Peripheral Bus to the 405GP CPU.
* The devices on the On-chip Peripheral Bus to the 405GP/EX CPU.
*/
const struct opb_dev {
int pvr;
@ -90,47 +102,79 @@ const struct opb_dev {
bus_addr_t addr;
int instance;
int irq;
int flags;
} opb_devs [] = {
/* IBM405GP */
{ IBM405GP, "com", IBM405GP_UART0_BASE, 0, 0 },
{ IBM405GP, "com", IBM405GP_UART1_BASE, 1, 1 },
{ IBM405GP, "emac", IBM405GP_EMAC0_BASE, 0, 9 }, /* XXX: really irq 9..15 */
{ IBM405GP, "opbgpio", IBM405GP_GPIO0_BASE, 0, -1 },
{ IBM405GP, "gpiic",IBM405GP_IIC0_BASE, 0, 2 },
{ IBM405GP, "wdog", -1, 0, -1 },
{ IBM405GP, "com", IBM405GP_UART0_BASE, 0, 0, 0 },
{ IBM405GP, "com", IBM405GP_UART1_BASE, 1, 1, 0 },
{ IBM405GP, "emac", IBM405GP_EMAC0_BASE, 0, 15, 0 },
{ IBM405GP, "opbgpio", IBM405GP_GPIO0_BASE, 0, -1, 0 },
{ IBM405GP, "gpiic",IBM405GP_IIC0_BASE, 0, 2, 0 },
{ IBM405GP, "wdog", -1, 0, -1, 0 },
/* IBM405GPR */
{ IBM405GPR, "com", IBM405GP_UART0_BASE, 0, 0 },
{ IBM405GPR, "com", IBM405GP_UART1_BASE, 1, 1 },
{ IBM405GPR, "emac", IBM405GP_EMAC0_BASE, 0, 9 }, /* XXX: really irq 9..15 */
{ IBM405GPR, "opbgpio", IBM405GP_GPIO0_BASE, 0, -1 },
{ IBM405GPR, "gpiic",IBM405GP_IIC0_BASE, 0, 2 },
{ IBM405GPR, "wdog", -1, 0, -1 },
{ IBM405GPR, "com", IBM405GP_UART0_BASE, 0, 0, 0 },
{ IBM405GPR, "com", IBM405GP_UART1_BASE, 1, 1, 0 },
{ IBM405GPR, "emac", IBM405GP_EMAC0_BASE, 0, 15, 0 },
{ IBM405GPR, "opbgpio", IBM405GP_GPIO0_BASE, 0, -1, 0 },
{ IBM405GPR, "gpiic",IBM405GP_IIC0_BASE, 0, 2, 0 },
{ IBM405GPR, "wdog", -1, 0, -1, 0 },
/* AMCC405EX */
{ AMCC405EX, "gpt", AMCC405EX_GPT0_BASE, 0, -1, 0 },
{ AMCC405EX, "com", AMCC405EX_UART0_BASE, 0, 26, 0 },
{ AMCC405EX, "com", AMCC405EX_UART1_BASE, 1, 1, 0 },
{ AMCC405EX, "gpiic",AMCC405EX_IIC0_BASE, 0, 2, 0 },
{ AMCC405EX, "gpiic",AMCC405EX_IIC1_BASE, 1, 7, 0 },
{ AMCC405EX, "scp", AMCC405EX_SCP0_BASE, 0, 8, 0 }, /* SPI */
{ AMCC405EX, "opbgpio", AMCC405EX_GPIO0_BASE, -1, -1, 0 },
{ AMCC405EX, "emac", AMCC405EX_EMAC0_BASE, 0, 24,
OPB_FLAGS_EMAC_GBE | OPB_FLAGS_EMAC_STACV2 | OPB_FLAGS_EMAC_HT256 |\
OPB_FLAGS_EMAC_RMII_RGMII },
{ AMCC405EX, "emac", AMCC405EX_EMAC1_BASE, 1, 25,
OPB_FLAGS_EMAC_GBE | OPB_FLAGS_EMAC_STACV2 | OPB_FLAGS_EMAC_HT256 |\
OPB_FLAGS_EMAC_RMII_RGMII },
{ AMCC405EX, "wdog", -1, 0, -1, 0 },
{ 0, NULL }
};
const struct opb_limit {
int (*opb_get_frequency)(void);
const struct opb_param {
int pvr;
bus_addr_t base;
bus_addr_t limit;
} opb_limits[] = {
{ IBM405GP, IBM405GP_UART0_BASE, IBM405GP_UART0_BASE + 0xfff },
{ IBM405GPR, IBM405GP_UART0_BASE, IBM405GP_UART0_BASE + 0xfff },
{ 0, 0, 0 }
int (*opb_get_frequency)(void);
bus_addr_t zmii_base;
bus_addr_t rgmii_base;
} opb_params[] = {
{ IBM405GP,
IBM405GP_IP_BASE, IBM405GP_IP_BASE + OPBREG_SIZE,
opb_get_frequency_405gp,
0, 0 },
{ IBM405GPR,
IBM405GP_IP_BASE, IBM405GP_IP_BASE + OPBREG_SIZE,
opb_get_frequency_405gp,
0, 0 },
{ AMCC405EX,
AMCC405EX_OPB_BASE, AMCC405EX_OPB_BASE + OPBREG_SIZE,
opb_get_frequency_405ex,
0, AMCC405EX_RGMIIB0_BASE},
{ 0 }
};
static int opb_match(struct device *, struct cfdata *, void *);
static void opb_attach(struct device *, struct device *, void *);
static int opb_submatch(struct device *, struct cfdata *,
const int *, void *);
static int opb_match(device_t, cfdata_t, void *);
static void opb_attach(device_t, device_t, void *);
static int opb_submatch(device_t, cfdata_t, const int *, void *);
static int opb_print(void *, const char *);
CFATTACH_DECL(opb, sizeof(struct device),
CFATTACH_DECL_NEW(opb, sizeof(struct opb_softc),
opb_match, opb_attach, NULL, NULL);
static struct powerpc_bus_space opb_tag = {
_BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE,
0x0, IBM405GP_UART0_BASE, 0x1000
0x00000000,
};
static char ex_storage[EXTENT_FIXED_STORAGE_SIZE(8)]
__attribute__((aligned(8)));
@ -140,45 +184,62 @@ static int opb_tag_init_done;
* Probe for the opb; always succeeds.
*/
static int
opb_match(struct device *parent, struct cfdata *cf, void *aux)
opb_match(device_t parent, cfdata_t cf, void *aux)
{
struct opb_attach_args *oaa = aux;
/* match only opb devices */
/* match only opb devices */
if (strcmp(oaa->opb_name, cf->cf_name) != 0)
return (0);
return 0;
return (1);
return 1;
}
static int
opb_submatch(struct device *parent, struct cfdata *cf,
const int *ldesc, void *aux)
opb_submatch(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
{
struct opb_attach_args *oaa = aux;
if (cf->cf_loc[OPBCF_ADDR] != OPBCF_ADDR_DEFAULT &&
cf->cf_loc[OPBCF_ADDR] != oaa->opb_addr)
return (0);
return 0;
return (config_match(parent, cf, aux));
return config_match(parent, cf, aux);
}
/*
* Attach the on-chip peripheral bus.
*/
static void
opb_attach(struct device *parent, struct device *self, void *aux)
opb_attach(device_t parent, device_t self, void *aux)
{
struct opb_softc *sc = device_private(self);
struct plb_attach_args *paa = aux;
struct opb_attach_args oaa;
bus_space_tag_t tag;
int i, pvr;
printf("\n");
aprint_naive("\n");
aprint_normal("\n");
pvr = mfpvr() >> 16;
tag = opb_get_bus_space_tag();
sc->sc_dev = self;
sc->sc_iot = opb_get_bus_space_tag();
for (i = 0; opb_params[i].pvr != 0 && opb_params[i].pvr != pvr; i++)
;
if (opb_params[i].pvr == 0)
panic("opb_get_bus_space_tag: no params for this CPU!");
opb_get_frequency = opb_params[i].opb_get_frequency;
#ifdef EMAC_ZMII_PHY
if (opb_params[i].zmii_base != 0)
bus_space_map(sc->sc_iot, opb_params[i].zmii_base, ZMII0_SIZE,
0, &sc->sc_zmiih);
#endif
#ifdef EMAC_RGMII_PHY
if (opb_params[i].rgmii_base != 0)
bus_space_map(sc->sc_iot, opb_params[i].rgmii_base, RGMII0_SIZE,
0, &sc->sc_rgmiih);
#endif
for (i = 0; opb_devs[i].name != NULL; i++) {
if (opb_devs[i].pvr != pvr)
@ -187,8 +248,9 @@ opb_attach(struct device *parent, struct device *self, void *aux)
oaa.opb_addr = opb_devs[i].addr;
oaa.opb_instance = opb_devs[i].instance;
oaa.opb_irq = opb_devs[i].irq;
oaa.opb_bt = tag;
oaa.opb_bt = sc->sc_iot;
oaa.opb_dmat = paa->plb_dmat;
oaa.opb_flags = opb_devs[i].flags;
(void) config_found_sm_loc(self, "opb", NULL, &oaa, opb_print,
opb_submatch);
@ -208,7 +270,7 @@ opb_print(void *aux, const char *pnp)
if (oaa->opb_irq != OPBCF_IRQ_DEFAULT)
aprint_normal(" irq %d", oaa->opb_irq);
return (UNCONF);
return UNCONF;
}
bus_space_tag_t
@ -219,13 +281,14 @@ opb_get_bus_space_tag(void)
if (!opb_tag_init_done) {
pvr = mfpvr() >> 16;
for (i = 0; opb_limits[i].pvr && opb_limits[i].pvr != pvr; i++)
for (i = 0; opb_params[i].pvr != 0 && opb_params[i].pvr != pvr;
i++)
;
if (opb_limits[i].pvr == 0)
panic("opb_get_bus_space_tag: no limits for this CPU!");
if (opb_params[i].pvr == 0)
panic("opb_get_bus_space_tag: no params for this CPU!");
opb_tag.pbs_base = opb_limits[i].base;
opb_tag.pbs_limit = opb_limits[i].limit;
opb_tag.pbs_base = opb_params[i].base;
opb_tag.pbs_limit = opb_params[i].limit;
if (bus_space_init(&opb_tag, "opbtag",
ex_storage, sizeof(ex_storage)))
@ -233,5 +296,37 @@ opb_get_bus_space_tag(void)
opb_tag_init_done = 1;
}
return (&opb_tag);
return &opb_tag;
}
static int
opb_get_frequency_405gp(void)
{
prop_number_t pn;
uint32_t pllmr;
unsigned int processor_freq, plb_freq, opb_freq;
pn = prop_dictionary_get(board_properties, "processor-frequency");
KASSERT(pn != NULL);
processor_freq = (unsigned int) prop_number_integer_value(pn);
pllmr = mfdcr(DCR_CPC0_PLLMR);
plb_freq = processor_freq / CPC0_PLLMR_CBDV(pllmr);
opb_freq = plb_freq / CPC0_PLLMR_OPDV(pllmr);
return opb_freq;
}
static int
opb_get_frequency_405ex(void)
{
prop_number_t pn;
unsigned int processor_freq, plb_freq, opb_freq;
pn = prop_dictionary_get(board_properties, "processor-frequency");
KASSERT(pn != NULL);
processor_freq = (unsigned int) prop_number_integer_value(pn);
plb_freq = processor_freq / CPR0_PLBDV0(mfcpr(DCR_CPR0_PLBD));
opb_freq = plb_freq / CPR0_OPBDV0(mfcpr(DCR_CPR0_OPBD));
return opb_freq;
}

39
sys/arch/powerpc/ibm4xx/dev/opbreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: opbreg.h,v 1.1 2002/08/13 04:57:49 simonb Exp $ */
/* $NetBSD: opbreg.h,v 1.2 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -38,7 +38,44 @@
#ifndef _IBM4XX_OPBREG_H_
#define _IBM4XX_OPBREG_H_
#define OPBREG_SIZE 0x1000
/* OPB Arbiter Registers */
#define OPBA_PR 0x00 /* Priority Register */
#define OPBA_CR 0x01 /* Control Register */
/* ZMII Bridge (440EP/440GP/440GX) */
#define ZMII0_SIZE 0x10
#define ZMII0_FER 0x0 /* Function Enable Register */
#define FER_MDI_MASK 0x88880000 /* MDI enable */
#define FER_MDI(emac) (1 << (31 - ((emac) << 2)))
#define FER__MII_MASK 0x7
#define FER__MII_MII 0x1 /* MII Enable */
#define FER__MII_RMII 0x2 /* ZMII (or RMII) Enable */
#define FER__MII_SMII 0x4 /* SMII Enable */
#define FER__MII(emac, mii) ((mii) << (28 - ((emac) << 2)))
#define ZMII0_SSR 0x4 /* Speed Selection Register */
#define SSR_SCI(emac) (0x4 << (28 - ((emac) << 2))) /* Suppress Collision Indication */
#define SSR_FSS(emac) (0x2 << (28 - ((emac) << 2))) /* Force Speed Selection */
#define SSR_SP_10MBPS 0x0
#define SSR_SP_100MBPS 0x2
#define SSR_ZSP(emac, sp) ((sp) << (27 - ((emac) << 2))) /* Speed Selection */
#define ZMII0_SMIISR 0x8 /* SMII Status Register */
#define SMIISR_SHIFT(emac) (24 - ((emac) << 3))
#define SMIISR_MASK 0xff
#define SMIISR_E1 0x01 /* RxD Set to 1 */
#define SMIISR_EC 0x02 /* RxD False Carrier Detected */
#define SMIISR_EN_INVALID 0x00 /* RxD Nibble Invalid */
#define SMIISR_EN_VALID 0x04 /* RxD Nibble Valid */
#define SMIISR_EJ_OK 0x00 /* RxD Jabber OK */
#define SMIISR_EJ_ERROR 0x08 /* RxD Jabber Error */
#define SMIISR_EL_DOWN 0x00 /* RxD Link Down */
#define SMIISR_EL_UP 0x10 /* RxD Link Up */
#define SMIISR_ED_HALF 0x00 /* RxD Duplex Half */
#define SMIISR_ED_FULL 0x20 /* RxD Duplex Full */
#define SMIISR_ES_10 0x00 /* RxD Speed 10MBit */
#define SMIISR_ES_100 0x40 /* RxD Speed 100MBit */
#define SMIISR_EF 0x80 /* RxD from Previous Frame */
#endif /* _IBM4XX_OPBREG_H_ */

17
sys/arch/powerpc/ibm4xx/dev/opbvar.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: opbvar.h,v 1.4 2006/02/21 04:25:29 thorpej Exp $ */
/* $NetBSD: opbvar.h,v 1.5 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -37,6 +37,13 @@
#include <machine/bus.h>
struct opb_softc {
device_t sc_dev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_zmiih;
bus_space_handle_t sc_rgmiih;
};
struct opb_attach_args {
const char *opb_name;
int opb_instance;
@ -44,7 +51,15 @@ struct opb_attach_args {
int opb_irq;
bus_space_tag_t opb_bt; /* Bus space tag */
bus_dma_tag_t opb_dmat; /* DMA tag */
int opb_flags;
#define OPB_FLAGS_EMAC_GBE (1 << 0) /* emac Giga bit Ethernet */
#define OPB_FLAGS_EMAC_STACV2 (1 << 1) /* emac Other version STAC */
#define OPB_FLAGS_EMAC_HT256 (1 << 2) /* emac 256bit Hash Table */
#define OPB_FLAGS_EMAC_RMII_ZMII (1 << 3) /* emac RMII uses ZMII */
#define OPB_FLAGS_EMAC_RMII_RGMII (1 << 4) /* emac RMII uses RGMII */
};
/* For use before opb_attach() is called */
extern bus_space_tag_t opb_get_bus_space_tag(void);
extern int (*opb_get_frequency)(void);

59
sys/arch/powerpc/ibm4xx/dev/plb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: plb.c,v 1.14 2005/12/11 12:18:42 christos Exp $ */
/* $NetBSD: plb.c,v 1.15 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -66,9 +66,10 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: plb.c,v 1.14 2005/12/11 12:18:42 christos Exp $");
__KERNEL_RCSID(0, "$NetBSD: plb.c,v 1.15 2010/03/18 13:47:04 kiyohara Exp $");
#include "locators.h"
#include "emac.h"
#include <sys/param.h>
#include <sys/systm.h>
@ -79,33 +80,48 @@ __KERNEL_RCSID(0, "$NetBSD: plb.c,v 1.14 2005/12/11 12:18:42 christos Exp $");
#define _POWERPC_BUS_DMA_PRIVATE
#include <machine/bus.h>
#include <powerpc/cpu.h>
#include <powerpc/ibm4xx/dev/malvar.h>
#include <powerpc/ibm4xx/dev/plbvar.h>
#include <powerpc/ibm4xx/ibm405gp.h>
#include <powerpc/ibm4xx/spr.h>
/*
* The devices that attach to the processor local bus on the 405GP CPU.
*/
const struct plb_dev plb_devs [] = {
{ "cpu", },
{ "ecc", },
{ "opb", },
{ "pchb", },
{ NULL }
/* IBM 405GP */
{ IBM405GP, "cpu", },
{ IBM405GP, "ecc", },
{ IBM405GP, "opb", },
{ IBM405GP, "pchb", },
/* IBM 405GPr */
{ IBM405GPR, "cpu", },
{ IBM405GPR, "ecc", },
{ IBM405GPR, "opb", },
{ IBM405GPR, "pchb", },
/* AMCC 405EX / EXR */
{ AMCC405EX, "cpu", },
{ AMCC405EX, "ecc", },
{ AMCC405EX, "opb", },
{ AMCC405EX, "pchb", },
{ 0, NULL }
};
static int plb_match(struct device *, struct cfdata *, void *);
static void plb_attach(struct device *, struct device *, void *);
static int plb_print(void *, const char *);
CFATTACH_DECL(plb, sizeof(struct device),
plb_match, plb_attach, NULL, NULL);
CFATTACH_DECL(plb, sizeof(struct device), plb_match, plb_attach, NULL, NULL);
/*
* "generic" DMA struct, nothing special.
*/
struct powerpc_bus_dma_tag ibm4xx_default_bus_dma_tag = {
0, /* _bounce_thresh */
_bus_dmamap_create,
_bus_dmamap_create,
_bus_dmamap_destroy,
_bus_dmamap_load,
_bus_dmamap_load_mbuf,
@ -129,7 +145,7 @@ static int
plb_match(struct device *parent, struct cfdata *cf, void *aux)
{
return (1);
return 1;
}
/*
@ -140,11 +156,21 @@ plb_attach(struct device *parent, struct device *self, void *aux)
{
struct plb_attach_args paa;
struct plb_dev *local_plb_devs = aux;
int i;
int pvr, i;
printf("\n");
aprint_naive("\n");
aprint_normal("\n");
pvr = mfpvr() >> 16;
#if NEMAC > 0
mal_attach(pvr);
#endif
for (i = 0; plb_devs[i].plb_name != NULL; i++) {
if (plb_devs[i].plb_pvr != pvr)
continue;
paa.plb_name = plb_devs[i].plb_name;
paa.plb_dmat = &ibm4xx_default_bus_dma_tag;
paa.plb_irq = PLBCF_IRQ_DEFAULT;
@ -153,6 +179,9 @@ plb_attach(struct device *parent, struct device *self, void *aux)
}
while (local_plb_devs && local_plb_devs->plb_name != NULL) {
if (plb_devs[i].plb_pvr != pvr)
continue;
paa.plb_name = local_plb_devs->plb_name;
paa.plb_dmat = &ibm4xx_default_bus_dma_tag;
paa.plb_irq = PLBCF_IRQ_DEFAULT;
@ -172,5 +201,5 @@ plb_print(void *aux, const char *pnp)
if (paa->plb_irq != PLBCF_IRQ_DEFAULT)
aprint_normal(" irq %d", paa->plb_irq);
return (UNCONF);
return UNCONF;
}

5
sys/arch/powerpc/ibm4xx/dev/plbvar.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: plbvar.h,v 1.4 2005/12/11 12:18:42 christos Exp $ */
/* $NetBSD: plbvar.h,v 1.5 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -38,7 +38,8 @@
#include <machine/bus.h>
struct plb_dev {
const char *plb_name;
int plb_pvr;
const char *plb_name;
};
struct plb_attach_args {

117
sys/arch/powerpc/ibm4xx/dev/rgmii.c Normal file
View File

@ -0,0 +1,117 @@
/* $NetBSD: rgmii.c,v 1.1 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright (c) 2010 KIYOHARA Takashi
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: rgmii.c,v 1.1 2010/03/18 13:47:04 kiyohara Exp $");
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/device.h>
#include <net/if.h>
#include <net/if_media.h>
#include <powerpc/ibm4xx/dev/rgmiireg.h>
#include <powerpc/ibm4xx/dev/rmiivar.h>
#include <powerpc/ibm4xx/dev/opbvar.h>
static void rgmii_enable(device_t, int);
static void rgmii_disable(device_t, int);
static void rgmii_speed(device_t, int, int);
void
rgmii_attach(device_t self, int instance,
void (**enable)(device_t, int),
void (**disable)(device_t, int),
void (**speed)(device_t, int, int))
{
struct opb_softc *sc = device_private(self);
uint32_t ssr;
instance %= 2;
rgmii_disable(self, instance);
ssr = bus_space_read_4(sc->sc_iot, sc->sc_rgmiih, RGMII0_SSR);
ssr &= ~SSR_SP(instance, SSR_SP_MASK);
bus_space_write_4(sc->sc_iot, sc->sc_rgmiih, RGMII0_SSR, ssr);
*enable = rgmii_enable;
*disable = rgmii_disable;
*speed = rgmii_speed;
}
static void
rgmii_enable(device_t self, int instance)
{
struct opb_softc *sc = device_private(self);
uint32_t fer;
instance %= 2;
fer = bus_space_read_4(sc->sc_iot, sc->sc_rgmiih, RGMII0_FER);
fer &= ~FER_MDIOEN_MASK;
fer |= FER_MDIOEN(instance);
bus_space_write_4(sc->sc_iot, sc->sc_rgmiih, RGMII0_FER, fer);
}
static void
rgmii_disable(device_t self, int instance)
{
struct opb_softc *sc = device_private(self);
uint32_t fer;
instance %= 2;
fer = bus_space_read_4(sc->sc_iot, sc->sc_rgmiih, RGMII0_FER);
fer &= ~FER_MDIOEN_MASK;
bus_space_write_4(sc->sc_iot, sc->sc_rgmiih, RGMII0_FER, fer);
}
static void
rgmii_speed(device_t self, int instance, int speed)
{
struct opb_softc *sc = device_private(self);
uint32_t ssr;
instance %= 2;
ssr = bus_space_read_4(sc->sc_iot, sc->sc_rgmiih, RGMII0_SSR);
ssr &= ~SSR_SP(instance, SSR_SP_MASK);
switch (speed) {
case IFM_1000_T:
ssr |= SSR_SP(instance, SSR_SP_1000MBPS);
break;
case IFM_100_TX:
ssr |= SSR_SP(instance, SSR_SP_100MBPS);
break;
case IFM_10_T:
ssr |= SSR_SP(instance, SSR_SP_10MBPS);
break;
}
bus_space_write_4(sc->sc_iot, sc->sc_rgmiih, RGMII0_SSR, ssr);
}

51
sys/arch/powerpc/ibm4xx/dev/rgmiireg.h Normal file
View File

@ -0,0 +1,51 @@
/* $NetBSD: rgmiireg.h,v 1.1 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright (c) 2010 KIYOHARA Takashi
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _IBM4XX_RGMIIREG_H_
#define _IBM4XX_RGMIIREG_H_
/* RGMII (reduced GMII) Bridge (405EX/440GX(EMAC 2, 3)) */
#define RGMII0_SIZE 0x8
#define RGMII0_FER 0x0 /* Function Enable Register */
#define FER_MDIOEN_MASK 0x000c0000 /* MDIO enable */
#define FER_MDIOEN(emac) (1 << ((1 - ((emac) % 2)) + 18))
#define FER_CHCFG_MASK 0x7 /* EMAC n Mask */
#define FER_CHCFG_RTBI 0x4 /* RTBI enabled */
#define FER_CHCFG_RGMII 0x5 /* RGMII enabled */
#define FER_CHCFG_TBI 0x6 /* TBI enabled */
#define FER_CHCFG_GMII 0x7 /* GMII enabled */
#define FER_CHCFG(rgmii, val) ((val) << ((rgmii) << 2))
#define RGMII0_SSR 0x4 /* Speed Select Register */
#define SSR_SP_MASK 0x7
#define SSR_SP_10MBPS 0x0
#define SSR_SP_100MBPS 0x2
#define SSR_SP_1000MBPS 0x4
#define SSR_SP(emac, sp) ((sp) << (((emac) % 2) << 3))
#endif /* _IBM4XX_RGMIIREG_H_ */

32
sys/arch/powerpc/ibm4xx/dev/rmiivar.h Normal file
View File

@ -0,0 +1,32 @@
/* $NetBSD: rmiivar.h,v 1.1 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright (c) 2010 KIYOHARA Takashi
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
void zmii_attach(device_t, int, void (**)(device_t, int),
void (**)(device_t, int), void (**)(device_t, int, int));
void rgmii_attach(device_t, int, void (**)(device_t, int),
void (**)(device_t, int), void (**)(device_t, int, int));

25
sys/arch/powerpc/ibm4xx/ibm4xx_autoconf.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ibm4xx_autoconf.c,v 1.12 2010/01/22 08:56:06 martin Exp $ */
/* $NetBSD: ibm4xx_autoconf.c,v 1.13 2010/03/18 13:47:05 kiyohara Exp $ */
/* Original Tag: ibm4xxgpx_autoconf.c,v 1.2 2004/10/23 17:12:22 thorpej Exp $ */
/*
@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ibm4xx_autoconf.c,v 1.12 2010/01/22 08:56:06 martin Exp $");
__KERNEL_RCSID(0, "$NetBSD: ibm4xx_autoconf.c,v 1.13 2010/03/18 13:47:05 kiyohara Exp $");
#include <sys/param.h>
#include <sys/conf.h>
@ -53,27 +53,34 @@ ibm4xx_device_register(struct device *dev, void *aux)
struct device *parent = device_parent(dev);
if (device_is_a(dev, "emac") && device_is_a(parent, "opb")) {
/* Set the mac-addr of the on-chip Ethernet. */
/* Set the mac-address of the on-chip Ethernet. */
struct opb_attach_args *oaa = aux;
if (oaa->opb_instance < 10) {
prop_dictionary_t dict = device_properties(dev);
prop_data_t pd;
prop_number_t pn;
unsigned char prop_name[15];
snprintf(prop_name, sizeof(prop_name),
"emac%d-mac-addr", oaa->opb_instance);
"emac%d-mac-addr", oaa->opb_instance);
pd = prop_dictionary_get(board_properties, prop_name);
if (pd == NULL) {
printf("WARNING: unable to get mac-addr "
"property from board properties\n");
return;
}
if (prop_dictionary_set(device_properties(dev),
"mac-address", pd) == false) {
printf("WARNING: unable to set mac-addr "
if (prop_dictionary_set(dict, "mac-address", pd) ==
false)
printf("WARNING: unable to set mac-address "
"property for %s\n", dev->dv_xname);
}
snprintf(prop_name, sizeof(prop_name),
"emac%d-mii-phy", oaa->opb_instance);
pn = prop_dictionary_get(board_properties, prop_name);
if (pn != NULL)
prop_dictionary_set_uint32(dict, "mii-phy",
prop_number_integer_value(pn));
}
return;
}

400
sys/arch/powerpc/ibm4xx/intr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: intr.c,v 1.22 2010/02/25 23:31:47 matt Exp $ */
/* $NetBSD: intr.c,v 1.23 2010/03/18 13:47:05 kiyohara Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.22 2010/02/25 23:31:47 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.23 2010/03/18 13:47:05 kiyohara Exp $");
#include <sys/param.h>
#include <sys/malloc.h>
@ -61,7 +61,7 @@ __KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.22 2010/02/25 23:31:47 matt Exp $");
#define ICU_LEN 32
#define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN)
#define IRQ_TO_MASK(irq) (0x80000000UL >> (irq))
#define IRQ_TO_MASK(irq) (0x80000000UL >> ((irq) & 0x1f))
#define IRQ_OF_MASK(mask) cntlzw(mask)
/*
@ -82,39 +82,97 @@ __KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.22 2010/02/25 23:31:47 matt Exp $");
#ifdef PPC_IBM403
#include <powerpc/ibm4xx/dcr403cgx.h>
#define INTR_STATUS DCR_EXISR
#define INTR_ACK DCR_EXISR
#define INTR_ENABLE DCR_EXIER
#elif defined(__virtex__)
#else /* Generic 405/440/460 Universal Interrupt Controller */
#include <evbppc/virtex/dev/xintcreg.h>
#define INTR_STATUS XINTC_ISR
#define INTR_ACK XINTC_IAR
#define INTR_ENABLE XINTC_IER
#define INTR_MASTER XINTC_MER
#define INTR_MASTER_EN (MER_HIE|MER_ME)
#undef IRQ_TO_MASK
#undef IRQ_OF_MASK
#undef IRQ_SOFTNET
#undef IRQ_SOFTCLOCK
#undef IRQ_SOFTSERIAL
#undef IRQ_CLOCK
#undef IRQ_STATCLOCK
#define IRQ_TO_MASK(i) (1 << (i)) /* Redefine mappings */
#define IRQ_OF_MASK(m) (31 - cntlzw(m))
#define IRQ_SOFTNET 31 /* Redefine "unused" pins */
#define IRQ_SOFTCLOCK 30
#define IRQ_SOFTSERIAL 29
#define IRQ_CLOCK 28
#define IRQ_STATCLOCK 27
#include <powerpc/ibm4xx/dcr4xx.h>
#else /* Generic 405 Universal Interrupt Controller */
#include "opt_uic.h"
#ifndef MULTIUIC
#include <powerpc/ibm4xx/dcr405gp.h>
#define INTR_STATUS DCR_UIC0_MSR
#define INTR_ACK DCR_UIC0_SR
#define INTR_ENABLE DCR_UIC0_ER
/* 405EP/405GP/405GPr/Virtex-4 */
#define INTR_STATUS (DCR_UIC0_BASE + DCR_UIC_MSR)
#define INTR_ACK (DCR_UIC0_BASE + DCR_UIC_SR)
#define INTR_ENABLE (DCR_UIC0_BASE + DCR_UIC_ER)
#else
/*
* We has following UICs. However can regist 32 HW-irqs.
* 440EP/440GP/440SP has 2 UICs.
* 405EX has 3 UICs.
* 440SPe has 4 UICs.
* 440GX has 4 UICs(3 UIC + UIC Base).
*/
#define NUIC 4
#define NIRQ ((NUIC) * ICU_LEN)
struct intrsrc;
static struct uic {
char uic_name[5];
uint32_t uic_baddr; /* UICn base address */
uint32_t uic_birq; /* UICn base irq */
struct intrsrc *uic_intrsrc;
} uics[NUIC];
static int num_uic = 0;
int base_uic = 0;
#define INTR_STATUS DCR_UIC_MSR
#define INTR_ACK DCR_UIC_SR
#define INTR_ENABLE DCR_UIC_ER
#undef mtdcr
#define _mtdcr(base, reg, val) \
__asm volatile("mtdcr %0,%1" : : "K"((base) + (reg)), "r"(val))
#define mtdcr(reg, val) \
({ \
switch(uic->uic_baddr) { \
case DCR_UIC0_BASE: _mtdcr(DCR_UIC0_BASE, (reg), (val)); break; \
case DCR_UIC1_BASE: _mtdcr(DCR_UIC1_BASE, (reg), (val)); break; \
case DCR_UIC2_BASE: _mtdcr(DCR_UIC2_BASE, (reg), (val)); break; \
case DCR_UIC3_BASE: _mtdcr(DCR_UIC3_BASE, (reg), (val)); break; \
case DCR_UICB_BASE: _mtdcr(DCR_UICB_BASE, (reg), (val)); break; \
case DCR_UIC2_BASE_440GX: \
_mtdcr(DCR_UIC2_BASE_440GX, (reg), (val)); break; \
default: \
panic("unknown UIC register 0x%x\n", uic->uic_baddr); \
} \
})
#undef mfdcr
#define _mfdcr(base, reg) \
__asm volatile("mfdcr %0,%1" : "=r"(__val) : "K"((base) + (reg)))
#define mfdcr(reg) \
({ \
uint32_t __val; \
\
switch(uic->uic_baddr) { \
case DCR_UIC0_BASE: _mfdcr(DCR_UIC0_BASE, reg); break; \
case DCR_UIC1_BASE: _mfdcr(DCR_UIC1_BASE, reg); break; \
case DCR_UIC2_BASE: _mfdcr(DCR_UIC2_BASE, reg); break; \
case DCR_UIC3_BASE: _mfdcr(DCR_UIC3_BASE, reg); break; \
case DCR_UICB_BASE: _mfdcr(DCR_UICB_BASE, reg); break; \
case DCR_UIC2_BASE_440GX: \
_mfdcr(DCR_UIC2_BASE_440GX, reg); break; \
default: \
panic("unknown UIC register 0x%x\n", uic->uic_baddr); \
} \
__val; \
})
uint8_t hwirq[ICU_LEN];
uint8_t virq[NIRQ];
int virq_max = 0;
static int ext_intr_core(void *);
#endif
#endif
@ -140,8 +198,9 @@ static const char *intr_typename(int);
struct intrhand {
int (*ih_fun)(void *);
void *ih_arg;
struct intrhand *ih_next;
int ih_level;
struct intrhand *ih_next;
int ih_irq;
};
struct intrsrc {
@ -157,9 +216,10 @@ volatile u_int imask[NIPL];
const int mask_clock = MASK_CLOCK;
const int mask_statclock = MASK_STATCLOCK;
static struct intrsrc intrs[ICU_LEN] = {
#define DEFINTR(name) \
{ EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, "uic", name), NULL, 0, 0 }
static struct intrsrc intrs0[ICU_LEN] = {
#define DEFINTR(name) \
{ EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, "uic0", name), \
NULL, 0, 0, 0 }
DEFINTR("pin0"), DEFINTR("pin1"), DEFINTR("pin2"),
DEFINTR("pin3"), DEFINTR("pin4"), DEFINTR("pin5"),
@ -167,15 +227,8 @@ static struct intrsrc intrs[ICU_LEN] = {
DEFINTR("pin9"), DEFINTR("pin10"), DEFINTR("pin11"),
DEFINTR("pin12"), DEFINTR("pin13"), DEFINTR("pin14"),
DEFINTR("pin15"), DEFINTR("pin16"), DEFINTR("pin17"),
DEFINTR("pin18"),
/* Reserved intrs, accounted in cpu_info */
DEFINTR(NULL), /* unused "pin19", softnet */
DEFINTR(NULL), /* unused "pin20", softclock */
DEFINTR(NULL), /* unused "pin21", softserial */
DEFINTR(NULL), /* unused "pin22", PIT hardclock */
DEFINTR(NULL), /* unused "pin23", FIT statclock */
DEFINTR("pin18"), DEFINTR("pin19"), DEFINTR("pin20"),
DEFINTR("pin21"), DEFINTR("pin22"), DEFINTR("pin23"),
DEFINTR("pin24"), DEFINTR("pin25"), DEFINTR("pin26"),
DEFINTR("pin27"), DEFINTR("pin28"), DEFINTR("pin29"),
DEFINTR("pin30"), DEFINTR("pin31")
@ -187,7 +240,7 @@ static struct intrsrc intrs[ICU_LEN] = {
/* Write External Enable Immediate */
#define wrteei(en) __asm volatile ("wrteei %0" : : "K"(en))
/* Enforce In Order Execution Of I/O */
/* Enforce In Order Execution of I/O */
#define eieio() __asm volatile ("eieio")
/*
@ -196,6 +249,9 @@ static struct intrsrc intrs[ICU_LEN] = {
void
intr_init(void)
{
#ifdef MULTIUIC
struct uic *uic = &uics[0];
#endif
int i;
for (i = 0; i < ICU_LEN; i++)
@ -207,7 +263,7 @@ intr_init(void)
case IRQ_STATCLOCK:
continue;
default:
evcnt_attach_static(&intrs[i].is_evcnt);
evcnt_attach_static(&intrs0[i].is_evcnt);
}
/* Initialized in powerpc/ibm4xx/cpu.c */
@ -215,22 +271,96 @@ intr_init(void)
evcnt_attach_static(&curcpu()->ci_ev_softnet);
evcnt_attach_static(&curcpu()->ci_ev_softserial);
#ifdef MULTIUIC
strcpy(uic->uic_name, intrs0[0].is_evcnt.ev_name);;
uic->uic_baddr = DCR_UIC0_BASE;
uic->uic_birq = num_uic * 32;
uic->uic_intrsrc = intrs0;
num_uic++;
#endif
mtdcr(INTR_ENABLE, 0x00000000); /* mask all */
mtdcr(INTR_ACK, 0xffffffff); /* acknowledge all */
#ifdef INTR_MASTER
mtdcr(INTR_MASTER, INTR_MASTER_EN); /* enable controller */
}
int
uic_add(u_int base, int irq)
{
#ifndef MULTIUIC
return -1;
#else
struct uic *uic = &uics[num_uic];
struct intrsrc *intrs;
int i;
#define UIC_BASE_TO_CHAR(b) \
(((b) >= DCR_UIC0_BASE && (b) <= DCR_UIC2_BASE) ? \
'0' + (((b) - DCR_UIC0_BASE) >> 4) : \
(((b) == DCR_UICB_BASE) ? 'b' : /* 440GX only */\
(((b) == DCR_UIC2_BASE_440GX) ? '2' : '?')))/* 440GX only */
sprintf(uic->uic_name, "uic%c", UIC_BASE_TO_CHAR(base));
uic->uic_baddr = base;
uic->uic_birq = num_uic * ICU_LEN;
intrs = malloc(sizeof(struct intrsrc) * ICU_LEN, M_DEVBUF,
M_NOWAIT | M_ZERO);
if (intrs == NULL)
return ENOMEM;
for (i = 0; i < ICU_LEN; i++)
switch (i + num_uic * ICU_LEN) {
case IRQ_SOFTNET:
case IRQ_SOFTCLOCK:
case IRQ_SOFTSERIAL:
case IRQ_CLOCK:
case IRQ_STATCLOCK:
continue;
default:
evcnt_attach_dynamic(
&intrs[i].is_evcnt, EVCNT_TYPE_INTR, NULL,
uic->uic_name, intrs0[i].is_evcnt.ev_name);
}
uic->uic_intrsrc = intrs;
num_uic++;
mtdcr(INTR_ENABLE, 0x00000000); /* mask all */
mtdcr(INTR_ACK, 0xffffffff); /* acknowledge all */
intr_establish(irq, IST_LEVEL, IPL_NONE, ext_intr_core, uic);
return 0;
#endif
}
/*
* external interrupt handler
*/
#ifdef MULTIUIC
void
ext_intr(void)
{
ext_intr_core(&uics[base_uic]);
}
#endif
#ifndef MULTIUIC
void
ext_intr(void)
#else
static int
ext_intr_core(void *arg)
#endif
{
struct cpu_info *ci = curcpu();
#ifndef MULTIUIC
struct intrsrc *intrs = intrs0;
#else
struct uic *uic = arg;
struct intrsrc *intrs = uic->uic_intrsrc;
#endif
struct intrhand *ih;
int i, bits_to_clear;
int irq, bits_to_clear, i;
int r_imen, msr;
int pcpl;
u_long int_state;
@ -244,18 +374,25 @@ ext_intr(void)
while (int_state) {
i = IRQ_OF_MASK(int_state);
r_imen = IRQ_TO_MASK(i);
#ifndef MULTIUIC
irq = i;
r_imen = IRQ_TO_MASK(irq);
int_state &= ~r_imen;
#else
irq = uic->uic_birq + i;
r_imen = IRQ_TO_MASK(virq[irq]);
int_state &= ~IRQ_TO_MASK(i);
#endif
if ((pcpl & r_imen) != 0) {
/* Masked! Mark as pending */
ci->ci_ipending |= r_imen;
disable_irq(i);
disable_irq(irq);
} else {
ci->ci_idepth++;
splraise(intrs[i].is_mask);
if (intrs[i].is_type == IST_LEVEL)
disable_irq(i);
disable_irq(irq);
wrteei(1);
ih = intrs[i].is_head;
@ -270,7 +407,7 @@ ext_intr(void)
mtmsr(msr);
if (intrs[i].is_type == IST_LEVEL)
enable_irq(i);
enable_irq(irq);
ci->ci_cpl = pcpl;
uvmexp.intrs++;
intrs[i].is_evcnt.ev_count++;
@ -282,11 +419,18 @@ ext_intr(void)
wrteei(1);
splx(pcpl);
mtmsr(msr);
#ifdef MULTIUIC
return 0;
#endif
}
static inline void
disable_irq(int irq)
{
#ifdef MULTIUIC
struct uic *uic = &uics[irq / ICU_LEN];
#endif
int mask, omask;
mask = omask = mfdcr(INTR_ENABLE);
@ -302,6 +446,9 @@ disable_irq(int irq)
static inline void
enable_irq(int irq)
{
#ifdef MULTIUIC
struct uic *uic = &uics[irq / ICU_LEN];
#endif
int mask, omask;
mask = omask = mfdcr(INTR_ENABLE);
@ -339,35 +486,50 @@ void *
intr_establish(int irq, int type, int level, int (*ih_fun)(void *),
void *ih_arg)
{
struct intrsrc *intrs;
struct intrhand *ih;
int msr;
int msr, i;
#ifndef MULTIUIC
if (! LEGAL_IRQ(irq))
panic("intr_establish: bogus irq %d", irq);
panic("intr_establish: bogus IRQ %d", irq);
intrs = intrs0;
i = irq;
#else
if (irq >= num_uic * ICU_LEN)
panic("intr_establish: bogus IRQ %d, max is %d",
irq, num_uic * ICU_LEN - 1);
intrs = uics[irq / ICU_LEN].uic_intrsrc;
i = irq % ICU_LEN;
if (intrs[i].is_head == NULL) {
virq[irq] = ++virq_max;
hwirq[virq[irq]] = irq;
}
#endif
if (type == IST_NONE)
panic("intr_establish: bogus type %d for irq %d", type, irq);
/* No point in sleeping unless someone can free memory. */
ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
ih = malloc(sizeof(*ih), M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
if (ih == NULL)
panic("intr_establish: can't malloc handler info");
switch (intrs[irq].is_type) {
switch (intrs[i].is_type) {
case IST_NONE:
intrs[irq].is_type = type;
intrs[i].is_type = type;
break;
case IST_EDGE:
case IST_LEVEL:
if (type == intrs[irq].is_type)
if (type == intrs[i].is_type)
break;
/* FALLTHROUGH */
case IST_PULSE:
if (type != IST_NONE)
panic("intr_establish: can't share %s with %s",
intr_typename(intrs[irq].is_type),
intr_typename(intrs[i].is_type),
intr_typename(type));
break;
}
@ -386,8 +548,9 @@ intr_establish(int irq, int type, int level, int (*ih_fun)(void *),
ih->ih_fun = ih_fun;
ih->ih_arg = ih_arg;
ih->ih_level = level;
ih->ih_next = intrs[irq].is_head;
intrs[irq].is_head = ih;
ih->ih_next = intrs[i].is_head;
ih->ih_irq = irq;
intrs[i].is_head = ih;
intr_calculatemasks();
@ -395,7 +558,8 @@ intr_establish(int irq, int type, int level, int (*ih_fun)(void *),
mtmsr(msr);
#ifdef IRQ_DEBUG
printf("***** intr_establish: irq%d h=%p arg=%p\n",irq, ih_fun, ih_arg);
printf("***** intr_establish: irq%d h=%p arg=%p\n",
irq, ih_fun, ih_arg);
#endif
return (ih);
}
@ -406,10 +570,19 @@ intr_establish(int irq, int type, int level, int (*ih_fun)(void *),
void
intr_disestablish(void *arg)
{
struct intrsrc *intrs;
struct intrhand *ih = arg;
struct intrhand **p;
int i, msr;
#ifndef MULTIUIC
intrs = intrs0;
#else
if (virq[ih->ih_irq] == 0)
panic("intr_disestablish: bogus irq %d", ih->ih_irq);
intrs = uics[ih->ih_irq / ICU_LEN].uic_intrsrc;
#endif
/* Lookup the handler. This is expensive, but not run often. */
for (i = 0; i < ICU_LEN; i++)
for (p = &intrs[i].is_head; *p != NULL; p = &(*p)->ih_next)
@ -440,23 +613,47 @@ intr_disestablish(void *arg)
static void
intr_calculatemasks(void)
{
#ifndef MULTIUIC
struct intrsrc *intrs = intrs0;
#else
struct intrsrc *intrs;
struct uic *uic;
int n;
#endif
struct intrhand *q;
int irq, level;
/* First, figure out which levels each IRQ uses. */
for (irq = 0; irq < ICU_LEN; irq++) {
register int levels = 0;
for (q = intrs[irq].is_head; q; q = q->ih_next)
levels |= 1 << q->ih_level;
intrs[irq].is_level = levels;
#ifdef MULTIUIC
for (n = 0, intrs = uics[n].uic_intrsrc; n < num_uic; n++)
#endif
{
/* First, figure out which levels each IRQ uses. */
for (irq = 0; irq < ICU_LEN; irq++) {
register int levels = 0;
for (q = intrs[irq].is_head; q; q = q->ih_next)
levels |= 1 << q->ih_level;
intrs[irq].is_level = levels;
}
}
/* Then figure out which IRQs use each level. */
for (level = 0; level < NIPL; level++) {
register int irqs = 0;
for (irq = 0; irq < ICU_LEN; irq++)
if (intrs[irq].is_level & (1 << level))
irqs |= IRQ_TO_MASK(irq);
#ifdef MULTIUIC
for (n = 0, uic = &uics[n], intrs = uic->uic_intrsrc;
n < num_uic; n++)
#endif
{
for (irq = 0; irq < ICU_LEN; irq++)
if (intrs[irq].is_level & (1 << level))
#ifndef MULTIUIC
irqs |= IRQ_TO_MASK(irq);
#else
irqs |= IRQ_TO_MASK(
virq[uic->uic_birq + irq]);
#endif
}
imask[level] = irqs | MASK_SOFTINTR;
}
@ -476,9 +673,11 @@ intr_calculatemasks(void)
imask[IPL_SCHED] = imask[IPL_VM] | MASK_CLOCK | MASK_STATCLOCK;
imask[IPL_HIGH] |= imask[IPL_SCHED];
#ifndef MULTIUIC
/* And eventually calculate the complete masks. */
for (irq = 0; irq < ICU_LEN; irq++) {
register int irqs = IRQ_TO_MASK(irq);
for (q = intrs[irq].is_head; q; q = q->ih_next)
irqs |= imask[q->ih_level];
intrs[irq].is_mask = irqs;
@ -489,16 +688,44 @@ intr_calculatemasks(void)
enable_irq(irq);
else
disable_irq(irq);
#else
for (n = 0; n < num_uic; n++) {
uic = &uics[n];
intrs = uic->uic_intrsrc;
/* And eventually calculate the complete masks. */
for (irq = 0; irq < ICU_LEN; irq++) {
register int irqs =
IRQ_TO_MASK(virq[uic->uic_birq + irq]);
for (q = intrs[irq].is_head; q; q = q->ih_next)
irqs |= imask[q->ih_level];
intrs[irq].is_mask = irqs;
}
for (irq = 0; irq < ICU_LEN; irq++)
if (intrs[irq].is_head != NULL)
enable_irq(uic->uic_birq + irq);
else
disable_irq(uic->uic_birq + irq);
}
#endif
}
static void
do_pending_int(void)
{
struct cpu_info *ci = curcpu();
#ifndef MULTIUIC
struct intrsrc *intrs = intrs0;
#else
struct intrsrc *intrs;
struct uic *uic;
#endif
struct intrhand *ih;
int irq;
int irq, i;
int pcpl;
int hwpend;
int pend, hwpend;
int emsr;
if (ci->ci_idepth)
@ -515,17 +742,31 @@ do_pending_int(void)
#ifdef __HAVE_FAST_SOFTINTS
again:
#endif
while ((hwpend = ci->ci_ipending & ~pcpl & MASK_HARDINTR) != 0) {
irq = IRQ_OF_MASK(hwpend);
if (intrs[irq].is_type != IST_LEVEL)
while ((pend = ci->ci_ipending & ~pcpl & MASK_HARDINTR) != 0) {
#ifndef MULTIUIC
irq = IRQ_OF_MASK(pend);
i = irq;
hwpend = pend;
#else
irq = hwirq[IRQ_OF_MASK(pend)];
i = irq % ICU_LEN;
hwpend = IRQ_TO_MASK(irq);
uic = &uics[irq / ICU_LEN];
intrs = uic->uic_intrsrc;
#endif
if (intrs[i].is_type != IST_LEVEL)
enable_irq(irq);
#ifndef MULTIUIC
ci->ci_ipending &= ~IRQ_TO_MASK(irq);
#else
ci->ci_ipending &= ~IRQ_TO_MASK(virq[irq]);
#endif
splraise(intrs[irq].is_mask);
splraise(intrs[i].is_mask);
mtmsr(emsr);
ih = intrs[irq].is_head;
ih = intrs[i].is_head;
while(ih) {
if (ih->ih_level == IPL_VM)
KERNEL_LOCK(1, NULL);
@ -534,12 +775,13 @@ do_pending_int(void)
KERNEL_UNLOCK_ONE(NULL);
ih = ih->ih_next;
}
mtdcr(INTR_ACK, hwpend);
wrteei(0);
if (intrs[irq].is_type == IST_LEVEL)
if (intrs[i].is_type == IST_LEVEL)
enable_irq(irq);
ci->ci_cpl = pcpl;
intrs[irq].is_evcnt.ev_count++;
intrs[i].is_evcnt.ev_count++;
}
#ifdef __HAVE_FAST_SOFTINTS
if ((ci->ci_ipending & ~pcpl) & MASK_SOFTSERIAL) {

26
sys/arch/powerpc/include/cpu.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.68 2010/03/09 22:41:03 matt Exp $ */
/* $NetBSD: cpu.h,v 1.69 2010/03/18 13:47:05 kiyohara Exp $ */
/*
* Copyright (C) 1999 Wolfgang Solfrank.
@ -310,6 +310,30 @@ cntlzw(uint32_t val)
__asm volatile("mfdcr %0,%1" : "=r"(__val) : "K"(reg)); \
__val; \
})
#define mtcpr(reg, val) \
do { \
mtdcr(DCR_CPR0_CFGADDR, reg); \
mtdcr(DCR_CPR0_CFGDATA, val); \
} while (0/*CONSTCOND*/)
#define mfcpr(reg) \
({ \
mtdcr(DCR_CPR0_CFGADDR, reg); \
mfdcr(DCR_CPR0_CFGDATA); \
})
#define mtsdr(reg, val) \
do { \
mtdcr(DCR_SDR0_CFGADDR, reg); \
mtdcr(DCR_SDR0_CFGDATA, val); \
} while (0/*CONSTCOND*/)
#define mfsdr(reg) \
({ \
mtdcr(DCR_SDR0_CFGADDR, reg); \
mfdcr(DCR_SDR0_CFGDATA); \
})
#endif /* PPC_IBM4XX || PPC_IBM403 */
#define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0)

92
sys/arch/powerpc/include/ibm4xx/amcc405ex.h Normal file
View File

@ -0,0 +1,92 @@
/* $NetBSD: amcc405ex.h,v 1.1 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Simon Burge and Eduardo Horvath for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _IBM4XX_AMCC405EX_H_
#define _IBM4XX_AMCC405EX_H_
/*
* Memory and PCI addresses
*/
/* Local Memory and Peripherals */
#define AMCC405EX_LOCAL_MEM_START 0x00000000
#define AMCC405EX_LOCAL_MEM_END 0x7fffffff
/* EBC - 256MB */
#define AMCC405EX_EBC_START 0x80000000
#define AMCC405EX_EBC_END 0x8fffffff
/* PCI Express - 1.6GB */
#define AMCC405EX_PCIE_MEM_START 0x90000000
#define AMCC405EX_PCIE_MEM_END 0xef5fffff
/*
* Internal peripheral addresses
*/
#define AMCC405EX_OPB_BASE 0xef600000
#define AMCC405EX_GPT0_BASE 0xef600000
#define AMCC405EX_UART0_BASE 0xef600200
#define AMCC405EX_UART1_BASE 0xef600300
#define AMCC405EX_IIC0_BASE 0xef600400
#define AMCC405EX_IIC1_BASE 0xef600500
#define AMCC405EX_SCP0_BASE 0xef600600
#define AMCC405EX_OPBA0_BASE 0xef600700
#define AMCC405EX_GPIO0_BASE 0xef600800
#define AMCC405EX_EMAC0_BASE 0xef600900
#define AMCC405EX_EMAC1_BASE 0xef600a00
#define AMCC405EX_RGMIIB0_BASE 0xef600b00
#define AMCC405EX_PKATRNG0_BASE 0xef610000
#define AMCC405EX_PCIEIH0_BASE 0xef620000
#define AMCC405EX_USBOTG0_BASE 0xef6c0000
#define AMCC405EX_SECURITY0_BASE 0xef700000
/* Expansion ROM - 254MB */
#define AMCC405EX_EXPANSION_ROM_START 0xf0000000
#define AMCC405EX_EXPANSION_ROM_END 0xffdfffff
/* Boot ROM - 2MB */
#define AMCC405EX_BOOT_ROM_START 0xffe00000
#define AMCC405EX_BOOT_ROM_END 0xffffffff
#ifndef _LOCORE
void ibm4xx_show_pci_map(void);
void ibm4xx_setup_pci(void);
#endif /* _LOCORE */
#endif /* _IBM4XX_AMCC405EX_H_ */

16
sys/arch/powerpc/include/ibm4xx/cpu.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.14 2009/03/14 14:46:05 dsl Exp $ */
/* $NetBSD: cpu.h,v 1.15 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -49,17 +49,19 @@
#define PVR_403 0x00200000
#define PVR_405GP 0x40110000
#define PVR_405GP_PASS1 0x40110000 /* RevA */
#define PVR_405GP_PASS2 0x40110040 /* RevB */
#define PVR_405GP_PASS2_1 0x40110082 /* RevC */
#define PVR_405GP_PASS3 0x401100c4 /* RevD */
#define PVR_405GPR 0x50910000
#define PVR_405GP 0x40110000
#define PVR_405GP_PASS1 0x40110000 /* RevA */
#define PVR_405GP_PASS2 0x40110040 /* RevB */
#define PVR_405GP_PASS2_1 0x40110082 /* RevC */
#define PVR_405GP_PASS3 0x401100c4 /* RevD */
#define PVR_405GPR 0x50910000
#define PVR_405GPR_REVB 0x50910951
#define PVR_405D5X1 0x20010000 /* Virtex II Pro */
#define PVR_405D5X2 0x20011000 /* Virtex 4 FX */
#define PVR_405EX 0x12910000
#if defined(_KERNEL)
extern char bootpath[];

1250
sys/arch/powerpc/include/ibm4xx/dcr405xx.h
View File

File diff suppressed because it is too large Load Diff

105
sys/arch/powerpc/include/ibm4xx/dcr405gp.h → sys/arch/powerpc/include/ibm4xx/dcr4xx.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: dcr405gp.h,v 1.5 2006/05/30 22:44:14 freza Exp $ */
/* $NetBSD: dcr4xx.h,v 1.1 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -41,6 +41,10 @@
/* Device Control Register declarations */
/* DCRs used for indirect access */
#define DCR_CPR0_CFGADDR 0x00c /* Clocking Configuration Address Register */
#define DCR_CPR0_CFGDATA 0x00d /* Clocking Configuration Data Register */
#define DCR_SDR0_CFGADDR 0x00e /* System DCR Configuration Address Register */
#define DCR_SDR0_CFGDATA 0x00f /* System DCR Configuration Data Register */
#define DCR_SDRAM0_CFGADDR 0x010 /* Memory Controller Address Register */
#define DCR_SDRAM0_CFGDATA 0x011 /* Memory Controller Data Register */
#define DCR_EBC0_CFGADDR 0x012 /* Peripheral Controller Address Register */
@ -64,6 +68,8 @@
/* Clocking, Power management and Chip Control */
#define DCR_CPC0_PLLMR 0x0b0 /* PLL Mode Register */
#define CPC0_PLLMR_CBDV(pllmr) ((((pllmr) & 0x00060000) >> 17) + 1)
#define CPC0_PLLMR_OPDV(pllmr) ((((pllmr) & 0x00018000) >> 15) + 1)
#define DCR_CPC0_CR0 0x0b1 /* Chip Control Register 0 */
#define DCR_CPC0_CR1 0x0b2 /* Chip Control Register 1 */
#define CPC0_CR1_CETE 0x00800000 /* CPU External Timer Enable */
@ -74,14 +80,21 @@
#define DCR_CPC0_FR 0x0ba /* CPM Force Register */
/* Universal Interrupt Controllers */
#define DCR_UIC0_SR 0x0c0 /* UIC0 Status Register */
#define DCR_UIC0_ER 0x0c2 /* UIC0 Enable Register */
#define DCR_UIC0_CR 0x0c3 /* UIC0 Critical Register */
#define DCR_UIC0_PR 0x0c4 /* UIC0 Polarity Register */
#define DCR_UIC0_TR 0x0c5 /* UIC0 Triggering Register */
#define DCR_UIC0_MSR 0x0c6 /* UIC0 Masked Status Register */
#define DCR_UIC0_VR 0x0c7 /* UIC0 Vector Register */
#define DCR_UIC0_VCR 0x0c8 /* UIC0 Vector Configuration Register */
#define DCR_UIC0_BASE 0x0c0 /* UIC0 Registers Base */
#define DCR_UIC1_BASE 0x0d0 /* UIC1 Registers Base */
#define DCR_UIC2_BASE 0x0e0 /* UIC2 Registers Base */
#define DCR_UIC3_BASE 0x0f0 /* UIC3 Registers Base */
#define DCR_UICB_BASE 0x200 /* UICB Registers Base */
#define DCR_UIC2_BASE_440GX 0x210 /* UIC2 Registers Base (440GX only) */
#define DCR_UIC_SR 0x000 /* UIC Status Register */
#define DCR_UIC_ER 0x002 /* UIC Enable Register */
#define DCR_UIC_CR 0x003 /* UIC Critical Register */
#define DCR_UIC_PR 0x004 /* UIC Polarity Register */
#define DCR_UIC_TR 0x005 /* UIC Triggering Register */
#define DCR_UIC_MSR 0x006 /* UIC Masked Status Register */
#define DCR_UIC_VR 0x007 /* UIC Vector Register */
#define DCR_UIC_VCR 0x008 /* UIC Vector Configuration Register */
/* Direct Memory Access */
#define DCR_DMA0_CR0 0x100 /* DMA Channel Control Register 0 */
@ -131,22 +144,54 @@
#define MAL0_CFG_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */
#define MAL0_CFG_LEA 0x00000002 /* Locked Error Active */
#define MAL0_CFG_SD 0x00000001 /* MAL Scroll Descriptor */
#define MAL0_CFG_RPP_MASK 0x00c00000 /* Read priority mask */
#define MAL0_CFG_RPP_0 0x00000000 /* Lowest */
#define MAL0_CFG_RPP_1 0x00400000
#define MAL0_CFG_RPP_2 0x00800000
#define MAL0_CFG_RPP_3 0x00c00000 /* Highest */
#define MAL0_CFG_RMBS_MASK 0x00300000 /* Read Max Burst Size */
#define MAL0_CFG_RMBS_4 0x00000000 /* Max burst size of 4 */
#define MAL0_CFG_RMBS_8 0x00100000 /* Max burst size of 8 */
#define MAL0_CFG_RMBS_16 0x00200000 /* Max burst size of 16 */
#define MAL0_CFG_RMBS_32 0x00300000 /* Max burst size of 32 */
#define MAL0_CFG_WPP_MASK 0x000c0000 /* Write PLB Priority */
#define MAL0_CFG_WPP_0 0x00000000 /* Lowest */
#define MAL0_CFG_WPP_1 0x00040000
#define MAL0_CFG_WPP_2 0x00080000
#define MAL0_CFG_WPP_3 0x000c0000 /* Highest */
#define MAL0_CFG_WMBS_MASK 0x00030000 /* Write Max Burst Size */
#define MAL0_CFG_WMBS_4 0x00000000 /* Max burst size of 4 */
#define MAL0_CFG_WMBS_8 0x00010000 /* Max burst size of 8 */
#define MAL0_CFG_WMBS_16 0x00020000 /* Max burst size of 16 */
#define MAL0_CFG_WMBS_32 0x00030000 /* Max burst size of 32 */
#define MAL0_CFG_PLBLE__EX 0x00008000 /* PLB Lock Error */
#define DCR_MAL0_ESR 0x181 /* Error Status Register */
#define MAL0_ESR_EVB 0x80000000 /* Error Valid Bit */
#define MAL0_ESR_CID_RX 0x40000000 /* Receive Channel */
#define MAL0_ESR_CID_MASK 0x3e000000 /* Channel ID */
#define MAL0_ESR_CID_SHIFT 25
#define MAL0_ESR_PTE 0x00800000 /* PLB Timeout Error */
#define MAL0_ESR_PRE 0x00400000 /* PLB Read Error */
#define MAL0_ESR_PWE 0x00200000 /* PLB Write Error */
#define MAL0_ESR_DE 0x00100000 /* Descriptor Error */
#define MAL0_ESR_ONE 0x00080000 /* OPB Non-fullword Error */
#define MAL0_ESR_OTE 0x00040000 /* OPB Timeout Error */
#define MAL0_ESR_OSE 0x00020000 /* OPB Slave Error */
#define MAL0_ESR_PEIN 0x00010000 /* PLB Bus Error Indication */
#define MAL0_ESR_PTEI 0x00000080 /* PLB Timeout Error Interrupt */
#define MAL0_ESR_PREI 0x00000040 /* PLB Read Error Interrupt */
#define MAL0_ESR_PWEI 0x00000020 /* PLB Write Error Interrupt */
#define MAL0_ESR_DEI 0x00000010 /* Descriptor Error Interrupt */
#define MAL0_ESR_ONEI 0x00000008 /* OPB Non-fullword Error Interrupt */
#define MAL0_ESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */
#define MAL0_ESR_OSEI 0x00000002 /* OPB Slave Error Interrupt */
#define MAL0_ESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */
#define DCR_MAL0_IER 0x182 /* Interrupt Enable Register */
#define MAL0_IER_PT 0x00000080 /* PLB Timeout Interrupt */
#define MAL0_IER_PRE 0x00000040 /* PLB Read Interrupt */
#define MAL0_IER_PWE 0x00000020 /* PLB Write Interrupt */
#define MAL0_IER_DE 0x00000010 /* Descriptor Error Interrupt */
#define MAL0_IER_NWE 0x00000008 /* Non-Word Transfer Error Interrupt */
#define MAL0_IER_TO 0x00000004 /* Time Out Error Interrupt */
@ -154,28 +199,52 @@
#define MAL0_IER_PLB 0x00000001 /* PLB Error Interrupt */
#define DCR_MALDBR 0x183 /* MAL Debug register */
#define DCR_MAL0_TXCASR 0x184 /* Tx Channel Active Register (Set) */
#define MAL0_TXCASR_CHAN0 0x80000000 /* Channel 0 Set Active */
#define MAL0_TXCASR_CHAN1 0x40000000 /* Channel 1 Set Active */
#define DCR_MAL0_TXCARR 0x185 /* Tx Channel Active Register (Reset) */
#define MAL0_TXCARR_CHAN0 0x80000000 /* Channel 0 Reset Active */
#define MAL0_TXCARR_CHAN1 0x40000000 /* Channel 1 Reset Active */
#define DCR_MAL0_TXEOBISR 0x186 /* Tx End of Buffer Interrupt Status Register */
#define MAL0_TXEOBISR_CHAN0 0x80000000 /* Channel 0 finished */
#define MAL0_TXEOBISR_CHAN1 0x40000000 /* Channel 1 finished */
#define DCR_MAL0_TXDEIR 0x187 /* Tx Descriptor Error Interrupt Register */
#define DCR_MAL0_RXCASR 0x190 /* Rx Channel Active Register (Set) */
#define MAL0_RXCASR_CHAN0 0x80000000 /* Channel 0 Set Active */
#define DCR_MAL0_RXCARR 0x191 /* Rx Channel Active Register (Reset) */
#define MAL0_RXCARR_CHAN0 0x80000000 /* Channel 0 Reset Active */
#define DCR_MAL0_RXEOBISR 0x192 /* Rx End of Buffer Interrupt Status Register */
#define MAL0_RXEOBISR_CHAN0 0x80000000 /* Channel 0 finished */
#define DCR_MAL0_RXDEIR 0x193 /* Rx Descriptor Error Interrupt Register */
#define MAL0__XCAR_CHAN(c) (0x80000000 >> (c))
#define DCR_MAL0_TXCTP0R 0x1a0 /* Channel Tx 0 Channel Table Pointer Register */
#define DCR_MAL0_TXCTP1R 0x1a1 /* Channel Tx 1 Channel Table Pointer Register */
#define DCR_MAL0_TXCTP2R 0x1a2 /* Channel Tx 2 Channel Table Pointer Register */
#define DCR_MAL0_TXCTP3R 0x1a3 /* Channel Tx 3 Channel Table Pointer Register */
#define DCR_MAL0_RXCTP0R 0x1c0 /* Channel Rx 0 Channel Table Pointer Register */
#define DCR_MAL0_RXCTP1R 0x1c1 /* Channel Rx 1 Channel Table Pointer Register */
#define DCR_MAL0_RXCTP2R 0x1c2 /* Channel Rx 2 Channel Table Pointer Register */
#define DCR_MAL0_RXCTP3R 0x1c3 /* Channel Rx 3 Channel Table Pointer Register */
#define DCR_MAL0_RCBS0 0x1e0 /* Channel Rx 0 Channel Buffer Size Register */
#define DCR_MAL0_RCBS1 0x1e1 /* Channel Rx 1 Channel Buffer Size Register */
#define DCR_MAL0_RCBS2 0x1e2 /* Channel Rx 2 Channel Buffer Size Register */
#define DCR_MAL0_RCBS3 0x1e3 /* Channel Rx 3 Channel Buffer Size Register */
/* Indirectly accessed Clocking Controller DCRs */
#define DCR_CPR0_CLKUPD 0x020 /* Clocking Update Register */
#define DCR_CPR0_PLLC 0x040 /* SYS_PLL Control Register */
#define DCR_CPR0_PLLD 0x060 /* SYS_PLL Divider Register */
#define DCR_CPR0_CPUD 0x080 /* CPU Clock Divider Register */
#define DCR_CPR0_PLBD 0x0a0 /* PLB Clock Divider Register */
#define CPR0_PLBDV0(x) \
((((x) & 0x07000000) >> 24) == 0 ? 8 : (((x) & 0x07000000) >> 24))
#define DCR_CPR0_OPBD 0x0c0 /* OPB Clock Divider Register */
#define CPR0_OPBDV0(x) \
((((x) & 0x03000000) >> 24) == 0 ? 4 : (((x) & 0x03000000) >> 24))
#define DCR_CPR0_PERD 0x0e0 /* Peripheral Clock Divider Register */
#define DCR_CPR0_AHBD 0x100 /* AHB Clock Divider Register */
#define DCR_CPR0_ICFG 0x140 /* Initial Configuration Register */
/* Indirectly accessed Clocking Controller DCRs */
#define DCR_SDR0_MFR 0x4300 /* Miscellaneous Function Register */
#define SDR0_MFR_ECS(n) (1 << (27 - (n))) /* Ethernet n Clock Selection */
#define SDR0_MFR_ETXFL(n) (1 << (15 - ((n) << 2))) /* Force Parity Error EMACn Tx FIFO Bits 0:63 */
#define SDR0_MFR_ETXFH(n) (1 << (14 - ((n) << 2))) /* Force Parity Error EMACn Tx FIFO Bits 64:127 */
#define SDR0_MFR_ERXFL(n) (1 << (13 - ((n) << 2))) /* Force Parity Error EMACn Rx FIFO Bits 0:63 */
#define SDR0_MFR_ERXFH(n) (1 << (12 - ((n) << 2))) /* Force Parity Error EMACn Rx FIFO Bits 64:127 */
/* Indirectly accessed SDRAM Controller DCRs */

3
sys/arch/powerpc/include/ibm4xx/ibm405gp.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: ibm405gp.h,v 1.10 2005/12/11 12:18:43 christos Exp $ */
/* $NetBSD: ibm405gp.h,v 1.11 2010/03/18 13:47:04 kiyohara Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -75,6 +75,7 @@
/*
* Internal peripheral addresses
*/
#define IBM405GP_IP_BASE 0xef600000
#define IBM405GP_UART0_BASE 0xef600300
#define IBM405GP_UART1_BASE 0xef600400

3
sys/arch/powerpc/include/ibm4xx/ibm4xx_intr.h
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@ -1,4 +1,4 @@
/* $NetBSD: ibm4xx_intr.h,v 1.16 2008/04/28 20:23:32 martin Exp $ */
/* $NetBSD: ibm4xx_intr.h,v 1.17 2010/03/18 13:47:04 kiyohara Exp $ */
/*-
* Copyright (c) 1998, 2007 The NetBSD Foundation, Inc.
@ -57,6 +57,7 @@
void *intr_establish(int, int, int, int (*)(void *), void *);
void intr_disestablish(void *);
void intr_init(void);
int uic_add(u_int, int);
void ext_intr(void); /* for machdep */
int splraise(int);
int spllower(int);

3
sys/arch/powerpc/include/ibm4xx/spr.h
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@ -1,4 +1,4 @@
/* $NetBSD: spr.h,v 1.1 2010/02/25 23:30:05 matt Exp $ */
/* $NetBSD: spr.h,v 1.2 2010/03/18 13:47:04 kiyohara Exp $ */
#ifndef _POWERPC_IBM4XX_SPR_H_
#define _POWERPC_IBM4XX_SPR_H_
@ -21,6 +21,7 @@
#define IBM401E2 0x0025
#define IBM401F2 0x0026
#define IBM401G2 0x0027
#define AMCC405EX 0x1291
#define XILVIRTEX 0x2001
#define IBM405GP 0x4011
#define IBMSTB03 0x4013