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Do set up the auxpll to the right value (8, to generate 96MHz),

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because the Au1500 and/or this board's firmware don't have it to the
right value at bootup, as was previously assumed. Makes USB-host work
on the Au1500, and should cause no change on other boards where it
previously "just worked".

Remove some #if 0'd out setting of FREQ0, since it's not currently
used.
This commit is contained in:
nathanw 2004-03-16 21:20:06 +00:00
parent 6e297aabcb
commit 263f910569
1 changed files with 3 additions and 8 deletions
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11
sys/arch/evbmips/alchemy/machdep.c
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@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.16 2004/02/13 11:36:12 wiz Exp $ */ /* $NetBSD: machdep.c,v 1.17 2004/03/16 21:20:06 nathanw Exp $ */
/* /*
* Copyright (c) 1992, 1993 * Copyright (c) 1992, 1993
@ -77,7 +77,7 @@
*/ */
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.16 2004/02/13 11:36:12 wiz Exp $"); __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.17 2004/03/16 21:20:06 nathanw Exp $");
#include "opt_ddb.h" #include "opt_ddb.h"
#include "opt_kgdb.h" #include "opt_kgdb.h"
@ -322,17 +322,12 @@ mach_init(int argc, char **argv, yamon_env_var *envp, u_long memsize)
/* /*
* Assign a clock for the USB Host controller. * Assign a clock for the USB Host controller.
*/ */
volatile u_int32_t *scsreg; volatile u_int32_t *scsreg, *auxpll;
u_int32_t tmp; u_int32_t tmp;
scsreg = (volatile u_int32_t *)(MIPS_PHYS_TO_KSEG1(SYS_CLKSRC)); scsreg = (volatile u_int32_t *)(MIPS_PHYS_TO_KSEG1(SYS_CLKSRC));
#if 0
auxpll = (volatile u_int32_t *)(MIPS_PHYS_TO_KSEG1(SYS_AUXPLL)); auxpll = (volatile u_int32_t *)(MIPS_PHYS_TO_KSEG1(SYS_AUXPLL));
*auxpll = 8; /* 96Mhz */ *auxpll = 8; /* 96Mhz */
tmp = *sfc0;
tmp |= SFC_FE0|SFC_FRDIV0;
*sfc0 = tmp;
#endif
tmp = *scsreg; tmp = *scsreg;
tmp &= ~USBH_ALL; /* clear all USBH bits in SYS_CLKSRC first */ tmp &= ~USBH_ALL; /* clear all USBH bits in SYS_CLKSRC first */
tmp |= (SCS_DUH|SCS_CUH|SCS_MUH(SCS_MEx_AUX)); /* 48Mhz */ tmp |= (SCS_DUH|SCS_CUH|SCS_MUH(SCS_MEx_AUX)); /* 48Mhz */