Add support for QEMU ARM Virtual Machine ("virt").

This commit is contained in:
jmcneill 2018-06-14 10:56:39 +00:00
parent 2f78d473d8
commit 2417111f9f
10 changed files with 508 additions and 2 deletions

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@ -0,0 +1,9 @@
# $NetBSD: files.virt,v 1.1 2018/06/14 10:56:39 jmcneill Exp $
#
# Configuration info for QEMU virtual boards.
#
#
file arch/arm/virt/virt_platform.c soc_virt
defflag opt_soc.h SOC_VIRT

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/* $NetBSD: virt_platform.c,v 1.1 2018/06/14 10:56:39 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include "opt_soc.h"
#include "opt_multiprocessor.h"
#include "opt_fdt_arm.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: virt_platform.c,v 1.1 2018/06/14 10:56:39 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/cpu.h>
#include <sys/device.h>
#include <sys/termios.h>
#include <dev/fdt/fdtvar.h>
#include <arm/fdt/arm_fdtvar.h>
#include <uvm/uvm_extern.h>
#include <machine/bootconfig.h>
#include <arm/cpufunc.h>
#include <evbarm/dev/plcomreg.h>
#include <evbarm/dev/plcomvar.h>
#include <dev/ic/ns16550reg.h>
#include <dev/ic/comreg.h>
#include <arm/cortex/gtmr_var.h>
#include <arm/arm/psci.h>
#include <arm/fdt/psci_fdt.h>
#include <arm/virt/virt_platform.h>
#define VIRT_UART_BASE 0x09000000
static const struct pmap_devmap *
virt_platform_devmap(void)
{
static const struct pmap_devmap devmap[] = {
DEVMAP_ENTRY(VIRT_CORE_VBASE,
VIRT_CORE_PBASE,
VIRT_CORE_SIZE),
DEVMAP_ENTRY_END
};
return devmap;
}
static void
virt_platform_init_attach_args(struct fdt_attach_args *faa)
{
extern struct arm32_bus_dma_tag arm_generic_dma_tag;
extern struct bus_space arm_generic_bs_tag;
extern struct bus_space arm_generic_a4x_bs_tag;
faa->faa_bst = &arm_generic_bs_tag;
faa->faa_a4x_bst = &arm_generic_a4x_bs_tag;
faa->faa_dmat = &arm_generic_dma_tag;
}
void virt_platform_early_putchar(char);
void
virt_platform_early_putchar(char c)
{
volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
(volatile uint32_t *)VIRT_CORE_PTOV(VIRT_UART_BASE) :
(volatile uint32_t *)VIRT_UART_BASE;
while ((uartaddr[PL01XCOM_FR / 4] & PL01X_FR_TXFF) != 0)
continue;
uartaddr[PL01XCOM_DR / 4] = c;
while ((uartaddr[PL01XCOM_FR / 4] & PL01X_FR_TXFE) == 0)
continue;
}
static void
virt_platform_device_register(device_t self, void *aux)
{
}
static u_int
virt_platform_uart_freq(void)
{
return 24000000;
}
static const struct arm_platform virt_platform = {
.devmap = virt_platform_devmap,
.bootstrap = psci_fdt_bootstrap,
.init_attach_args = virt_platform_init_attach_args,
.early_putchar = virt_platform_early_putchar,
.device_register = virt_platform_device_register,
.reset = psci_fdt_reset,
.delay = gtmr_delay,
.uart_freq = virt_platform_uart_freq,
};
ARM_PLATFORM(virt, "linux,dummy-virt", &virt_platform);

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/* $NetBSD: virt_platform.h,v 1.1 2018/06/14 10:56:39 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _ARM_VIRT_PLATFORM_H
#define _ARM_VIRT_PLATFORM_H
#include <arch/evbarm/fdt/platform.h>
#define VIRT_CORE_VBASE KERNEL_IO_VBASE
#define VIRT_CORE_PBASE 0x00000000
#define VIRT_CORE_SIZE 0x10000000
#define VIRT_CORE_PTOV(p) (((p) - VIRT_CORE_PBASE) + VIRT_CORE_VBASE)
#endif /* _ARM_VIRT_PLATFORM_H */

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@ -1,5 +1,5 @@
#
# $NetBSD: GENERIC64,v 1.15 2018/05/10 00:05:22 jmcneill Exp $
# $NetBSD: GENERIC64,v 1.16 2018/06/14 10:56:39 jmcneill Exp $
#
# GENERIC ARM (aarch64) kernel
#
@ -49,6 +49,7 @@ options SOC_TEGRA210
options SOC_SUN50I_A64
options SOC_SUN50I_H5
options SOC_SUN50I_H6
options SOC_VIRT
#options MULTIPROCESSOR
pseudo-device openfirm # /dev/openfirm
@ -63,6 +64,7 @@ options VERBOSE_INIT_ARM # verbose bootstrapping messages
#options EARLYCONS=bcm2837
#options EARLYCONS=sunxi, CONSADDR=0x01c28000
#options EARLYCONS=tegra, CONSADDR=0x70006000
#options EARLYCONS=virt
makeoptions DEBUG="-g" # compile full symbol table
makeoptions COPY_SYMTAB=1

56
sys/arch/evbarm/conf/VIRT Normal file
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#
# $NetBSD: VIRT,v 1.1 2018/06/14 10:56:39 jmcneill Exp $
#
# QEMU ARM 'virt' virtual machine
#
include "arch/evbarm/conf/std.virt"
include "arch/evbarm/conf/GENERIC.common"
options CPU_CORTEXA15
options SOC_VIRT
options MULTIPROCESSOR
pseudo-device openfirm # /dev/openfirm
#options DIAGNOSTIC # internal consistency checks
#options DEBUG
#options LOCKDEBUG
#options PMAP_DEBUG # Enable pmap_debug_level code
#options IPKDB # remote kernel debugging
#options VERBOSE_INIT_ARM # verbose bootstrapping messages
makeoptions DEBUG="-g" # compile full symbol table
makeoptions COPY_SYMTAB=1
config netbsd root on ? type ?
# Device tree support
armfdt0 at root
fdt* at fdtbus?
# CPUs
cpus* at fdt? pass 0
cpu* at cpus?
fclock* at fdt? pass 4
fregulator* at fdt? pass 4
# Power state coordination interface
psci* at fdt?
# Timer
gtmr* at fdt? pass 1 # ARM Generic Timer
armgtmr0 at gtmr?
# Interrupt controller
gic* at fdt? pass 1 # GIC
armgic0 at gic?
# UART
plcom* at fdt? # ARM PL011 UART
# RTC
plrtc* at fdt? # ARM PrimeCell RTC
cinclude "arch/evbarm/conf/VIRT.local"

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@ -1,4 +1,4 @@
# $NetBSD: files.generic64,v 1.1 2018/04/01 04:35:04 ryo Exp $
# $NetBSD: files.generic64,v 1.2 2018/06/14 10:56:39 jmcneill Exp $
#
defparam opt_arm_debug.h EARLYCONS
@ -13,3 +13,4 @@ include "arch/evbarm/conf/files.fdt"
include "arch/arm/broadcom/files.bcm2835"
include "arch/arm/nvidia/files.tegra"
include "arch/arm/sunxi/files.sunxi"
include "arch/arm/virt/files.virt"

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# $NetBSD: files.virt,v 1.1 2018/06/14 10:56:39 jmcneill Exp $
#
# QEMU 'virt' machine configuration info
#
include "arch/arm/pic/files.pic"
include "arch/arm/cortex/files.cortex"
file arch/arm/arm32/arm32_boot.c
file arch/arm/arm32/arm32_kvminit.c
file arch/arm/arm32/arm32_reboot.c
file arch/arm/arm32/irq_dispatch.S
file arch/arm/arm32/armv7_generic_space.c
file arch/arm/arm/arm_generic_dma.c
file arch/arm/arm/bus_space_a4x.S
include "arch/evbarm/conf/files.fdt"
include "arch/arm/virt/files.virt"

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# $NetBSD: mk.virt,v 1.1 2018/06/14 10:56:39 jmcneill Exp $
.if !empty(MACHINE_ARCH:M*eb)
EXTRA_LINKFLAGS+= --be8
.endif
SYSTEM_FIRST_OBJ= virt_start.o
SYSTEM_FIRST_SFILE= ${THISARM}/virt/virt_start.S
_OSRELEASE!= ${HOST_SH} $S/conf/osrelease.sh
KERNEL_BASE_PHYS?=$(LOADADDRESS)
KERNEL_BASE_VIRT?=$(LOADADDRESS)
MKUBOOTIMAGEARGS= -A arm -T kernel -O linux
MKUBOOTIMAGEARGS+= -a $(KERNEL_BASE_PHYS) -e $(KERNEL_BASE_PHYS)
MKUBOOTIMAGEARGS+= -n "NetBSD/$(BOARDTYPE) ${_OSRELEASE}"
MKUBOOTIMAGEARGS_NONE= ${MKUBOOTIMAGEARGS} -C none
MKUBOOTIMAGEARGS_GZ= ${MKUBOOTIMAGEARGS} -C gz
SYSTEM_LD_TAIL_EXTRA+=; \
echo ${OBJCOPY} -S -O binary $@ $@.bin; \
${OBJCOPY} -S -O binary $@ $@.bin; \
echo ${TOOL_GZIP} -9c $@.bin > $@.bin.gz; \
${TOOL_GZIP} -9c $@.bin > $@.bin.gz; \
echo ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_GZ} $@.bin.gz $@.gz.ub; \
${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_GZ} $@.bin.gz $@.gz.ub; \
echo ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_NONE} $@.bin $@.ub; \
${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_NONE} $@.bin $@.ub; \
echo
EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.bin@}
EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.ub@}
EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.bin.gz@}
EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.gz.ub@}

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# $NetBSD: std.virt,v 1.1 2018/06/14 10:56:39 jmcneill Exp $
#
# standard NetBSD/evbarm for VIRT options
machine evbarm arm
include "arch/evbarm/conf/std.evbarm"
# Pull in VIRT config definitions
include "arch/evbarm/conf/files.virt"
options FDT # Flattened Device Tree support
options DRAM_BLOCKS=256
options MODULAR
options MODULAR_DEFAULT_AUTOLOAD
options ARM_HAS_VBAR
options __HAVE_CPU_COUNTER
options __HAVE_CPU_UAREA_ALLOC_IDLELWP
options __HAVE_FAST_SOFTINTS # should be in types.h
#options __HAVE_MM_MD_DIRECT_MAPPED_PHYS
options TPIDRPRW_IS_CURCPU
options KERNEL_BASE_EXT=0x80000000
options FPU_VFP
makeoptions KERNEL_BASE_PHYS="0x40000000"
makeoptions KERNEL_BASE_VIRT="0x40000000"
makeoptions BOARDTYPE="virt"
makeoptions BOARDMKFRAG="${THISARM}/conf/mk.virt"
makeoptions CPUFLAGS="-mcpu=cortex-a15 -mfpu=neon"
options ARM_INTR_IMPL="<arch/arm/fdt/fdt_intr.h>"
options ARM_GENERIC_TODR
# initrd support
options MEMORY_DISK_HOOKS
options MEMORY_DISK_DYNAMIC
pseudo-device md

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/* $NetBSD: virt_start.S,v 1.1 2018/06/14 10:56:39 jmcneill Exp $ */
/*-
* Copyright (c) 2015 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Sergio L. Pascual.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "opt_cpuoptions.h"
#include "opt_cputypes.h"
#include "opt_multiprocessor.h"
#include "opt_arm_debug.h"
#include "opt_fdt.h"
#include <arm/asm.h>
#include <arm/armreg.h>
#include "assym.h"
#include <arm/virt/virt_platform.h>
RCSID("$NetBSD: virt_start.S,v 1.1 2018/06/14 10:56:39 jmcneill Exp $")
#ifdef VERBOSE_INIT_ARM
#define XPUTC(n) mov r0, n; bl xputc
#define XPUTC2(n) mov r0, n; blx r11
#else
#define XPUTC(n)
#define XPUTC2(n)
#endif
#define INIT_MEMSIZE 64
#define TEMP_L1_TABLE (KERNEL_BASE - KERNEL_BASE_VOFFSET + INIT_MEMSIZE * L1_S_SIZE - L1_TABLE_SIZE)
#define MD_CPU_HATCH _C_LABEL(arm_fdt_cpu_hatch)
/*
* Kernel start routine for Versatile Express boards running on uboot firmware
* At this point, this code has been loaded into SDRAM
* and the MMU is off
*/
.section .start,"ax",%progbits
.global _C_LABEL(virt_start)
_C_LABEL(virt_start):
#ifdef __ARMEB__
setend be /* force big endian */
#endif
/* Move into supervisor mode and disable IRQs/FIQs. */
cpsid if, #PSR_SVC32_MODE
/* Save any arguments passed to us. */
movw r4, #:lower16:uboot_args
movt r4, #:upper16:uboot_args
sub r4, r4, #KERNEL_BASE_VOFFSET
stmia r4, {r0-r3}
#ifdef FDT
/*
* ARM boot protocol has FDT address in r2
*/
movw r4, #:lower16:fdt_addr_r
movt r4, #:upper16:fdt_addr_r
sub r4, r4, #KERNEL_BASE_VOFFSET
str r2, [r4]
#endif
/* Add DTB PA (1MB) from r2 to MMU init table */
movw r3, #:lower16:(L1_S_SIZE - 1) /* align DTB PA to 1M */
movt r3, #:upper16:(L1_S_SIZE - 1)
bic r0, r2, r3
orr r0, r0, #1 /* 1MB mapping */
bic r1, r2, r3
movw r3, #:lower16:(L1_S_PROTO_armv7|L1_S_APv7_KRW|L1_S_CACHEABLE)
movt r3, #:upper16:(L1_S_PROTO_armv7|L1_S_APv7_KRW|L1_S_CACHEABLE)
orr r1, r1, r3
adr r3, .Lmmu_init_table_dtb /* table entry addr */
stmia r3, {r0-r1} /* patch table entry */
XPUTC('a')
bl cortex_init
XPUTC('b')
/*
* Set up a preliminary mapping in the MMU to allow us to run
* at KERNEL_BASE with caches on.
*/
adr r1, .Lmmu_init_table
movw r0, #:lower16:TEMP_L1_TABLE
movt r0, #:upper16:TEMP_L1_TABLE
bl arm_boot_l1pt_init
XPUTC('c')
adr r11, xputc
movw lr, #:lower16:1f
movt lr, #:upper16:1f
movw r0, #:lower16:TEMP_L1_TABLE
movt r0, #:upper16:TEMP_L1_TABLE
b arm_cpuinit
.pushsection .text, "ax", %progbits
.align 0
1:
XPUTC2('d')
b start
.popsection
.align 0
.global xputc
.type xputc,%function
xputc:
movw r2, #0x0000
movt r2, #0x1c09
str r0, [r2]
bx lr
#include <arm/cortex/a9_mpsubr.S>
.align 0
.Lmmu_init_table:
/* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable, shareable */
MMU_INIT(KERNEL_BASE, KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
#if KERNEL_BASE_VOFFSET
/* Map physical addresses of kernel 1:1 PA:VA write-back cacheable, shareable */
MMU_INIT(KERNEL_BASE - KERNEL_BASE_VOFFSET,
KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
#endif
/* Map VIRT CORE (so console will work) */
MMU_INIT(VIRT_CORE_VBASE, VIRT_CORE_PBASE,
VIRT_CORE_SIZE / L1_S_SIZE,
L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
/* Map VIRT CORE (so console will work) */
MMU_INIT(VIRT_CORE_PBASE, VIRT_CORE_PBASE,
VIRT_CORE_SIZE / L1_S_SIZE,
L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
/* Map DTB location in SDRAM, patched in later */
.Lmmu_init_table_dtb:
MMU_INIT(0, 0, 0, 0)
/* end of table */
MMU_INIT(0, 0, 0, 0)
END(virt_start)